| --- a/arch/mips/ralink/mt7621.c | 
 | +++ b/arch/mips/ralink/mt7621.c | 
 | @@ -58,7 +58,9 @@ | 
 |  #define MT7621_GPIO_MODE_SDHCI_SHIFT	18 | 
 |  #define MT7621_GPIO_MODE_SDHCI_GPIO	1 | 
 |   | 
 | -static void *detect_magic __initdata = detect_memory_region; | 
 | +#define MT7621_MEM_TEST_PATTERN         0xaa5555aa | 
 | + | 
 | +static u32 detect_magic __initdata; | 
 |   | 
 |  static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) }; | 
 |  static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) }; | 
 | @@ -144,26 +146,34 @@ static struct clk *__init mt7621_add_sys | 
 |  	return clk; | 
 |  } | 
 |   | 
 | +static bool __init mt7621_addr_wraparound_test(phys_addr_t size) | 
 | +{ | 
 | +	void *dm = (void *)KSEG1ADDR(&detect_magic); | 
 | +	if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE) | 
 | +		return true; | 
 | +	__raw_writel(MT7621_MEM_TEST_PATTERN, dm); | 
 | +	if (__raw_readl(dm) != __raw_readl(dm + size)) | 
 | +		return false; | 
 | +	__raw_writel(!MT7621_MEM_TEST_PATTERN, dm); | 
 | +	return __raw_readl(dm) == __raw_readl(dm + size); | 
 | +} | 
 | + | 
 |  void __init mt7621_memory_detect(void) | 
 |  { | 
 | -	void *dm = &detect_magic; | 
 |  	phys_addr_t size; | 
 |   | 
 | -	for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) { | 
 | -		if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic))) | 
 | -			break; | 
 | +	for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) { | 
 | +		if (mt7621_addr_wraparound_test(size)) { | 
 | +			add_memory_region(MT7621_LOWMEM_BASE, size, BOOT_MEM_RAM); | 
 | +			return; | 
 | +		} | 
 |  	} | 
 |   | 
 | -	if ((size == 256 * SZ_1M) && | 
 | -	    (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) && | 
 | -	    __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) { | 
 | -		add_memory_region(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE, | 
 | -				  BOOT_MEM_RAM); | 
 | -		add_memory_region(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE, | 
 | -				  BOOT_MEM_RAM); | 
 | -	} else { | 
 | -		add_memory_region(MT7621_LOWMEM_BASE, size, BOOT_MEM_RAM); | 
 | -	} | 
 | +	/* addr doesn't wrap around at dm + 256M, assume 512M memory. */ | 
 | +	add_memory_region(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE, | 
 | +			  BOOT_MEM_RAM); | 
 | +	add_memory_region(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE, | 
 | +			  BOOT_MEM_RAM); | 
 |  } | 
 |   | 
 |  void __init ralink_clk_init(void) |