ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/external/subpack/devel/gcc/Config.in b/external/subpack/devel/gcc/Config.in
new file mode 100644
index 0000000..f435b45
--- /dev/null
+++ b/external/subpack/devel/gcc/Config.in
@@ -0,0 +1,34 @@
+# gcc library configuration
+menu "Libraries"
+ depends on PACKAGE_gcc
+ config INCLUDE_STATIC_LIBC
+ bool "Include static libc on target"
+ help
+ Copies libc.a to target device
+ Increases the size of an already
+ very large package
+ default n
+ config INCLUDE_STATIC_LIBPTHREAD
+ bool "Include static libptread on target"
+ help
+ Copies libpthread.a to target device
+ Increases the size of an already
+ very large package
+ default n
+ config INCLUDE_STATIC_LIBSTDC
+ bool "Include static libstdc++ on target"
+ help
+ Copies libstdc++.a to target device
+ Increases the size of an already
+ very large package
+ default n
+ config INCLUDE_STATIC_LINK_SPEC
+ depends on INCLUDE_STATIC_LIBSTDC
+ bool "Generate spec file for easy static c++ linking on target"
+ help
+ Creates a spec file for gcc to eliminate the need for
+ -lstdc++, libgcc_pic and -static-libstdc flags when
+ statically linking c++ programs
+ default n
+endmenu
+
diff --git a/external/subpack/devel/gcc/Makefile b/external/subpack/devel/gcc/Makefile
new file mode 100644
index 0000000..9085a05
--- /dev/null
+++ b/external/subpack/devel/gcc/Makefile
@@ -0,0 +1,248 @@
+#
+# Copyright (C) 2002-2003 Erik Andersen <andersen@uclibc.org>
+# Copyright (C) 2004 Manuel Novoa III <mjn3@uclibc.org>
+# Copyright (C) 2005-2006 Felix Fietkau <nbd@nbd.name>
+# Copyright (C) 2006-2014 OpenWrt.org
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=gcc
+GCC_VERSION:=$(call qstrip,$(CONFIG_GCC_VERSION))
+PKG_VERSION:=$(firstword $(subst +, ,$(GCC_VERSION)))
+GCC_MAJOR_VERSION:=$(word 1,$(subst ., ,$(PKG_VERSION)))
+PKG_RELEASE:=7
+GCC_DIR:=$(PKG_NAME)-$(PKG_VERSION)
+
+PKG_SOURCE_URL:=@GNU/gcc/gcc-$(PKG_VERSION)
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
+PKG_INSTALL:=1
+PKG_FIXUP:=libtool
+PKG_BUILD_PARALLEL:=1
+
+PKG_CPE_ID:=cpe:/a:gnu:gcc
+
+ifeq ($(PKG_VERSION),12.3.0)
+ PKG_HASH:=949a5d4f99e786421a93b532b22ffab5578de7321369975b91aec97adfda8c3b
+endif
+
+ifeq ($(PKG_VERSION),13.3.0)
+ PKG_HASH:=0845e9621c9543a13f484e94584a49ffc0129970e9914624235fc1d061a0c083
+endif
+
+ifeq ($(PKG_VERSION),14.2.0)
+ PKG_HASH:=a7b39bc69cbf9e25826c5a60ab26477001f7c08d85cec04bc0e29cabed6f3cc9
+endif
+
+PATCH_DIR:=patches-$(GCC_MAJOR_VERSION).x
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/gcc
+ SECTION:=devel
+ CATEGORY:=Development
+ TITLE:=gcc
+ MAINTAINER:=W. Michael Petullo <mike@flyn.org>
+ DEPENDS:= +binutils +libstdcpp +libzstd @!arc
+ MENU:=1
+endef
+
+define Package/gcc/config
+ source "$(SOURCE)/Config.in"
+endef
+
+ifeq ($(CONFIG_INCLUDE_STATIC_LIBC),y)
+ COPY_STATIC_LIBC=cp -a $(TOOLCHAIN_ROOT_DIR)/lib/libc.a $(1)/usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)
+endif
+
+ifeq ($(CONFIG_INCLUDE_STATIC_LIBPTHREAD),y)
+ COPY_STATIC_LIBPTHREAD=cp -a $(TOOLCHAIN_ROOT_DIR)/lib/libpthread.a $(1)/usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)
+endif
+
+ifeq ($(CONFIG_INCLUDE_STATIC_LIBSTDC),y)
+ COPY_STATIC_LIBSTDC=cp -a $(TOOLCHAIN_ROOT_DIR)/lib/libstdc++.a $(1)/usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)
+endif
+
+ifeq ($(CONFIG_INCLUDE_STATIC_LINK_SPEC),y)
+ INSTALL_STATIC_SPEC=g++ -dumpspecs |sed s/--start-group}\ %G\ %L\ /--start-group}\ %G\ %L\ -lstdc++\ -lgcc_pic\ / >/usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)/specs
+ REMOVE_STATIC_SPEC=rm /usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)/specs
+endif
+
+TARGET_LANGUAGES:="c,c++"
+BUGURL=https://dev.openwrt.org/
+PKGVERSION=OpenWrt GCC $(PKG_VERSION)
+TARGET_CPPFLAGS += -D_GLIBCXX_INCLUDE_NEXT_C_HEADERS
+
+# not using sstrip here as this messes up the .so's somehow
+STRIP:=$(firstword $(TOOLCHAIN_BIN_DIRS))/$(TARGET_CROSS)strip
+RSTRIP:= \
+ NM="$(firstword $(TOOLCHAIN_BIN_DIRS))/$(TARGET_CROSS)nm" \
+ STRIP="$(STRIP)" \
+ STRIP_KMOD="$(STRIP) --strip-debug" \
+ $(SCRIPT_DIR)/rstrip.sh
+
+ifneq ($(CONFIG_SOFT_FLOAT),y)
+ ifeq ($(CONFIG_arm),y)
+ ARM_FLOAT_OPTION:= --with-float=hard
+ endif
+endif
+
+GMPSRC=gmp-6.1.0
+
+define Download/gmp
+ URL:=ftp://gcc.gnu.org/pub/gcc/infrastructure/
+ FILE:=$(GMPSRC).tar.bz2
+ HASH:=498449a994efeba527885c10405993427995d3f86b8768d8cdf8d9dd7c6b73e8
+endef
+$(eval $(call Download,gmp))
+
+MPCSRC=mpc-1.0.3
+
+define Download/mpc
+ URL:=ftp://gcc.gnu.org/pub/gcc/infrastructure/
+ FILE:=$(MPCSRC).tar.gz
+ HASH:=617decc6ea09889fb08ede330917a00b16809b8db88c29c31bfbb49cbf88ecc3
+endef
+$(eval $(call Download,mpc))
+
+MPFRSRC=mpfr-3.1.4
+
+define Download/mpfr
+ URL:=ftp://gcc.gnu.org/pub/gcc/infrastructure/
+ FILE:=$(MPFRSRC).tar.bz2
+ HASH:=d3103a80cdad2407ed581f3618c4bed04e0c92d1cf771a65ead662cc397f7775
+endef
+$(eval $(call Download,mpfr))
+
+define Build/Prepare
+ $(PKG_UNPACK)
+# we have to download and unpack additional stuff before patching
+ tar -C $(PKG_BUILD_DIR) -xvjf $(DL_DIR)/$(GMPSRC).tar.bz2
+ ln -sf $(PKG_BUILD_DIR)/$(GMPSRC) $(PKG_BUILD_DIR)/gmp
+ tar -C $(PKG_BUILD_DIR) -xvzf $(DL_DIR)/$(MPCSRC).tar.gz
+ ln -sf $(PKG_BUILD_DIR)/$(MPCSRC) $(PKG_BUILD_DIR)/mpc
+ tar -C $(PKG_BUILD_DIR) -xvjf $(DL_DIR)/$(MPFRSRC).tar.bz2
+ ln -sf $(PKG_BUILD_DIR)/$(MPFRSRC) $(PKG_BUILD_DIR)/mpfr
+ $(Build/Patch)
+# poor man's fix for `none-openwrt-linux' not recognized when building with musl
+ cp $(PKG_BUILD_DIR)/config.sub $(PKG_BUILD_DIR)/mpfr/
+ cp $(PKG_BUILD_DIR)/config.sub $(PKG_BUILD_DIR)/gmp/
+ chmod u+w $(PKG_BUILD_DIR)/mpc/config.sub
+ cp $(PKG_BUILD_DIR)/config.sub $(PKG_BUILD_DIR)/mpc/
+endef
+
+CONFIGURE_ARGS += CXXFLAGS_FOR_TARGET="-g -O2 -D_GLIBCXX_INCLUDE_NEXT_C_HEADERS"
+
+define Build/Configure
+ (cd $(PKG_BUILD_DIR); rm -f config.cache; \
+ SHELL="$(BASH)" \
+ $(TARGET_CONFIGURE_OPTS) \
+ $(PKG_BUILD_DIR)/configure \
+ $(CONFIGURE_ARGS) \
+ --build=$(GNU_HOST_NAME) \
+ --host=$(REAL_GNU_TARGET_NAME) \
+ --target=$(REAL_GNU_TARGET_NAME) \
+ --enable-languages=$(TARGET_LANGUAGES) \
+ --with-bugurl=$(BUGURL) \
+ --with-pkgversion="$(PKGVERSION)" \
+ --enable-shared \
+ $(if $(CONFIG_LIBC_USE_GLIBC),--enable,--disable)-__cxa_atexit \
+ --with-default-libstdcxx-abi=gcc4-compatible \
+ --enable-target-optspace \
+ --with-gnu-ld \
+ --disable-nls \
+ --disable-libsanitizer \
+ --disable-libvtv \
+ --disable-libcilkrts \
+ --disable-libmudflap \
+ --disable-libmpx \
+ --disable-multilib \
+ --disable-libgomp \
+ --disable-libquadmath \
+ --disable-libssp \
+ --disable-decimal-float \
+ --disable-libstdcxx-pch \
+ --with-host-libstdcxx=-lstdc++ \
+ --prefix=/usr \
+ --libexecdir=/usr/lib \
+ --with-local-prefix=/usr \
+ --with-stage1-ldflags=-lstdc++ \
+ $(ARM_FLOAT_OPTION) \
+ $(SOFT_FLOAT_CONFIG_OPTION) \
+ $(call qstrip,$(CONFIG_EXTRA_GCC_CONFIG_OPTIONS)) \
+ );
+endef
+
+define Build/Compile
+ export SHELL="$(BASH)"; $(MAKE_VARS) $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
+ DESTDIR="$(PKG_INSTALL_DIR)" $(MAKE_ARGS) all
+ export SHELL="$(BASH)"; $(MAKE_VARS) $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
+ DESTDIR="$(PKG_INSTALL_DIR)" $(MAKE_ARGS) install
+endef
+
+ENVCFLAGS:="$(TARGET_OPTIMIZATION) $(EXTRA_OPTIMIZATION)
+ifeq ($(CONFIG_SOFT_FLOAT),y)
+ ifeq ($(CONFIG_arm),y)
+ ENVCFLAGS+= -mfloat-abi=soft
+ else
+ ENVCFLAGS+= -msoft-float
+ endif
+endif
+ENVCFLAGS+="
+
+ENVLDFLAGS:="-Wl,-rpath=/usr/lib -Wl,--dynamic-linker=/usr/lib/$(DYNLINKER) -L/usr/lib, -lstdc++"
+
+define Package/gcc/install
+ $(INSTALL_DIR) $(1)/usr/bin $(1)/usr/lib $(1)/usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)
+ cp -ar $(PKG_INSTALL_DIR)/usr/include $(1)/usr
+ cp -a $(PKG_INSTALL_DIR)/usr/bin/{$(REAL_GNU_TARGET_NAME)-{g++,gcc},cpp,gcov} $(1)/usr/bin
+ ln -s $(REAL_GNU_TARGET_NAME)-g++ $(1)/usr/bin/c++
+ ln -s $(REAL_GNU_TARGET_NAME)-g++ $(1)/usr/bin/g++
+ ln -s $(REAL_GNU_TARGET_NAME)-g++ $(1)/usr/bin/$(REAL_GNU_TARGET_NAME)-c++
+ ln -s $(REAL_GNU_TARGET_NAME)-gcc $(1)/usr/bin/gcc
+ ln -s $(REAL_GNU_TARGET_NAME)-gcc $(1)/usr/bin/cc
+ ln -s $(REAL_GNU_TARGET_NAME)-gcc $(1)/usr/bin/$(REAL_GNU_TARGET_NAME)-gcc-$(PKG_VERSION)
+ cp -ar $(PKG_INSTALL_DIR)/usr/lib/gcc $(1)/usr/lib
+ cp -ar $(TOOLCHAIN_ROOT_DIR)/include $(1)/usr
+ cp -a $(TOOLCHAIN_ROOT_DIR)/lib/*.{o,so*} $(1)/usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)
+ cp -a $(TOOLCHAIN_ROOT_DIR)/lib/*nonshared*.a $(1)/usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)
+ cp -a $(TOOLCHAIN_ROOT_DIR)/lib/libm.a $(1)/usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)
+ $(COPY_STATIC_LIBC)
+ $(COPY_STATIC_LIBPTHREAD)
+ $(COPY_STATIC_LIBSTDC)
+ rm -f $(1)/usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)/libgo*
+ rm -f $(1)/usr/lib/$(PKG_NAME)/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION)/libcc1*
+ echo '#!/bin/sh' > $(1)/usr/bin/gcc_env.sh
+ echo 'export LDFLAGS=$(ENVLDFLAGS)' >> $(1)/usr/bin/gcc_env.sh
+ echo 'export CFLAGS=$(ENVCFLAGS)' >> $(1)/usr/bin/gcc_env.sh
+ chmod +x $(1)/usr/bin/gcc_env.sh
+endef
+
+ifeq ($(CONFIG_INCLUDE_STATIC_LINK_SPEC),y)
+define Package/gcc/postinst
+#!/bin/sh
+
+$(INSTALL_STATIC_SPEC)
+endef
+
+define Package/gcc/postrm
+#!/bin/sh
+
+$(REMOVE_STATIC_SPEC)
+endef
+endif
+
+$(eval $(call BuildPackage,gcc))
diff --git a/external/subpack/devel/gcc/README b/external/subpack/devel/gcc/README
new file mode 100644
index 0000000..06ace1a
--- /dev/null
+++ b/external/subpack/devel/gcc/README
@@ -0,0 +1,10 @@
+Native GCC that runs on target.
+
+To save disk space, this GCC uses dynamic linking on the target box. There
+are configuration options to include libstdc++.a, libc.a and libpthread.a
+if staticly linked binaries are needed.
+
+For now, this was only tested on arm (EABI) and mips targets. Others to be
+done...
+
+ Christian Beier <cb@shoutrlabs.com>
diff --git a/external/subpack/devel/gcc/patches-12.x/002-case_insensitive.patch b/external/subpack/devel/gcc/patches-12.x/002-case_insensitive.patch
new file mode 100644
index 0000000..409497e
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/002-case_insensitive.patch
@@ -0,0 +1,24 @@
+commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun Oct 19 21:45:51 2014 +0000
+
+ gcc: do not assume that the Mac OS X filesystem is case insensitive
+
+ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+
+ SVN-Revision: 42973
+
+--- a/include/filenames.h
++++ b/include/filenames.h
+@@ -44,11 +44,6 @@ extern "C" {
+ # define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c)
+ # define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f)
+ #else /* not DOSish */
+-# if defined(__APPLE__)
+-# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM
+-# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1
+-# endif
+-# endif /* __APPLE__ */
+ # define HAS_DRIVE_SPEC(f) (0)
+ # define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c)
+ # define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f)
diff --git a/external/subpack/devel/gcc/patches-12.x/003-dont-choke-when-building-32bit-on-64bit.patch b/external/subpack/devel/gcc/patches-12.x/003-dont-choke-when-building-32bit-on-64bit.patch
new file mode 100644
index 0000000..c41f35e
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/003-dont-choke-when-building-32bit-on-64bit.patch
@@ -0,0 +1,13 @@
+--- a/gcc/real.h
++++ b/gcc/real.h
+@@ -77,8 +77,10 @@ struct GTY(()) real_value {
+ + (REAL_VALUE_TYPE_SIZE%HOST_BITS_PER_WIDE_INT ? 1 : 0)) /* round up */
+
+ /* Verify the guess. */
++#ifndef __LP64__
+ extern char test_real_width
+ [sizeof (REAL_VALUE_TYPE) <= REAL_WIDTH * sizeof (HOST_WIDE_INT) ? 1 : -1];
++#endif
+
+ /* Calculate the format for CONST_DOUBLE. We need as many slots as
+ are necessary to overlay a REAL_VALUE_TYPE on them. This could be
diff --git a/external/subpack/devel/gcc/patches-12.x/010-documentation.patch b/external/subpack/devel/gcc/patches-12.x/010-documentation.patch
new file mode 100644
index 0000000..39ee48e
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/010-documentation.patch
@@ -0,0 +1,35 @@
+commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2
+Author: Luka Perkov <luka@openwrt.org>
+Date: Tue Feb 26 16:16:33 2013 +0000
+
+ gcc: don't build documentation
+
+ This closes #13039.
+
+ Signed-off-by: Luka Perkov <luka@openwrt.org>
+
+ SVN-Revision: 35807
+
+--- a/gcc/Makefile.in
++++ b/gcc/Makefile.in
+@@ -3366,18 +3366,10 @@ doc/gcc.info: $(TEXI_GCC_FILES)
+ doc/gccint.info: $(TEXI_GCCINT_FILES)
+ doc/cppinternals.info: $(TEXI_CPPINT_FILES)
+
+-doc/%.info: %.texi
+- if [ x$(BUILD_INFO) = xinfo ]; then \
+- $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \
+- -I $(gcc_docdir)/include -o $@ $<; \
+- fi
++doc/%.info:
+
+ # Duplicate entry to handle renaming of gccinstall.info
+-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES)
+- if [ x$(BUILD_INFO) = xinfo ]; then \
+- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
+- -I $(gcc_docdir)/include -o $@ $<; \
+- fi
++doc/gccinstall.info:
+
+ doc/cpp.dvi: $(TEXI_CPP_FILES)
+ doc/gcc.dvi: $(TEXI_GCC_FILES)
diff --git a/external/subpack/devel/gcc/patches-12.x/110-Fix-MIPS-PR-84790.patch b/external/subpack/devel/gcc/patches-12.x/110-Fix-MIPS-PR-84790.patch
new file mode 100644
index 0000000..856fd6a
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/110-Fix-MIPS-PR-84790.patch
@@ -0,0 +1,20 @@
+Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.
+MIPS16 functions have a static assembler prologue which clobbers
+registers v0 and v1. Add these register clobbers to function call
+instructions.
+
+--- a/gcc/config/mips/mips.cc
++++ b/gcc/config/mips/mips.cc
+@@ -3134,6 +3134,12 @@ mips_emit_call_insn (rtx pattern, rtx or
+ emit_insn (gen_update_got_version ());
+ }
+
++ if (TARGET_MIPS16 && TARGET_USE_GOT)
++ {
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));
++ }
++
+ if (TARGET_MIPS16
+ && TARGET_EXPLICIT_RELOCS
+ && TARGET_CALL_CLOBBERED_GP)
diff --git a/external/subpack/devel/gcc/patches-12.x/230-musl_libssp.patch b/external/subpack/devel/gcc/patches-12.x/230-musl_libssp.patch
new file mode 100644
index 0000000..a909d63
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/230-musl_libssp.patch
@@ -0,0 +1,13 @@
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -987,7 +987,9 @@ proper position among the other output f
+ #endif
+
+ #ifndef LINK_SSP_SPEC
+-#ifdef TARGET_LIBC_PROVIDES_SSP
++#if DEFAULT_LIBC == LIBC_MUSL
++#define LINK_SSP_SPEC "-lssp_nonshared"
++#elif defined(TARGET_LIBC_PROVIDES_SSP)
+ #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
+ "|fstack-protector-strong|fstack-protector-explicit:}"
+ #else
diff --git a/external/subpack/devel/gcc/patches-12.x/300-mips_Os_cpu_rtx_cost_model.patch b/external/subpack/devel/gcc/patches-12.x/300-mips_Os_cpu_rtx_cost_model.patch
new file mode 100644
index 0000000..1d223f2
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/300-mips_Os_cpu_rtx_cost_model.patch
@@ -0,0 +1,21 @@
+commit ecf7671b769fe96f7b5134be442089f8bdba55d2
+Author: Felix Fietkau <nbd@nbd.name>
+Date: Thu Aug 4 20:29:45 2016 +0200
+
+gcc: add a patch to generate better code with Os on mips
+
+Also happens to reduce compressed code size a bit
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+
+--- a/gcc/config/mips/mips.cc
++++ b/gcc/config/mips/mips.cc
+@@ -20216,7 +20216,7 @@ mips_option_override (void)
+ flag_pcc_struct_return = 0;
+
+ /* Decide which rtx_costs structure to use. */
+- if (optimize_size)
++ if (0 && optimize_size)
+ mips_cost = &mips_rtx_cost_optimize_size;
+ else
+ mips_cost = &mips_rtx_cost_data[mips_tune];
diff --git a/external/subpack/devel/gcc/patches-12.x/700-RISCV-Inline-subword-atomic-ops.patch b/external/subpack/devel/gcc/patches-12.x/700-RISCV-Inline-subword-atomic-ops.patch
new file mode 100644
index 0000000..b164c76
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/700-RISCV-Inline-subword-atomic-ops.patch
@@ -0,0 +1,2021 @@
+From f797260adaf52bee0ec0e16190bbefbe1bfc3692 Mon Sep 17 00:00:00 2001
+From: Patrick O'Neill <patrick@rivosinc.com>
+Date: Tue, 18 Apr 2023 14:33:13 -0700
+Subject: [PATCH] RISCV: Inline subword atomic ops
+
+RISC-V has no support for subword atomic operations; code currently
+generates libatomic library calls.
+
+This patch changes the default behavior to inline subword atomic calls
+(using the same logic as the existing library call).
+Behavior can be specified using the -minline-atomics and
+-mno-inline-atomics command line flags.
+
+gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm.
+This will need to stay for backwards compatibility and the
+-mno-inline-atomics flag.
+
+2023-04-18 Patrick O'Neill <patrick@rivosinc.com>
+
+gcc/ChangeLog:
+ PR target/104338
+ * config/riscv/riscv-protos.h: Add helper function stubs.
+ * config/riscv/riscv.cc: Add helper functions for subword masking.
+ * config/riscv/riscv.opt: Add command-line flag.
+ * config/riscv/sync.md: Add masking logic and inline asm for fetch_and_op,
+ fetch_and_nand, CAS, and exchange ops.
+ * doc/invoke.texi: Add blurb regarding command-line flag.
+
+libgcc/ChangeLog:
+ PR target/104338
+ * config/riscv/atomic.c: Add reference to duplicate logic.
+
+gcc/testsuite/ChangeLog:
+ PR target/104338
+ * gcc.target/riscv/inline-atomics-1.c: New test.
+ * gcc.target/riscv/inline-atomics-2.c: New test.
+ * gcc.target/riscv/inline-atomics-3.c: New test.
+ * gcc.target/riscv/inline-atomics-4.c: New test.
+ * gcc.target/riscv/inline-atomics-5.c: New test.
+ * gcc.target/riscv/inline-atomics-6.c: New test.
+ * gcc.target/riscv/inline-atomics-7.c: New test.
+ * gcc.target/riscv/inline-atomics-8.c: New test.
+
+Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+---
+ gcc/config/riscv/riscv-protos.h | 2 +
+ gcc/config/riscv/riscv.cc | 49 ++
+ gcc/config/riscv/riscv.opt | 4 +
+ gcc/config/riscv/sync.md | 301 +++++++++
+ gcc/doc/invoke.texi | 10 +-
+ .../gcc.target/riscv/inline-atomics-1.c | 18 +
+ .../gcc.target/riscv/inline-atomics-2.c | 9 +
+ .../gcc.target/riscv/inline-atomics-3.c | 569 ++++++++++++++++++
+ .../gcc.target/riscv/inline-atomics-4.c | 566 +++++++++++++++++
+ .../gcc.target/riscv/inline-atomics-5.c | 87 +++
+ .../gcc.target/riscv/inline-atomics-6.c | 87 +++
+ .../gcc.target/riscv/inline-atomics-7.c | 69 +++
+ .../gcc.target/riscv/inline-atomics-8.c | 69 +++
+ libgcc/config/riscv/atomic.c | 2 +
+ 14 files changed, 1841 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-1.c
+ create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-2.c
+ create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-3.c
+ create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-4.c
+ create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-5.c
+ create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-6.c
+ create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-7.c
+ create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-8.c
+
+--- a/gcc/config/riscv/riscv-protos.h
++++ b/gcc/config/riscv/riscv-protos.h
+@@ -74,6 +74,8 @@ extern bool riscv_expand_block_move (rtx
+ extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
+ extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
+ extern bool riscv_gpr_save_operation_p (rtx);
++extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
++extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *);
+
+ /* Routines implemented in riscv-c.cc. */
+ void riscv_cpu_cpp_builtins (cpp_reader *);
+--- a/gcc/config/riscv/riscv.cc
++++ b/gcc/config/riscv/riscv.cc
+@@ -5605,6 +5605,55 @@ riscv_asan_shadow_offset (void)
+ return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
+ }
+
++/* Given memory reference MEM, expand code to compute the aligned
++ memory address, shift and mask values and store them into
++ *ALIGNED_MEM, *SHIFT, *MASK and *NOT_MASK. */
++
++void
++riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask,
++ rtx *not_mask)
++{
++ /* Align the memory address to a word. */
++ rtx addr = force_reg (Pmode, XEXP (mem, 0));
++
++ rtx addr_mask = gen_int_mode (-4, Pmode);
++
++ rtx aligned_addr = gen_reg_rtx (Pmode);
++ emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, addr_mask));
++
++ *aligned_mem = change_address (mem, SImode, aligned_addr);
++
++ /* Calculate the shift amount. */
++ emit_move_insn (*shift, gen_rtx_AND (SImode, gen_lowpart (SImode, addr),
++ gen_int_mode (3, SImode)));
++ emit_move_insn (*shift, gen_rtx_ASHIFT (SImode, *shift,
++ gen_int_mode (3, SImode)));
++
++ /* Calculate the mask. */
++ int unshifted_mask = GET_MODE_MASK (GET_MODE (mem));
++
++ emit_move_insn (*mask, gen_int_mode (unshifted_mask, SImode));
++
++ emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask,
++ gen_lowpart (QImode, *shift)));
++
++ emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask));
++}
++
++/* Leftshift a subword within an SImode register. */
++
++void
++riscv_lshift_subword (machine_mode mode, rtx value, rtx shift,
++ rtx *shifted_value)
++{
++ rtx value_reg = gen_reg_rtx (SImode);
++ emit_move_insn (value_reg, simplify_gen_subreg (SImode, value,
++ mode, 0));
++
++ emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg,
++ gen_lowpart (QImode, shift)));
++}
++
+ /* Initialize the GCC target structure. */
+ #undef TARGET_ASM_ALIGNED_HI_OP
+ #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
+--- a/gcc/config/riscv/riscv.opt
++++ b/gcc/config/riscv/riscv.opt
+@@ -209,6 +209,10 @@ int riscv_vector_elen_flags
+ TargetVariable
+ int riscv_zvl_flags
+
++minline-atomics
++Target Var(TARGET_INLINE_SUBWORD_ATOMIC) Init(1)
++Always inline subword atomic operations.
++
+ Enum
+ Name(isa_spec_class) Type(enum riscv_isa_spec_class)
+ Supported ISA specs (for use with the -misa-spec= option):
+--- a/gcc/config/riscv/sync.md
++++ b/gcc/config/riscv/sync.md
+@@ -21,8 +21,11 @@
+
+ (define_c_enum "unspec" [
+ UNSPEC_COMPARE_AND_SWAP
++ UNSPEC_COMPARE_AND_SWAP_SUBWORD
+ UNSPEC_SYNC_OLD_OP
++ UNSPEC_SYNC_OLD_OP_SUBWORD
+ UNSPEC_SYNC_EXCHANGE
++ UNSPEC_SYNC_EXCHANGE_SUBWORD
+ UNSPEC_ATOMIC_STORE
+ UNSPEC_MEMORY_BARRIER
+ ])
+@@ -92,6 +95,135 @@
+ "%F3amo<insn>.<amo>%A3 %0,%z2,%1"
+ [(set (attr "length") (const_int 8))])
+
++(define_insn "subword_atomic_fetch_strong_<atomic_optab>"
++ [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem
++ (match_operand:SI 1 "memory_operand" "+A")) ;; mem location
++ (set (match_dup 1)
++ (unspec_volatile:SI
++ [(any_atomic:SI (match_dup 1)
++ (match_operand:SI 2 "register_operand" "rI")) ;; value for op
++ (match_operand:SI 3 "register_operand" "rI")] ;; mask
++ UNSPEC_SYNC_OLD_OP_SUBWORD))
++ (match_operand:SI 4 "register_operand" "rI") ;; not_mask
++ (clobber (match_scratch:SI 5 "=&r")) ;; tmp_1
++ (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_2
++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
++ {
++ return "1:\;"
++ "lr.w.aq\t%0, %1\;"
++ "<insn>\t%5, %0, %2\;"
++ "and\t%5, %5, %3\;"
++ "and\t%6, %0, %4\;"
++ "or\t%6, %6, %5\;"
++ "sc.w.rl\t%5, %6, %1\;"
++ "bnez\t%5, 1b";
++ }
++ [(set (attr "length") (const_int 28))])
++
++(define_expand "atomic_fetch_nand<mode>"
++ [(match_operand:SHORT 0 "register_operand") ;; old value at mem
++ (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location
++ (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op
++ (match_operand:SI 3 "const_int_operand")] ;; model
++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
++{
++ /* We have no QImode/HImode atomics, so form a mask, then use
++ subword_atomic_fetch_strong_nand to implement a LR/SC version of the
++ operation. */
++
++ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
++ is disabled */
++
++ rtx old = gen_reg_rtx (SImode);
++ rtx mem = operands[1];
++ rtx value = operands[2];
++ rtx aligned_mem = gen_reg_rtx (SImode);
++ rtx shift = gen_reg_rtx (SImode);
++ rtx mask = gen_reg_rtx (SImode);
++ rtx not_mask = gen_reg_rtx (SImode);
++
++ riscv_subword_address (mem, &aligned_mem, &shift, &mask, ¬_mask);
++
++ rtx shifted_value = gen_reg_rtx (SImode);
++ riscv_lshift_subword (<MODE>mode, value, shift, &shifted_value);
++
++ emit_insn (gen_subword_atomic_fetch_strong_nand (old, aligned_mem,
++ shifted_value,
++ mask, not_mask));
++
++ emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
++ gen_lowpart (QImode, shift)));
++
++ emit_move_insn (operands[0], gen_lowpart (<MODE>mode, old));
++
++ DONE;
++})
++
++(define_insn "subword_atomic_fetch_strong_nand"
++ [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem
++ (match_operand:SI 1 "memory_operand" "+A")) ;; mem location
++ (set (match_dup 1)
++ (unspec_volatile:SI
++ [(not:SI (and:SI (match_dup 1)
++ (match_operand:SI 2 "register_operand" "rI"))) ;; value for op
++ (match_operand:SI 3 "register_operand" "rI")] ;; mask
++ UNSPEC_SYNC_OLD_OP_SUBWORD))
++ (match_operand:SI 4 "register_operand" "rI") ;; not_mask
++ (clobber (match_scratch:SI 5 "=&r")) ;; tmp_1
++ (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_2
++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
++ {
++ return "1:\;"
++ "lr.w.aq\t%0, %1\;"
++ "and\t%5, %0, %2\;"
++ "not\t%5, %5\;"
++ "and\t%5, %5, %3\;"
++ "and\t%6, %0, %4\;"
++ "or\t%6, %6, %5\;"
++ "sc.w.rl\t%5, %6, %1\;"
++ "bnez\t%5, 1b";
++ }
++ [(set (attr "length") (const_int 32))])
++
++(define_expand "atomic_fetch_<atomic_optab><mode>"
++ [(match_operand:SHORT 0 "register_operand") ;; old value at mem
++ (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location
++ (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op
++ (match_operand:SI 3 "const_int_operand")] ;; model
++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
++{
++ /* We have no QImode/HImode atomics, so form a mask, then use
++ subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
++ operation. */
++
++ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
++ is disabled */
++
++ rtx old = gen_reg_rtx (SImode);
++ rtx mem = operands[1];
++ rtx value = operands[2];
++ rtx aligned_mem = gen_reg_rtx (SImode);
++ rtx shift = gen_reg_rtx (SImode);
++ rtx mask = gen_reg_rtx (SImode);
++ rtx not_mask = gen_reg_rtx (SImode);
++
++ riscv_subword_address (mem, &aligned_mem, &shift, &mask, ¬_mask);
++
++ rtx shifted_value = gen_reg_rtx (SImode);
++ riscv_lshift_subword (<MODE>mode, value, shift, &shifted_value);
++
++ emit_insn (gen_subword_atomic_fetch_strong_<atomic_optab> (old, aligned_mem,
++ shifted_value,
++ mask, not_mask));
++
++ emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
++ gen_lowpart (QImode, shift)));
++
++ emit_move_insn (operands[0], gen_lowpart (<MODE>mode, old));
++
++ DONE;
++})
++
+ (define_insn "atomic_exchange<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&r")
+ (unspec_volatile:GPR
+@@ -104,6 +236,56 @@
+ "%F3amoswap.<amo>%A3 %0,%z2,%1"
+ [(set (attr "length") (const_int 8))])
+
++(define_expand "atomic_exchange<mode>"
++ [(match_operand:SHORT 0 "register_operand") ;; old value at mem
++ (match_operand:SHORT 1 "memory_operand") ;; mem location
++ (match_operand:SHORT 2 "register_operand") ;; value
++ (match_operand:SI 3 "const_int_operand")] ;; model
++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
++{
++ rtx old = gen_reg_rtx (SImode);
++ rtx mem = operands[1];
++ rtx value = operands[2];
++ rtx aligned_mem = gen_reg_rtx (SImode);
++ rtx shift = gen_reg_rtx (SImode);
++ rtx mask = gen_reg_rtx (SImode);
++ rtx not_mask = gen_reg_rtx (SImode);
++
++ riscv_subword_address (mem, &aligned_mem, &shift, &mask, ¬_mask);
++
++ rtx shifted_value = gen_reg_rtx (SImode);
++ riscv_lshift_subword (<MODE>mode, value, shift, &shifted_value);
++
++ emit_insn (gen_subword_atomic_exchange_strong (old, aligned_mem,
++ shifted_value, not_mask));
++
++ emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
++ gen_lowpart (QImode, shift)));
++
++ emit_move_insn (operands[0], gen_lowpart (<MODE>mode, old));
++ DONE;
++})
++
++(define_insn "subword_atomic_exchange_strong"
++ [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem
++ (match_operand:SI 1 "memory_operand" "+A")) ;; mem location
++ (set (match_dup 1)
++ (unspec_volatile:SI
++ [(match_operand:SI 2 "reg_or_0_operand" "rI") ;; value
++ (match_operand:SI 3 "reg_or_0_operand" "rI")] ;; not_mask
++ UNSPEC_SYNC_EXCHANGE_SUBWORD))
++ (clobber (match_scratch:SI 4 "=&r"))] ;; tmp_1
++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
++ {
++ return "1:\;"
++ "lr.w.aq\t%0, %1\;"
++ "and\t%4, %0, %3\;"
++ "or\t%4, %4, %2\;"
++ "sc.w.rl\t%4, %4, %1\;"
++ "bnez\t%4, 1b";
++ }
++ [(set (attr "length") (const_int 20))])
++
+ (define_insn "atomic_cas_value_strong<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=&r")
+ (match_operand:GPR 1 "memory_operand" "+A"))
+@@ -152,6 +334,125 @@
+ DONE;
+ })
+
++(define_expand "atomic_compare_and_swap<mode>"
++ [(match_operand:SI 0 "register_operand") ;; bool output
++ (match_operand:SHORT 1 "register_operand") ;; val output
++ (match_operand:SHORT 2 "memory_operand") ;; memory
++ (match_operand:SHORT 3 "reg_or_0_operand") ;; expected value
++ (match_operand:SHORT 4 "reg_or_0_operand") ;; desired value
++ (match_operand:SI 5 "const_int_operand") ;; is_weak
++ (match_operand:SI 6 "const_int_operand") ;; mod_s
++ (match_operand:SI 7 "const_int_operand")] ;; mod_f
++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
++{
++ emit_insn (gen_atomic_cas_value_strong<mode> (operands[1], operands[2],
++ operands[3], operands[4],
++ operands[6], operands[7]));
++
++ rtx val = gen_reg_rtx (SImode);
++ if (operands[1] != const0_rtx)
++ emit_move_insn (val, gen_rtx_SIGN_EXTEND (SImode, operands[1]));
++ else
++ emit_move_insn (val, const0_rtx);
++
++ rtx exp = gen_reg_rtx (SImode);
++ if (operands[3] != const0_rtx)
++ emit_move_insn (exp, gen_rtx_SIGN_EXTEND (SImode, operands[3]));
++ else
++ emit_move_insn (exp, const0_rtx);
++
++ rtx compare = val;
++ if (exp != const0_rtx)
++ {
++ rtx difference = gen_rtx_MINUS (SImode, val, exp);
++ compare = gen_reg_rtx (SImode);
++ emit_move_insn (compare, difference);
++ }
++
++ if (word_mode != SImode)
++ {
++ rtx reg = gen_reg_rtx (word_mode);
++ emit_move_insn (reg, gen_rtx_SIGN_EXTEND (word_mode, compare));
++ compare = reg;
++ }
++
++ emit_move_insn (operands[0], gen_rtx_EQ (SImode, compare, const0_rtx));
++ DONE;
++})
++
++(define_expand "atomic_cas_value_strong<mode>"
++ [(match_operand:SHORT 0 "register_operand") ;; val output
++ (match_operand:SHORT 1 "memory_operand") ;; memory
++ (match_operand:SHORT 2 "reg_or_0_operand") ;; expected value
++ (match_operand:SHORT 3 "reg_or_0_operand") ;; desired value
++ (match_operand:SI 4 "const_int_operand") ;; mod_s
++ (match_operand:SI 5 "const_int_operand") ;; mod_f
++ (match_scratch:SHORT 6)]
++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
++{
++ /* We have no QImode/HImode atomics, so form a mask, then use
++ subword_atomic_cas_strong<mode> to implement a LR/SC version of the
++ operation. */
++
++ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
++ is disabled */
++
++ rtx old = gen_reg_rtx (SImode);
++ rtx mem = operands[1];
++ rtx aligned_mem = gen_reg_rtx (SImode);
++ rtx shift = gen_reg_rtx (SImode);
++ rtx mask = gen_reg_rtx (SImode);
++ rtx not_mask = gen_reg_rtx (SImode);
++
++ riscv_subword_address (mem, &aligned_mem, &shift, &mask, ¬_mask);
++
++ rtx o = operands[2];
++ rtx n = operands[3];
++ rtx shifted_o = gen_reg_rtx (SImode);
++ rtx shifted_n = gen_reg_rtx (SImode);
++
++ riscv_lshift_subword (<MODE>mode, o, shift, &shifted_o);
++ riscv_lshift_subword (<MODE>mode, n, shift, &shifted_n);
++
++ emit_move_insn (shifted_o, gen_rtx_AND (SImode, shifted_o, mask));
++ emit_move_insn (shifted_n, gen_rtx_AND (SImode, shifted_n, mask));
++
++ emit_insn (gen_subword_atomic_cas_strong (old, aligned_mem,
++ shifted_o, shifted_n,
++ mask, not_mask));
++
++ emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
++ gen_lowpart (QImode, shift)));
++
++ emit_move_insn (operands[0], gen_lowpart (<MODE>mode, old));
++
++ DONE;
++})
++
++(define_insn "subword_atomic_cas_strong"
++ [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem
++ (match_operand:SI 1 "memory_operand" "+A")) ;; mem location
++ (set (match_dup 1)
++ (unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ") ;; expected value
++ (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;; desired value
++ UNSPEC_COMPARE_AND_SWAP_SUBWORD))
++ (match_operand:SI 4 "register_operand" "rI") ;; mask
++ (match_operand:SI 5 "register_operand" "rI") ;; not_mask
++ (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_1
++ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
++ {
++ return "1:\;"
++ "lr.w.aq\t%0, %1\;"
++ "and\t%6, %0, %4\;"
++ "bne\t%6, %z2, 1f\;"
++ "and\t%6, %0, %5\;"
++ "or\t%6, %6, %3\;"
++ "sc.w.rl\t%6, %6, %1\;"
++ "bnez\t%6, 1b\;"
++ "1:";
++ }
++ [(set (attr "length") (const_int 28))])
++
+ (define_expand "atomic_test_and_set"
+ [(match_operand:QI 0 "register_operand" "") ;; bool output
+ (match_operand:QI 1 "memory_operand" "+A") ;; memory
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -753,7 +753,8 @@ Objective-C and Objective-C++ Dialects}.
+ -moverride=@var{string} -mverbose-cost-dump @gol
+ -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{sysreg} @gol
+ -mstack-protector-guard-offset=@var{offset} -mtrack-speculation @gol
+--moutline-atomics }
++-moutline-atomics
++-minline-atomics -mno-inline-atomics}
+
+ @emph{Adapteva Epiphany Options}
+ @gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol
+@@ -28035,6 +28036,13 @@ Do or don't use smaller but slower prolo
+ library function calls. The default is to use fast inline prologues and
+ epilogues.
+
++@opindex minline-atomics
++@item -minline-atomics
++@itemx -mno-inline-atomics
++Do or don't use smaller but slower subword atomic emulation code that uses
++libatomic function calls. The default is to use fast inline subword atomics
++that do not require libatomic.
++
+ @item -mshorten-memrefs
+ @itemx -mno-shorten-memrefs
+ @opindex mshorten-memrefs
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-1.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile } */
++/* { dg-options "-mno-inline-atomics" } */
++/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */
++/* { dg-final { scan-assembler "\tcall\t__sync_fetch_and_add_1" } } */
++/* { dg-final { scan-assembler "\tcall\t__sync_fetch_and_nand_1" } } */
++/* { dg-final { scan-assembler "\tcall\t__sync_bool_compare_and_swap_1" } } */
++
++char foo;
++char bar;
++char baz;
++
++int
++main ()
++{
++ __sync_fetch_and_add(&foo, 1);
++ __sync_fetch_and_nand(&bar, 1);
++ __sync_bool_compare_and_swap (&baz, 1, 2);
++}
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* Verify that subword atomics do not generate calls. */
++/* { dg-options "-minline-atomics" } */
++/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */
++/* { dg-final { scan-assembler-not "\tcall\t__sync_fetch_and_add_1" } } */
++/* { dg-final { scan-assembler-not "\tcall\t__sync_fetch_and_nand_1" } } */
++/* { dg-final { scan-assembler-not "\tcall\t__sync_bool_compare_and_swap_1" } } */
++
++#include "inline-atomics-1.c"
+\ No newline at end of file
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-3.c
+@@ -0,0 +1,569 @@
++/* Check all char alignments. */
++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-op-1.c */
++/* Test __atomic routines for existence and proper execution on 1 byte
++ values with each valid memory model. */
++/* { dg-do run } */
++/* { dg-options "-minline-atomics -Wno-address-of-packed-member" } */
++
++/* Test the execution of the __atomic_*OP builtin routines for a char. */
++
++extern void abort(void);
++
++char count, res;
++const char init = ~0;
++
++struct A
++{
++ char a;
++ char b;
++ char c;
++ char d;
++} __attribute__ ((packed)) A;
++
++/* The fetch_op routines return the original value before the operation. */
++
++void
++test_fetch_add (char* v)
++{
++ *v = 0;
++ count = 1;
++
++ if (__atomic_fetch_add (v, count, __ATOMIC_RELAXED) != 0)
++ abort ();
++
++ if (__atomic_fetch_add (v, 1, __ATOMIC_CONSUME) != 1)
++ abort ();
++
++ if (__atomic_fetch_add (v, count, __ATOMIC_ACQUIRE) != 2)
++ abort ();
++
++ if (__atomic_fetch_add (v, 1, __ATOMIC_RELEASE) != 3)
++ abort ();
++
++ if (__atomic_fetch_add (v, count, __ATOMIC_ACQ_REL) != 4)
++ abort ();
++
++ if (__atomic_fetch_add (v, 1, __ATOMIC_SEQ_CST) != 5)
++ abort ();
++}
++
++
++void
++test_fetch_sub (char* v)
++{
++ *v = res = 20;
++ count = 0;
++
++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_RELAXED) != res--)
++ abort ();
++
++ if (__atomic_fetch_sub (v, 1, __ATOMIC_CONSUME) != res--)
++ abort ();
++
++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_ACQUIRE) != res--)
++ abort ();
++
++ if (__atomic_fetch_sub (v, 1, __ATOMIC_RELEASE) != res--)
++ abort ();
++
++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_ACQ_REL) != res--)
++ abort ();
++
++ if (__atomic_fetch_sub (v, 1, __ATOMIC_SEQ_CST) != res--)
++ abort ();
++}
++
++void
++test_fetch_and (char* v)
++{
++ *v = init;
++
++ if (__atomic_fetch_and (v, 0, __ATOMIC_RELAXED) != init)
++ abort ();
++
++ if (__atomic_fetch_and (v, init, __ATOMIC_CONSUME) != 0)
++ abort ();
++
++ if (__atomic_fetch_and (v, 0, __ATOMIC_ACQUIRE) != 0)
++ abort ();
++
++ *v = ~*v;
++ if (__atomic_fetch_and (v, init, __ATOMIC_RELEASE) != init)
++ abort ();
++
++ if (__atomic_fetch_and (v, 0, __ATOMIC_ACQ_REL) != init)
++ abort ();
++
++ if (__atomic_fetch_and (v, 0, __ATOMIC_SEQ_CST) != 0)
++ abort ();
++}
++
++void
++test_fetch_nand (char* v)
++{
++ *v = init;
++
++ if (__atomic_fetch_nand (v, 0, __ATOMIC_RELAXED) != init)
++ abort ();
++
++ if (__atomic_fetch_nand (v, init, __ATOMIC_CONSUME) != init)
++ abort ();
++
++ if (__atomic_fetch_nand (v, 0, __ATOMIC_ACQUIRE) != 0 )
++ abort ();
++
++ if (__atomic_fetch_nand (v, init, __ATOMIC_RELEASE) != init)
++ abort ();
++
++ if (__atomic_fetch_nand (v, init, __ATOMIC_ACQ_REL) != 0)
++ abort ();
++
++ if (__atomic_fetch_nand (v, 0, __ATOMIC_SEQ_CST) != init)
++ abort ();
++}
++
++void
++test_fetch_xor (char* v)
++{
++ *v = init;
++ count = 0;
++
++ if (__atomic_fetch_xor (v, count, __ATOMIC_RELAXED) != init)
++ abort ();
++
++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_CONSUME) != init)
++ abort ();
++
++ if (__atomic_fetch_xor (v, 0, __ATOMIC_ACQUIRE) != 0)
++ abort ();
++
++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_RELEASE) != 0)
++ abort ();
++
++ if (__atomic_fetch_xor (v, 0, __ATOMIC_ACQ_REL) != init)
++ abort ();
++
++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_SEQ_CST) != init)
++ abort ();
++}
++
++void
++test_fetch_or (char* v)
++{
++ *v = 0;
++ count = 1;
++
++ if (__atomic_fetch_or (v, count, __ATOMIC_RELAXED) != 0)
++ abort ();
++
++ count *= 2;
++ if (__atomic_fetch_or (v, 2, __ATOMIC_CONSUME) != 1)
++ abort ();
++
++ count *= 2;
++ if (__atomic_fetch_or (v, count, __ATOMIC_ACQUIRE) != 3)
++ abort ();
++
++ count *= 2;
++ if (__atomic_fetch_or (v, 8, __ATOMIC_RELEASE) != 7)
++ abort ();
++
++ count *= 2;
++ if (__atomic_fetch_or (v, count, __ATOMIC_ACQ_REL) != 15)
++ abort ();
++
++ count *= 2;
++ if (__atomic_fetch_or (v, count, __ATOMIC_SEQ_CST) != 31)
++ abort ();
++}
++
++/* The OP_fetch routines return the new value after the operation. */
++
++void
++test_add_fetch (char* v)
++{
++ *v = 0;
++ count = 1;
++
++ if (__atomic_add_fetch (v, count, __ATOMIC_RELAXED) != 1)
++ abort ();
++
++ if (__atomic_add_fetch (v, 1, __ATOMIC_CONSUME) != 2)
++ abort ();
++
++ if (__atomic_add_fetch (v, count, __ATOMIC_ACQUIRE) != 3)
++ abort ();
++
++ if (__atomic_add_fetch (v, 1, __ATOMIC_RELEASE) != 4)
++ abort ();
++
++ if (__atomic_add_fetch (v, count, __ATOMIC_ACQ_REL) != 5)
++ abort ();
++
++ if (__atomic_add_fetch (v, count, __ATOMIC_SEQ_CST) != 6)
++ abort ();
++}
++
++
++void
++test_sub_fetch (char* v)
++{
++ *v = res = 20;
++ count = 0;
++
++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_RELAXED) != --res)
++ abort ();
++
++ if (__atomic_sub_fetch (v, 1, __ATOMIC_CONSUME) != --res)
++ abort ();
++
++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_ACQUIRE) != --res)
++ abort ();
++
++ if (__atomic_sub_fetch (v, 1, __ATOMIC_RELEASE) != --res)
++ abort ();
++
++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_ACQ_REL) != --res)
++ abort ();
++
++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_SEQ_CST) != --res)
++ abort ();
++}
++
++void
++test_and_fetch (char* v)
++{
++ *v = init;
++
++ if (__atomic_and_fetch (v, 0, __ATOMIC_RELAXED) != 0)
++ abort ();
++
++ *v = init;
++ if (__atomic_and_fetch (v, init, __ATOMIC_CONSUME) != init)
++ abort ();
++
++ if (__atomic_and_fetch (v, 0, __ATOMIC_ACQUIRE) != 0)
++ abort ();
++
++ *v = ~*v;
++ if (__atomic_and_fetch (v, init, __ATOMIC_RELEASE) != init)
++ abort ();
++
++ if (__atomic_and_fetch (v, 0, __ATOMIC_ACQ_REL) != 0)
++ abort ();
++
++ *v = ~*v;
++ if (__atomic_and_fetch (v, 0, __ATOMIC_SEQ_CST) != 0)
++ abort ();
++}
++
++void
++test_nand_fetch (char* v)
++{
++ *v = init;
++
++ if (__atomic_nand_fetch (v, 0, __ATOMIC_RELAXED) != init)
++ abort ();
++
++ if (__atomic_nand_fetch (v, init, __ATOMIC_CONSUME) != 0)
++ abort ();
++
++ if (__atomic_nand_fetch (v, 0, __ATOMIC_ACQUIRE) != init)
++ abort ();
++
++ if (__atomic_nand_fetch (v, init, __ATOMIC_RELEASE) != 0)
++ abort ();
++
++ if (__atomic_nand_fetch (v, init, __ATOMIC_ACQ_REL) != init)
++ abort ();
++
++ if (__atomic_nand_fetch (v, 0, __ATOMIC_SEQ_CST) != init)
++ abort ();
++}
++
++
++
++void
++test_xor_fetch (char* v)
++{
++ *v = init;
++ count = 0;
++
++ if (__atomic_xor_fetch (v, count, __ATOMIC_RELAXED) != init)
++ abort ();
++
++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_CONSUME) != 0)
++ abort ();
++
++ if (__atomic_xor_fetch (v, 0, __ATOMIC_ACQUIRE) != 0)
++ abort ();
++
++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_RELEASE) != init)
++ abort ();
++
++ if (__atomic_xor_fetch (v, 0, __ATOMIC_ACQ_REL) != init)
++ abort ();
++
++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_SEQ_CST) != 0)
++ abort ();
++}
++
++void
++test_or_fetch (char* v)
++{
++ *v = 0;
++ count = 1;
++
++ if (__atomic_or_fetch (v, count, __ATOMIC_RELAXED) != 1)
++ abort ();
++
++ count *= 2;
++ if (__atomic_or_fetch (v, 2, __ATOMIC_CONSUME) != 3)
++ abort ();
++
++ count *= 2;
++ if (__atomic_or_fetch (v, count, __ATOMIC_ACQUIRE) != 7)
++ abort ();
++
++ count *= 2;
++ if (__atomic_or_fetch (v, 8, __ATOMIC_RELEASE) != 15)
++ abort ();
++
++ count *= 2;
++ if (__atomic_or_fetch (v, count, __ATOMIC_ACQ_REL) != 31)
++ abort ();
++
++ count *= 2;
++ if (__atomic_or_fetch (v, count, __ATOMIC_SEQ_CST) != 63)
++ abort ();
++}
++
++
++/* Test the OP routines with a result which isn't used. Use both variations
++ within each function. */
++
++void
++test_add (char* v)
++{
++ *v = 0;
++ count = 1;
++
++ __atomic_add_fetch (v, count, __ATOMIC_RELAXED);
++ if (*v != 1)
++ abort ();
++
++ __atomic_fetch_add (v, count, __ATOMIC_CONSUME);
++ if (*v != 2)
++ abort ();
++
++ __atomic_add_fetch (v, 1 , __ATOMIC_ACQUIRE);
++ if (*v != 3)
++ abort ();
++
++ __atomic_fetch_add (v, 1, __ATOMIC_RELEASE);
++ if (*v != 4)
++ abort ();
++
++ __atomic_add_fetch (v, count, __ATOMIC_ACQ_REL);
++ if (*v != 5)
++ abort ();
++
++ __atomic_fetch_add (v, count, __ATOMIC_SEQ_CST);
++ if (*v != 6)
++ abort ();
++}
++
++
++void
++test_sub (char* v)
++{
++ *v = res = 20;
++ count = 0;
++
++ __atomic_sub_fetch (v, count + 1, __ATOMIC_RELAXED);
++ if (*v != --res)
++ abort ();
++
++ __atomic_fetch_sub (v, count + 1, __ATOMIC_CONSUME);
++ if (*v != --res)
++ abort ();
++
++ __atomic_sub_fetch (v, 1, __ATOMIC_ACQUIRE);
++ if (*v != --res)
++ abort ();
++
++ __atomic_fetch_sub (v, 1, __ATOMIC_RELEASE);
++ if (*v != --res)
++ abort ();
++
++ __atomic_sub_fetch (v, count + 1, __ATOMIC_ACQ_REL);
++ if (*v != --res)
++ abort ();
++
++ __atomic_fetch_sub (v, count + 1, __ATOMIC_SEQ_CST);
++ if (*v != --res)
++ abort ();
++}
++
++void
++test_and (char* v)
++{
++ *v = init;
++
++ __atomic_and_fetch (v, 0, __ATOMIC_RELAXED);
++ if (*v != 0)
++ abort ();
++
++ *v = init;
++ __atomic_fetch_and (v, init, __ATOMIC_CONSUME);
++ if (*v != init)
++ abort ();
++
++ __atomic_and_fetch (v, 0, __ATOMIC_ACQUIRE);
++ if (*v != 0)
++ abort ();
++
++ *v = ~*v;
++ __atomic_fetch_and (v, init, __ATOMIC_RELEASE);
++ if (*v != init)
++ abort ();
++
++ __atomic_and_fetch (v, 0, __ATOMIC_ACQ_REL);
++ if (*v != 0)
++ abort ();
++
++ *v = ~*v;
++ __atomic_fetch_and (v, 0, __ATOMIC_SEQ_CST);
++ if (*v != 0)
++ abort ();
++}
++
++void
++test_nand (char* v)
++{
++ *v = init;
++
++ __atomic_fetch_nand (v, 0, __ATOMIC_RELAXED);
++ if (*v != init)
++ abort ();
++
++ __atomic_fetch_nand (v, init, __ATOMIC_CONSUME);
++ if (*v != 0)
++ abort ();
++
++ __atomic_nand_fetch (v, 0, __ATOMIC_ACQUIRE);
++ if (*v != init)
++ abort ();
++
++ __atomic_nand_fetch (v, init, __ATOMIC_RELEASE);
++ if (*v != 0)
++ abort ();
++
++ __atomic_fetch_nand (v, init, __ATOMIC_ACQ_REL);
++ if (*v != init)
++ abort ();
++
++ __atomic_nand_fetch (v, 0, __ATOMIC_SEQ_CST);
++ if (*v != init)
++ abort ();
++}
++
++
++
++void
++test_xor (char* v)
++{
++ *v = init;
++ count = 0;
++
++ __atomic_xor_fetch (v, count, __ATOMIC_RELAXED);
++ if (*v != init)
++ abort ();
++
++ __atomic_fetch_xor (v, ~count, __ATOMIC_CONSUME);
++ if (*v != 0)
++ abort ();
++
++ __atomic_xor_fetch (v, 0, __ATOMIC_ACQUIRE);
++ if (*v != 0)
++ abort ();
++
++ __atomic_fetch_xor (v, ~count, __ATOMIC_RELEASE);
++ if (*v != init)
++ abort ();
++
++ __atomic_fetch_xor (v, 0, __ATOMIC_ACQ_REL);
++ if (*v != init)
++ abort ();
++
++ __atomic_xor_fetch (v, ~count, __ATOMIC_SEQ_CST);
++ if (*v != 0)
++ abort ();
++}
++
++void
++test_or (char* v)
++{
++ *v = 0;
++ count = 1;
++
++ __atomic_or_fetch (v, count, __ATOMIC_RELAXED);
++ if (*v != 1)
++ abort ();
++
++ count *= 2;
++ __atomic_fetch_or (v, count, __ATOMIC_CONSUME);
++ if (*v != 3)
++ abort ();
++
++ count *= 2;
++ __atomic_or_fetch (v, 4, __ATOMIC_ACQUIRE);
++ if (*v != 7)
++ abort ();
++
++ count *= 2;
++ __atomic_fetch_or (v, 8, __ATOMIC_RELEASE);
++ if (*v != 15)
++ abort ();
++
++ count *= 2;
++ __atomic_or_fetch (v, count, __ATOMIC_ACQ_REL);
++ if (*v != 31)
++ abort ();
++
++ count *= 2;
++ __atomic_fetch_or (v, count, __ATOMIC_SEQ_CST);
++ if (*v != 63)
++ abort ();
++}
++
++int
++main ()
++{
++ char* V[] = {&A.a, &A.b, &A.c, &A.d};
++
++ for (int i = 0; i < 4; i++) {
++ test_fetch_add (V[i]);
++ test_fetch_sub (V[i]);
++ test_fetch_and (V[i]);
++ test_fetch_nand (V[i]);
++ test_fetch_xor (V[i]);
++ test_fetch_or (V[i]);
++
++ test_add_fetch (V[i]);
++ test_sub_fetch (V[i]);
++ test_and_fetch (V[i]);
++ test_nand_fetch (V[i]);
++ test_xor_fetch (V[i]);
++ test_or_fetch (V[i]);
++
++ test_add (V[i]);
++ test_sub (V[i]);
++ test_and (V[i]);
++ test_nand (V[i]);
++ test_xor (V[i]);
++ test_or (V[i]);
++ }
++
++ return 0;
++}
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-4.c
+@@ -0,0 +1,566 @@
++/* Check all short alignments. */
++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-op-2.c */
++/* Test __atomic routines for existence and proper execution on 2 byte
++ values with each valid memory model. */
++/* { dg-do run } */
++/* { dg-options "-minline-atomics -Wno-address-of-packed-member" } */
++
++/* Test the execution of the __atomic_*OP builtin routines for a short. */
++
++extern void abort(void);
++
++short count, res;
++const short init = ~0;
++
++struct A
++{
++ short a;
++ short b;
++} __attribute__ ((packed)) A;
++
++/* The fetch_op routines return the original value before the operation. */
++
++void
++test_fetch_add (short* v)
++{
++ *v = 0;
++ count = 1;
++
++ if (__atomic_fetch_add (v, count, __ATOMIC_RELAXED) != 0)
++ abort ();
++
++ if (__atomic_fetch_add (v, 1, __ATOMIC_CONSUME) != 1)
++ abort ();
++
++ if (__atomic_fetch_add (v, count, __ATOMIC_ACQUIRE) != 2)
++ abort ();
++
++ if (__atomic_fetch_add (v, 1, __ATOMIC_RELEASE) != 3)
++ abort ();
++
++ if (__atomic_fetch_add (v, count, __ATOMIC_ACQ_REL) != 4)
++ abort ();
++
++ if (__atomic_fetch_add (v, 1, __ATOMIC_SEQ_CST) != 5)
++ abort ();
++}
++
++
++void
++test_fetch_sub (short* v)
++{
++ *v = res = 20;
++ count = 0;
++
++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_RELAXED) != res--)
++ abort ();
++
++ if (__atomic_fetch_sub (v, 1, __ATOMIC_CONSUME) != res--)
++ abort ();
++
++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_ACQUIRE) != res--)
++ abort ();
++
++ if (__atomic_fetch_sub (v, 1, __ATOMIC_RELEASE) != res--)
++ abort ();
++
++ if (__atomic_fetch_sub (v, count + 1, __ATOMIC_ACQ_REL) != res--)
++ abort ();
++
++ if (__atomic_fetch_sub (v, 1, __ATOMIC_SEQ_CST) != res--)
++ abort ();
++}
++
++void
++test_fetch_and (short* v)
++{
++ *v = init;
++
++ if (__atomic_fetch_and (v, 0, __ATOMIC_RELAXED) != init)
++ abort ();
++
++ if (__atomic_fetch_and (v, init, __ATOMIC_CONSUME) != 0)
++ abort ();
++
++ if (__atomic_fetch_and (v, 0, __ATOMIC_ACQUIRE) != 0)
++ abort ();
++
++ *v = ~*v;
++ if (__atomic_fetch_and (v, init, __ATOMIC_RELEASE) != init)
++ abort ();
++
++ if (__atomic_fetch_and (v, 0, __ATOMIC_ACQ_REL) != init)
++ abort ();
++
++ if (__atomic_fetch_and (v, 0, __ATOMIC_SEQ_CST) != 0)
++ abort ();
++}
++
++void
++test_fetch_nand (short* v)
++{
++ *v = init;
++
++ if (__atomic_fetch_nand (v, 0, __ATOMIC_RELAXED) != init)
++ abort ();
++
++ if (__atomic_fetch_nand (v, init, __ATOMIC_CONSUME) != init)
++ abort ();
++
++ if (__atomic_fetch_nand (v, 0, __ATOMIC_ACQUIRE) != 0 )
++ abort ();
++
++ if (__atomic_fetch_nand (v, init, __ATOMIC_RELEASE) != init)
++ abort ();
++
++ if (__atomic_fetch_nand (v, init, __ATOMIC_ACQ_REL) != 0)
++ abort ();
++
++ if (__atomic_fetch_nand (v, 0, __ATOMIC_SEQ_CST) != init)
++ abort ();
++}
++
++void
++test_fetch_xor (short* v)
++{
++ *v = init;
++ count = 0;
++
++ if (__atomic_fetch_xor (v, count, __ATOMIC_RELAXED) != init)
++ abort ();
++
++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_CONSUME) != init)
++ abort ();
++
++ if (__atomic_fetch_xor (v, 0, __ATOMIC_ACQUIRE) != 0)
++ abort ();
++
++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_RELEASE) != 0)
++ abort ();
++
++ if (__atomic_fetch_xor (v, 0, __ATOMIC_ACQ_REL) != init)
++ abort ();
++
++ if (__atomic_fetch_xor (v, ~count, __ATOMIC_SEQ_CST) != init)
++ abort ();
++}
++
++void
++test_fetch_or (short* v)
++{
++ *v = 0;
++ count = 1;
++
++ if (__atomic_fetch_or (v, count, __ATOMIC_RELAXED) != 0)
++ abort ();
++
++ count *= 2;
++ if (__atomic_fetch_or (v, 2, __ATOMIC_CONSUME) != 1)
++ abort ();
++
++ count *= 2;
++ if (__atomic_fetch_or (v, count, __ATOMIC_ACQUIRE) != 3)
++ abort ();
++
++ count *= 2;
++ if (__atomic_fetch_or (v, 8, __ATOMIC_RELEASE) != 7)
++ abort ();
++
++ count *= 2;
++ if (__atomic_fetch_or (v, count, __ATOMIC_ACQ_REL) != 15)
++ abort ();
++
++ count *= 2;
++ if (__atomic_fetch_or (v, count, __ATOMIC_SEQ_CST) != 31)
++ abort ();
++}
++
++/* The OP_fetch routines return the new value after the operation. */
++
++void
++test_add_fetch (short* v)
++{
++ *v = 0;
++ count = 1;
++
++ if (__atomic_add_fetch (v, count, __ATOMIC_RELAXED) != 1)
++ abort ();
++
++ if (__atomic_add_fetch (v, 1, __ATOMIC_CONSUME) != 2)
++ abort ();
++
++ if (__atomic_add_fetch (v, count, __ATOMIC_ACQUIRE) != 3)
++ abort ();
++
++ if (__atomic_add_fetch (v, 1, __ATOMIC_RELEASE) != 4)
++ abort ();
++
++ if (__atomic_add_fetch (v, count, __ATOMIC_ACQ_REL) != 5)
++ abort ();
++
++ if (__atomic_add_fetch (v, count, __ATOMIC_SEQ_CST) != 6)
++ abort ();
++}
++
++
++void
++test_sub_fetch (short* v)
++{
++ *v = res = 20;
++ count = 0;
++
++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_RELAXED) != --res)
++ abort ();
++
++ if (__atomic_sub_fetch (v, 1, __ATOMIC_CONSUME) != --res)
++ abort ();
++
++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_ACQUIRE) != --res)
++ abort ();
++
++ if (__atomic_sub_fetch (v, 1, __ATOMIC_RELEASE) != --res)
++ abort ();
++
++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_ACQ_REL) != --res)
++ abort ();
++
++ if (__atomic_sub_fetch (v, count + 1, __ATOMIC_SEQ_CST) != --res)
++ abort ();
++}
++
++void
++test_and_fetch (short* v)
++{
++ *v = init;
++
++ if (__atomic_and_fetch (v, 0, __ATOMIC_RELAXED) != 0)
++ abort ();
++
++ *v = init;
++ if (__atomic_and_fetch (v, init, __ATOMIC_CONSUME) != init)
++ abort ();
++
++ if (__atomic_and_fetch (v, 0, __ATOMIC_ACQUIRE) != 0)
++ abort ();
++
++ *v = ~*v;
++ if (__atomic_and_fetch (v, init, __ATOMIC_RELEASE) != init)
++ abort ();
++
++ if (__atomic_and_fetch (v, 0, __ATOMIC_ACQ_REL) != 0)
++ abort ();
++
++ *v = ~*v;
++ if (__atomic_and_fetch (v, 0, __ATOMIC_SEQ_CST) != 0)
++ abort ();
++}
++
++void
++test_nand_fetch (short* v)
++{
++ *v = init;
++
++ if (__atomic_nand_fetch (v, 0, __ATOMIC_RELAXED) != init)
++ abort ();
++
++ if (__atomic_nand_fetch (v, init, __ATOMIC_CONSUME) != 0)
++ abort ();
++
++ if (__atomic_nand_fetch (v, 0, __ATOMIC_ACQUIRE) != init)
++ abort ();
++
++ if (__atomic_nand_fetch (v, init, __ATOMIC_RELEASE) != 0)
++ abort ();
++
++ if (__atomic_nand_fetch (v, init, __ATOMIC_ACQ_REL) != init)
++ abort ();
++
++ if (__atomic_nand_fetch (v, 0, __ATOMIC_SEQ_CST) != init)
++ abort ();
++}
++
++
++
++void
++test_xor_fetch (short* v)
++{
++ *v = init;
++ count = 0;
++
++ if (__atomic_xor_fetch (v, count, __ATOMIC_RELAXED) != init)
++ abort ();
++
++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_CONSUME) != 0)
++ abort ();
++
++ if (__atomic_xor_fetch (v, 0, __ATOMIC_ACQUIRE) != 0)
++ abort ();
++
++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_RELEASE) != init)
++ abort ();
++
++ if (__atomic_xor_fetch (v, 0, __ATOMIC_ACQ_REL) != init)
++ abort ();
++
++ if (__atomic_xor_fetch (v, ~count, __ATOMIC_SEQ_CST) != 0)
++ abort ();
++}
++
++void
++test_or_fetch (short* v)
++{
++ *v = 0;
++ count = 1;
++
++ if (__atomic_or_fetch (v, count, __ATOMIC_RELAXED) != 1)
++ abort ();
++
++ count *= 2;
++ if (__atomic_or_fetch (v, 2, __ATOMIC_CONSUME) != 3)
++ abort ();
++
++ count *= 2;
++ if (__atomic_or_fetch (v, count, __ATOMIC_ACQUIRE) != 7)
++ abort ();
++
++ count *= 2;
++ if (__atomic_or_fetch (v, 8, __ATOMIC_RELEASE) != 15)
++ abort ();
++
++ count *= 2;
++ if (__atomic_or_fetch (v, count, __ATOMIC_ACQ_REL) != 31)
++ abort ();
++
++ count *= 2;
++ if (__atomic_or_fetch (v, count, __ATOMIC_SEQ_CST) != 63)
++ abort ();
++}
++
++
++/* Test the OP routines with a result which isn't used. Use both variations
++ within each function. */
++
++void
++test_add (short* v)
++{
++ *v = 0;
++ count = 1;
++
++ __atomic_add_fetch (v, count, __ATOMIC_RELAXED);
++ if (*v != 1)
++ abort ();
++
++ __atomic_fetch_add (v, count, __ATOMIC_CONSUME);
++ if (*v != 2)
++ abort ();
++
++ __atomic_add_fetch (v, 1 , __ATOMIC_ACQUIRE);
++ if (*v != 3)
++ abort ();
++
++ __atomic_fetch_add (v, 1, __ATOMIC_RELEASE);
++ if (*v != 4)
++ abort ();
++
++ __atomic_add_fetch (v, count, __ATOMIC_ACQ_REL);
++ if (*v != 5)
++ abort ();
++
++ __atomic_fetch_add (v, count, __ATOMIC_SEQ_CST);
++ if (*v != 6)
++ abort ();
++}
++
++
++void
++test_sub (short* v)
++{
++ *v = res = 20;
++ count = 0;
++
++ __atomic_sub_fetch (v, count + 1, __ATOMIC_RELAXED);
++ if (*v != --res)
++ abort ();
++
++ __atomic_fetch_sub (v, count + 1, __ATOMIC_CONSUME);
++ if (*v != --res)
++ abort ();
++
++ __atomic_sub_fetch (v, 1, __ATOMIC_ACQUIRE);
++ if (*v != --res)
++ abort ();
++
++ __atomic_fetch_sub (v, 1, __ATOMIC_RELEASE);
++ if (*v != --res)
++ abort ();
++
++ __atomic_sub_fetch (v, count + 1, __ATOMIC_ACQ_REL);
++ if (*v != --res)
++ abort ();
++
++ __atomic_fetch_sub (v, count + 1, __ATOMIC_SEQ_CST);
++ if (*v != --res)
++ abort ();
++}
++
++void
++test_and (short* v)
++{
++ *v = init;
++
++ __atomic_and_fetch (v, 0, __ATOMIC_RELAXED);
++ if (*v != 0)
++ abort ();
++
++ *v = init;
++ __atomic_fetch_and (v, init, __ATOMIC_CONSUME);
++ if (*v != init)
++ abort ();
++
++ __atomic_and_fetch (v, 0, __ATOMIC_ACQUIRE);
++ if (*v != 0)
++ abort ();
++
++ *v = ~*v;
++ __atomic_fetch_and (v, init, __ATOMIC_RELEASE);
++ if (*v != init)
++ abort ();
++
++ __atomic_and_fetch (v, 0, __ATOMIC_ACQ_REL);
++ if (*v != 0)
++ abort ();
++
++ *v = ~*v;
++ __atomic_fetch_and (v, 0, __ATOMIC_SEQ_CST);
++ if (*v != 0)
++ abort ();
++}
++
++void
++test_nand (short* v)
++{
++ *v = init;
++
++ __atomic_fetch_nand (v, 0, __ATOMIC_RELAXED);
++ if (*v != init)
++ abort ();
++
++ __atomic_fetch_nand (v, init, __ATOMIC_CONSUME);
++ if (*v != 0)
++ abort ();
++
++ __atomic_nand_fetch (v, 0, __ATOMIC_ACQUIRE);
++ if (*v != init)
++ abort ();
++
++ __atomic_nand_fetch (v, init, __ATOMIC_RELEASE);
++ if (*v != 0)
++ abort ();
++
++ __atomic_fetch_nand (v, init, __ATOMIC_ACQ_REL);
++ if (*v != init)
++ abort ();
++
++ __atomic_nand_fetch (v, 0, __ATOMIC_SEQ_CST);
++ if (*v != init)
++ abort ();
++}
++
++
++
++void
++test_xor (short* v)
++{
++ *v = init;
++ count = 0;
++
++ __atomic_xor_fetch (v, count, __ATOMIC_RELAXED);
++ if (*v != init)
++ abort ();
++
++ __atomic_fetch_xor (v, ~count, __ATOMIC_CONSUME);
++ if (*v != 0)
++ abort ();
++
++ __atomic_xor_fetch (v, 0, __ATOMIC_ACQUIRE);
++ if (*v != 0)
++ abort ();
++
++ __atomic_fetch_xor (v, ~count, __ATOMIC_RELEASE);
++ if (*v != init)
++ abort ();
++
++ __atomic_fetch_xor (v, 0, __ATOMIC_ACQ_REL);
++ if (*v != init)
++ abort ();
++
++ __atomic_xor_fetch (v, ~count, __ATOMIC_SEQ_CST);
++ if (*v != 0)
++ abort ();
++}
++
++void
++test_or (short* v)
++{
++ *v = 0;
++ count = 1;
++
++ __atomic_or_fetch (v, count, __ATOMIC_RELAXED);
++ if (*v != 1)
++ abort ();
++
++ count *= 2;
++ __atomic_fetch_or (v, count, __ATOMIC_CONSUME);
++ if (*v != 3)
++ abort ();
++
++ count *= 2;
++ __atomic_or_fetch (v, 4, __ATOMIC_ACQUIRE);
++ if (*v != 7)
++ abort ();
++
++ count *= 2;
++ __atomic_fetch_or (v, 8, __ATOMIC_RELEASE);
++ if (*v != 15)
++ abort ();
++
++ count *= 2;
++ __atomic_or_fetch (v, count, __ATOMIC_ACQ_REL);
++ if (*v != 31)
++ abort ();
++
++ count *= 2;
++ __atomic_fetch_or (v, count, __ATOMIC_SEQ_CST);
++ if (*v != 63)
++ abort ();
++}
++
++int
++main () {
++ short* V[] = {&A.a, &A.b};
++
++ for (int i = 0; i < 2; i++) {
++ test_fetch_add (V[i]);
++ test_fetch_sub (V[i]);
++ test_fetch_and (V[i]);
++ test_fetch_nand (V[i]);
++ test_fetch_xor (V[i]);
++ test_fetch_or (V[i]);
++
++ test_add_fetch (V[i]);
++ test_sub_fetch (V[i]);
++ test_and_fetch (V[i]);
++ test_nand_fetch (V[i]);
++ test_xor_fetch (V[i]);
++ test_or_fetch (V[i]);
++
++ test_add (V[i]);
++ test_sub (V[i]);
++ test_and (V[i]);
++ test_nand (V[i]);
++ test_xor (V[i]);
++ test_or (V[i]);
++ }
++
++ return 0;
++}
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-5.c
+@@ -0,0 +1,87 @@
++/* Test __atomic routines for existence and proper execution on 1 byte
++ values with each valid memory model. */
++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-compare-exchange-1.c */
++/* { dg-do run } */
++/* { dg-options "-minline-atomics" } */
++
++/* Test the execution of the __atomic_compare_exchange_n builtin for a char. */
++
++extern void abort(void);
++
++char v = 0;
++char expected = 0;
++char max = ~0;
++char desired = ~0;
++char zero = 0;
++
++#define STRONG 0
++#define WEAK 1
++
++int
++main ()
++{
++
++ if (!__atomic_compare_exchange_n (&v, &expected, max, STRONG , __ATOMIC_RELAXED, __ATOMIC_RELAXED))
++ abort ();
++ if (expected != 0)
++ abort ();
++
++ if (__atomic_compare_exchange_n (&v, &expected, 0, STRONG , __ATOMIC_ACQUIRE, __ATOMIC_RELAXED))
++ abort ();
++ if (expected != max)
++ abort ();
++
++ if (!__atomic_compare_exchange_n (&v, &expected, 0, STRONG , __ATOMIC_RELEASE, __ATOMIC_ACQUIRE))
++ abort ();
++ if (expected != max)
++ abort ();
++ if (v != 0)
++ abort ();
++
++ if (__atomic_compare_exchange_n (&v, &expected, desired, WEAK, __ATOMIC_ACQ_REL, __ATOMIC_ACQUIRE))
++ abort ();
++ if (expected != 0)
++ abort ();
++
++ if (!__atomic_compare_exchange_n (&v, &expected, desired, STRONG , __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST))
++ abort ();
++ if (expected != 0)
++ abort ();
++ if (v != max)
++ abort ();
++
++ /* Now test the generic version. */
++
++ v = 0;
++
++ if (!__atomic_compare_exchange (&v, &expected, &max, STRONG, __ATOMIC_RELAXED, __ATOMIC_RELAXED))
++ abort ();
++ if (expected != 0)
++ abort ();
++
++ if (__atomic_compare_exchange (&v, &expected, &zero, STRONG , __ATOMIC_ACQUIRE, __ATOMIC_RELAXED))
++ abort ();
++ if (expected != max)
++ abort ();
++
++ if (!__atomic_compare_exchange (&v, &expected, &zero, STRONG , __ATOMIC_RELEASE, __ATOMIC_ACQUIRE))
++ abort ();
++ if (expected != max)
++ abort ();
++ if (v != 0)
++ abort ();
++
++ if (__atomic_compare_exchange (&v, &expected, &desired, WEAK, __ATOMIC_ACQ_REL, __ATOMIC_ACQUIRE))
++ abort ();
++ if (expected != 0)
++ abort ();
++
++ if (!__atomic_compare_exchange (&v, &expected, &desired, STRONG , __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST))
++ abort ();
++ if (expected != 0)
++ abort ();
++ if (v != max)
++ abort ();
++
++ return 0;
++}
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-6.c
+@@ -0,0 +1,87 @@
++/* Test __atomic routines for existence and proper execution on 2 byte
++ values with each valid memory model. */
++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-compare-exchange-2.c */
++/* { dg-do run } */
++/* { dg-options "-minline-atomics" } */
++
++/* Test the execution of the __atomic_compare_exchange_n builtin for a short. */
++
++extern void abort(void);
++
++short v = 0;
++short expected = 0;
++short max = ~0;
++short desired = ~0;
++short zero = 0;
++
++#define STRONG 0
++#define WEAK 1
++
++int
++main ()
++{
++
++ if (!__atomic_compare_exchange_n (&v, &expected, max, STRONG , __ATOMIC_RELAXED, __ATOMIC_RELAXED))
++ abort ();
++ if (expected != 0)
++ abort ();
++
++ if (__atomic_compare_exchange_n (&v, &expected, 0, STRONG , __ATOMIC_ACQUIRE, __ATOMIC_RELAXED))
++ abort ();
++ if (expected != max)
++ abort ();
++
++ if (!__atomic_compare_exchange_n (&v, &expected, 0, STRONG , __ATOMIC_RELEASE, __ATOMIC_ACQUIRE))
++ abort ();
++ if (expected != max)
++ abort ();
++ if (v != 0)
++ abort ();
++
++ if (__atomic_compare_exchange_n (&v, &expected, desired, WEAK, __ATOMIC_ACQ_REL, __ATOMIC_ACQUIRE))
++ abort ();
++ if (expected != 0)
++ abort ();
++
++ if (!__atomic_compare_exchange_n (&v, &expected, desired, STRONG , __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST))
++ abort ();
++ if (expected != 0)
++ abort ();
++ if (v != max)
++ abort ();
++
++ /* Now test the generic version. */
++
++ v = 0;
++
++ if (!__atomic_compare_exchange (&v, &expected, &max, STRONG, __ATOMIC_RELAXED, __ATOMIC_RELAXED))
++ abort ();
++ if (expected != 0)
++ abort ();
++
++ if (__atomic_compare_exchange (&v, &expected, &zero, STRONG , __ATOMIC_ACQUIRE, __ATOMIC_RELAXED))
++ abort ();
++ if (expected != max)
++ abort ();
++
++ if (!__atomic_compare_exchange (&v, &expected, &zero, STRONG , __ATOMIC_RELEASE, __ATOMIC_ACQUIRE))
++ abort ();
++ if (expected != max)
++ abort ();
++ if (v != 0)
++ abort ();
++
++ if (__atomic_compare_exchange (&v, &expected, &desired, WEAK, __ATOMIC_ACQ_REL, __ATOMIC_ACQUIRE))
++ abort ();
++ if (expected != 0)
++ abort ();
++
++ if (!__atomic_compare_exchange (&v, &expected, &desired, STRONG , __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST))
++ abort ();
++ if (expected != 0)
++ abort ();
++ if (v != max)
++ abort ();
++
++ return 0;
++}
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-7.c
+@@ -0,0 +1,69 @@
++/* Test __atomic routines for existence and proper execution on 1 byte
++ values with each valid memory model. */
++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-exchange-1.c */
++/* { dg-do run } */
++/* { dg-options "-minline-atomics" } */
++
++/* Test the execution of the __atomic_exchange_n builtin for a char. */
++
++extern void abort(void);
++
++char v, count, ret;
++
++int
++main ()
++{
++ v = 0;
++ count = 0;
++
++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_RELAXED) != count)
++ abort ();
++ count++;
++
++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_ACQUIRE) != count)
++ abort ();
++ count++;
++
++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_RELEASE) != count)
++ abort ();
++ count++;
++
++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_ACQ_REL) != count)
++ abort ();
++ count++;
++
++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_SEQ_CST) != count)
++ abort ();
++ count++;
++
++ /* Now test the generic version. */
++
++ count++;
++
++ __atomic_exchange (&v, &count, &ret, __ATOMIC_RELAXED);
++ if (ret != count - 1 || v != count)
++ abort ();
++ count++;
++
++ __atomic_exchange (&v, &count, &ret, __ATOMIC_ACQUIRE);
++ if (ret != count - 1 || v != count)
++ abort ();
++ count++;
++
++ __atomic_exchange (&v, &count, &ret, __ATOMIC_RELEASE);
++ if (ret != count - 1 || v != count)
++ abort ();
++ count++;
++
++ __atomic_exchange (&v, &count, &ret, __ATOMIC_ACQ_REL);
++ if (ret != count - 1 || v != count)
++ abort ();
++ count++;
++
++ __atomic_exchange (&v, &count, &ret, __ATOMIC_SEQ_CST);
++ if (ret != count - 1 || v != count)
++ abort ();
++ count++;
++
++ return 0;
++}
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-8.c
+@@ -0,0 +1,69 @@
++/* Test __atomic routines for existence and proper execution on 2 byte
++ values with each valid memory model. */
++/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-exchange-2.c */
++/* { dg-do run } */
++/* { dg-options "-minline-atomics" } */
++
++/* Test the execution of the __atomic_X builtin for a short. */
++
++extern void abort(void);
++
++short v, count, ret;
++
++int
++main ()
++{
++ v = 0;
++ count = 0;
++
++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_RELAXED) != count)
++ abort ();
++ count++;
++
++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_ACQUIRE) != count)
++ abort ();
++ count++;
++
++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_RELEASE) != count)
++ abort ();
++ count++;
++
++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_ACQ_REL) != count)
++ abort ();
++ count++;
++
++ if (__atomic_exchange_n (&v, count + 1, __ATOMIC_SEQ_CST) != count)
++ abort ();
++ count++;
++
++ /* Now test the generic version. */
++
++ count++;
++
++ __atomic_exchange (&v, &count, &ret, __ATOMIC_RELAXED);
++ if (ret != count - 1 || v != count)
++ abort ();
++ count++;
++
++ __atomic_exchange (&v, &count, &ret, __ATOMIC_ACQUIRE);
++ if (ret != count - 1 || v != count)
++ abort ();
++ count++;
++
++ __atomic_exchange (&v, &count, &ret, __ATOMIC_RELEASE);
++ if (ret != count - 1 || v != count)
++ abort ();
++ count++;
++
++ __atomic_exchange (&v, &count, &ret, __ATOMIC_ACQ_REL);
++ if (ret != count - 1 || v != count)
++ abort ();
++ count++;
++
++ __atomic_exchange (&v, &count, &ret, __ATOMIC_SEQ_CST);
++ if (ret != count - 1 || v != count)
++ abort ();
++ count++;
++
++ return 0;
++}
+--- a/libgcc/config/riscv/atomic.c
++++ b/libgcc/config/riscv/atomic.c
+@@ -30,6 +30,8 @@ see the files COPYING3 and COPYING.RUNTI
+ #define INVERT "not %[tmp1], %[tmp1]\n\t"
+ #define DONT_INVERT ""
+
++/* Logic duplicated in gcc/gcc/config/riscv/sync.md for use when inlining is enabled */
++
+ #define GENERATE_FETCH_AND_OP(type, size, opname, insn, invert, cop) \
+ type __sync_fetch_and_ ## opname ## _ ## size (type *p, type v) \
+ { \
diff --git a/external/subpack/devel/gcc/patches-12.x/701-riscv-linux-Don-t-add-latomic-with-pthread.patch b/external/subpack/devel/gcc/patches-12.x/701-riscv-linux-Don-t-add-latomic-with-pthread.patch
new file mode 100644
index 0000000..328c7be
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/701-riscv-linux-Don-t-add-latomic-with-pthread.patch
@@ -0,0 +1,36 @@
+From 203f3060dd363361b172f7295f42bb6bf5ac0b3b Mon Sep 17 00:00:00 2001
+From: Andreas Schwab <schwab@suse.de>
+Date: Sat, 23 Apr 2022 15:48:42 +0200
+Subject: [PATCH] riscv/linux: Don't add -latomic with -pthread
+
+Now that we have support for inline subword atomic operations, it is no
+longer necessary to link against libatomic. This also fixes testsuite
+failures because the framework does not properly set up the linker flags
+for finding libatomic.
+The use of atomic operations is also independent of the use of libpthread.
+
+gcc/
+ * config/riscv/linux.h (LIB_SPEC): Don't redefine.
+---
+ gcc/config/riscv/linux.h | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+--- a/gcc/config/riscv/linux.h
++++ b/gcc/config/riscv/linux.h
+@@ -35,16 +35,6 @@ along with GCC; see the file COPYING3.
+ #undef MUSL_DYNAMIC_LINKER
+ #define MUSL_DYNAMIC_LINKER "/lib/ld-musl-riscv" XLEN_SPEC MUSL_ABI_SUFFIX ".so.1"
+
+-/* Because RISC-V only has word-sized atomics, it requries libatomic where
+- others do not. So link libatomic by default, as needed. */
+-#undef LIB_SPEC
+-#ifdef LD_AS_NEEDED_OPTION
+-#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC \
+- " %{pthread:" LD_AS_NEEDED_OPTION " -latomic " LD_NO_AS_NEEDED_OPTION "}"
+-#else
+-#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC " -latomic "
+-#endif
+-
+ #define ICACHE_FLUSH_FUNC "__riscv_flush_icache"
+
+ #define CPP_SPEC "%{pthread:-D_REENTRANT}"
diff --git a/external/subpack/devel/gcc/patches-12.x/810-arm-softfloat-libgcc.patch b/external/subpack/devel/gcc/patches-12.x/810-arm-softfloat-libgcc.patch
new file mode 100644
index 0000000..5c9d86a
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/810-arm-softfloat-libgcc.patch
@@ -0,0 +1,33 @@
+commit 8570c4be394cff7282f332f97da2ff569a927ddb
+Author: Imre Kaloz <kaloz@openwrt.org>
+Date: Wed Feb 2 20:06:12 2011 +0000
+
+ fixup arm soft-float symbols
+
+ SVN-Revision: 25325
+
+--- a/libgcc/config/arm/t-linux
++++ b/libgcc/config/arm/t-linux
+@@ -1,6 +1,10 @@
+ LIB1ASMSRC = arm/lib1funcs.S
+ LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \
+- _ctzsi2 _arm_addsubdf3 _arm_addsubsf3
++ _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \
++ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \
++ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \
++ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \
++ _arm_fixsfsi _arm_fixunssfsi
+
+ # Just for these, we omit the frame pointer since it makes such a big
+ # difference.
+--- a/gcc/config/arm/linux-elf.h
++++ b/gcc/config/arm/linux-elf.h
+@@ -58,8 +58,6 @@
+ %{shared:-lc} \
+ %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
+
+-#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
+-
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #define LINUX_TARGET_LINK_SPEC "%{h*} \
diff --git a/external/subpack/devel/gcc/patches-12.x/820-libgcc_pic.patch b/external/subpack/devel/gcc/patches-12.x/820-libgcc_pic.patch
new file mode 100644
index 0000000..525a95b
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/820-libgcc_pic.patch
@@ -0,0 +1,44 @@
+commit c96312958c0621e72c9b32da5bc224ffe2161384
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Mon Oct 19 23:26:09 2009 +0000
+
+ gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow)
+
+ SVN-Revision: 18086
+
+--- a/libgcc/Makefile.in
++++ b/libgcc/Makefile.in
+@@ -930,11 +930,12 @@ $(libgcov-driver-objects): %$(objext): $
+
+ # Static libraries.
+ libgcc.a: $(libgcc-objects)
++libgcc_pic.a: $(libgcc-s-objects)
+ libgcov.a: $(libgcov-objects)
+ libunwind.a: $(libunwind-objects)
+ libgcc_eh.a: $(libgcc-eh-objects)
+
+-libgcc.a libgcov.a libunwind.a libgcc_eh.a:
++libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a:
+ -rm -f $@
+
+ objects="$(objects)"; \
+@@ -958,7 +959,7 @@ all: libunwind.a
+ endif
+
+ ifeq ($(enable_shared),yes)
+-all: libgcc_eh.a libgcc_s$(SHLIB_EXT)
++all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT)
+ ifneq ($(LIBUNWIND),)
+ all: libunwind$(SHLIB_EXT)
+ libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT)
+@@ -1164,6 +1165,10 @@ install-shared:
+ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a
+ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a
+
++ $(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/
++ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a
++ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a
++
+ $(subst @multilib_dir@,$(MULTIDIR),$(subst \
+ @shlib_base_name@,libgcc_s,$(subst \
+ @shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL))))
diff --git a/external/subpack/devel/gcc/patches-12.x/840-armv4_pass_fix-v4bx_to_ld.patch b/external/subpack/devel/gcc/patches-12.x/840-armv4_pass_fix-v4bx_to_ld.patch
new file mode 100644
index 0000000..e3cb616
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/840-armv4_pass_fix-v4bx_to_ld.patch
@@ -0,0 +1,28 @@
+commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc
+Author: Imre Kaloz <kaloz@openwrt.org>
+Date: Wed Feb 2 19:34:36 2011 +0000
+
+ add armv4 fixup patches
+
+ SVN-Revision: 25322
+
+
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -91,10 +91,15 @@
+ #define MUSL_DYNAMIC_LINKER \
+ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1"
+
++/* For armv4 we pass --fix-v4bx to linker to support EABI */
++#undef TARGET_FIX_V4BX_SPEC
++#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\
++ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
+ use the GNU/Linux version, not the generic BPABI version. */
+ #undef LINK_SPEC
+-#define LINK_SPEC EABI_LINK_SPEC \
++#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC \
+ LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \
+ LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC)
+
diff --git a/external/subpack/devel/gcc/patches-12.x/850-use_shared_libgcc.patch b/external/subpack/devel/gcc/patches-12.x/850-use_shared_libgcc.patch
new file mode 100644
index 0000000..7be30f3
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/850-use_shared_libgcc.patch
@@ -0,0 +1,54 @@
+commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun Feb 12 20:25:47 2012 +0000
+
+ gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary
+
+ SVN-Revision: 30486
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -132,10 +132,6 @@
+ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} " \
+ LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)
+
+-/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we
+- do not use -lfloat. */
+-#undef LIBGCC_SPEC
+-
+ /* Clear the instruction cache from `beg' to `end'. This is
+ implemented in lib1funcs.S, so ensure an error if this definition
+ is used. */
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -71,6 +71,10 @@ see the files COPYING3 and COPYING.RUNTI
+ builtin_version ("CRuntime_Musl"); \
+ } while (0)
+
++#ifndef LIBGCC_SPEC
++#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}"
++#endif
++
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+ uClibc or Bionic or musl is the default C library and whether
+ -muclibc or -mglibc or -mbionic or -mmusl has been passed to change
+--- a/libgcc/mkmap-symver.awk
++++ b/libgcc/mkmap-symver.awk
+@@ -136,5 +136,5 @@ function output(lib) {
+ else if (inherit[lib])
+ printf("} %s;\n", inherit[lib]);
+ else
+- printf ("\n local:\n\t*;\n};\n");
++ printf ("\n\t*;\n};\n");
+ }
+--- a/gcc/config/rs6000/linux.h
++++ b/gcc/config/rs6000/linux.h
+@@ -67,6 +67,9 @@
+ #undef CPP_OS_DEFAULT_SPEC
+ #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)"
+
++#undef LIBGCC_SPEC
++#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc"
++
+ #undef LINK_SHLIB_SPEC
+ #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}} \
+ %{static-pie:-static -pie --no-dynamic-linker -z text}"
diff --git a/external/subpack/devel/gcc/patches-12.x/851-libgcc_no_compat.patch b/external/subpack/devel/gcc/patches-12.x/851-libgcc_no_compat.patch
new file mode 100644
index 0000000..d710e40
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/851-libgcc_no_compat.patch
@@ -0,0 +1,22 @@
+commit 64661de100da1ec1061ef3e5e400285dce115e6b
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun May 10 13:16:35 2015 +0000
+
+ gcc: add some size optimization patches
+
+ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+
+ SVN-Revision: 45664
+
+--- a/libgcc/config/t-libunwind
++++ b/libgcc/config/t-libunwind
+@@ -2,8 +2,7 @@
+
+ HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER
+
+-LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \
+- $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c
++LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
+ LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
+
+ # Override the default value from t-slibgcc-elf-ver and mention -lunwind
diff --git a/external/subpack/devel/gcc/patches-12.x/870-ppc_no_crtsavres.patch b/external/subpack/devel/gcc/patches-12.x/870-ppc_no_crtsavres.patch
new file mode 100644
index 0000000..e51079d
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/870-ppc_no_crtsavres.patch
@@ -0,0 +1,11 @@
+--- a/gcc/config/rs6000/rs6000-logue.cc
++++ b/gcc/config/rs6000/rs6000-logue.cc
+@@ -348,7 +348,7 @@ rs6000_savres_strategy (rs6000_stack_t *
+ /* Define cutoff for using out-of-line functions to save registers. */
+ if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
+ {
+- if (!optimize_size)
++ if (1)
+ {
+ strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
+ strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
diff --git a/external/subpack/devel/gcc/patches-12.x/881-no_tm_section.patch b/external/subpack/devel/gcc/patches-12.x/881-no_tm_section.patch
new file mode 100644
index 0000000..2029910
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/881-no_tm_section.patch
@@ -0,0 +1,11 @@
+--- a/libgcc/crtstuff.c
++++ b/libgcc/crtstuff.c
+@@ -152,7 +152,7 @@ call_ ## FUNC (void) \
+ #endif
+
+ #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF)
+-# define USE_TM_CLONE_REGISTRY 1
++# define USE_TM_CLONE_REGISTRY 0
+ #elif !defined(USE_TM_CLONE_REGISTRY)
+ # define USE_TM_CLONE_REGISTRY 0
+ #endif
diff --git a/external/subpack/devel/gcc/patches-12.x/900-bad-mips16-crt.patch b/external/subpack/devel/gcc/patches-12.x/900-bad-mips16-crt.patch
new file mode 100644
index 0000000..dd6e9dc
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/900-bad-mips16-crt.patch
@@ -0,0 +1,9 @@
+--- a/libgcc/config/mips/t-mips16
++++ b/libgcc/config/mips/t-mips16
+@@ -43,3 +43,6 @@ SYNC_CFLAGS = -mno-mips16
+
+ # Version these symbols if building libgcc.so.
+ SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver
++
++CRTSTUFF_T_CFLAGS += -mno-mips16
++CRTSTUFF_T_CFLAGS_S += -mno-mips16
diff --git a/external/subpack/devel/gcc/patches-12.x/910-mbsd_multi.patch b/external/subpack/devel/gcc/patches-12.x/910-mbsd_multi.patch
new file mode 100644
index 0000000..9233c6a
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/910-mbsd_multi.patch
@@ -0,0 +1,146 @@
+commit 99368862e44740ff4fd33760893f04e14f9dbdf1
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Tue Jul 31 00:52:27 2007 +0000
+
+ Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly
+
+ SVN-Revision: 8256
+
+ This patch brings over a feature from MirBSD:
+ * -fhonour-copts
+ If this option is not given, it's warned (depending
+ on environment variables). This is to catch errors
+ of misbuilt packages which override CFLAGS themselves.
+
+ This patch was authored by Thorsten Glaser <tg at mirbsd.de>
+ with copyright assignment to the FSF in effect.
+
+--- a/gcc/c-family/c-opts.cc
++++ b/gcc/c-family/c-opts.cc
+@@ -107,6 +107,9 @@ static dump_flags_t original_dump_flags;
+ /* Whether any standard preincluded header has been preincluded. */
+ static bool done_preinclude;
+
++/* Check if a port honours COPTS. */
++static int honour_copts = 0;
++
+ static void handle_OPT_d (const char *);
+ static void set_std_cxx98 (int);
+ static void set_std_cxx11 (int);
+@@ -478,6 +481,12 @@ c_common_handle_option (size_t scode, co
+ flag_no_builtin = !value;
+ break;
+
++ case OPT_fhonour_copts:
++ if (c_language == clk_c) {
++ honour_copts++;
++ }
++ break;
++
+ case OPT_fconstant_string_class_:
+ constant_string_class_name = arg;
+ break;
+@@ -1218,6 +1227,47 @@ c_common_init (void)
+ return false;
+ }
+
++ if (c_language == clk_c) {
++ char *ev = getenv ("GCC_HONOUR_COPTS");
++ int evv;
++ if (ev == NULL)
++ evv = -1;
++ else if ((*ev == '0') || (*ev == '\0'))
++ evv = 0;
++ else if (*ev == '1')
++ evv = 1;
++ else if (*ev == '2')
++ evv = 2;
++ else if (*ev == 's')
++ evv = -1;
++ else {
++ warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1");
++ evv = 1; /* maybe depend this on something like MIRBSD_NATIVE? */
++ }
++ if (evv == 1) {
++ if (honour_copts == 0) {
++ error ("someone does not honour COPTS at all in lenient mode");
++ return false;
++ } else if (honour_copts != 1) {
++ warning (0, "someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ }
++ } else if (evv == 2) {
++ if (honour_copts == 0) {
++ error ("someone does not honour COPTS at all in strict mode");
++ return false;
++ } else if (honour_copts != 1) {
++ error ("someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ return false;
++ }
++ } else if (evv == 0) {
++ if (honour_copts != 1)
++ inform (UNKNOWN_LOCATION, "someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ }
++ }
++
+ return true;
+ }
+
+--- a/gcc/c-family/c.opt
++++ b/gcc/c-family/c.opt
+@@ -1755,6 +1755,9 @@ C++ ObjC++ Optimization Alias(fexception
+ fhonor-std
+ C++ ObjC++ WarnRemoved
+
++fhonour-copts
++C ObjC C++ ObjC++ RejectNegative
++
+ fhosted
+ C ObjC
+ Assume normal C execution environment.
+--- a/gcc/common.opt
++++ b/gcc/common.opt
+@@ -1770,6 +1770,9 @@ fharden-conditional-branches
+ Common Var(flag_harden_conditional_branches) Optimization
+ Harden conditional branches by checking reversed conditions.
+
++fhonour-copts
++Common RejectNegative
++
+ ; Nonzero means ignore `#ident' directives. 0 means handle them.
+ ; Generate position-independent code for executables if possible
+ ; On SVR4 targets, it also controls whether or not to emit a
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -9597,6 +9597,17 @@ This option is only supported for C and
+ @option{-Wall} and by @option{-Wpedantic}, which can be disabled with
+ @option{-Wno-pointer-sign}.
+
++@item -fhonour-copts
++@opindex fhonour-copts
++If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not
++given at least once, and warn if it is given more than once.
++If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not
++given exactly once.
++If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option
++is not given exactly once.
++The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}.
++This flag and environment variable only affect the C language.
++
+ @item -Wstack-protector
+ @opindex Wstack-protector
+ @opindex Wno-stack-protector
+--- a/gcc/opts.cc
++++ b/gcc/opts.cc
+@@ -2699,6 +2699,9 @@ common_handle_option (struct gcc_options
+ add_comma_separated_to_vector (&opts->x_flag_ignored_attributes, arg);
+ break;
+
++ case OPT_fhonour_copts:
++ break;
++
+ case OPT_Werror:
+ dc->warning_as_error_requested = value;
+ break;
diff --git a/external/subpack/devel/gcc/patches-12.x/920-specs_nonfatal_getenv.patch b/external/subpack/devel/gcc/patches-12.x/920-specs_nonfatal_getenv.patch
new file mode 100644
index 0000000..59bd350
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/920-specs_nonfatal_getenv.patch
@@ -0,0 +1,22 @@
+Author: Jo-Philipp Wich <jow@openwrt.org>
+Date: Sat Apr 21 03:02:39 2012 +0000
+
+ gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset
+
+ SVN-Revision: 31390
+
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -10186,8 +10186,10 @@ getenv_spec_function (int argc, const ch
+ }
+
+ if (!value)
+- fatal_error (input_location,
+- "environment variable %qs not defined", varname);
++ {
++ warning (input_location, "environment variable %qs not defined", varname);
++ value = "";
++ }
+
+ /* We have to escape every character of the environment variable so
+ they are not interpreted as active spec characters. A
diff --git a/external/subpack/devel/gcc/patches-12.x/960-gotools-fix-compilation-when-making-cross-compiler.patch b/external/subpack/devel/gcc/patches-12.x/960-gotools-fix-compilation-when-making-cross-compiler.patch
new file mode 100644
index 0000000..b1d7576
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/960-gotools-fix-compilation-when-making-cross-compiler.patch
@@ -0,0 +1,67 @@
+From dda6b050cd74a352670787a294596a9c56c21327 Mon Sep 17 00:00:00 2001
+From: Yousong Zhou <yszhou4tech@gmail.com>
+Date: Fri, 4 May 2018 18:20:53 +0800
+Subject: [PATCH] gotools: fix compilation when making cross compiler
+
+libgo is "the runtime support library for the Go programming language.
+This library is intended for use with the Go frontend."
+
+gccgo will link target files with libgo.so which depends on libgcc_s.so.1, but
+the linker will complain that it cannot find it. That's because shared libgcc
+is not present in the install directory yet. libgo.so was made without problem
+because gcc will emit -lgcc_s when compiled with -shared option. When gotools
+were being made, it was supplied with -static-libgcc thus no link option was
+provided. Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec
+for linking with libgo.so
+
+- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation
+- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html
+
+When 3-pass GCC compilation is used, shared libgcc runtime libraries will be
+available after gcc pass2 completed and will meet the gotools link requirement
+at gcc pass3
+---
+ gotools/Makefile.am | 4 +++-
+ gotools/Makefile.in | 4 +++-
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/gotools/Makefile.am
++++ b/gotools/Makefile.am
+@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+
+ libgodir = ../$(target_noncanonical)/libgo
++libgccdir = ../$(target_noncanonical)/libgcc
+ LIBGODEP = $(libgodir)/libgo.la
+
+ LIBGOTOOL = $(libgodir)/libgotool.a
+@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+
+ AM_GOCFLAGS = -I $(libgodir)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \
++ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s
+ GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+
+ libgosrcdir = $(srcdir)/../libgo/go
+--- a/gotools/Makefile.in
++++ b/gotools/Makefile.in
+@@ -337,6 +337,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd
+ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+ libgodir = ../$(target_noncanonical)/libgo
++libgccdir = ../$(target_noncanonical)/libgcc
+ LIBGODEP = $(libgodir)/libgo.la
+ LIBGOTOOL = $(libgodir)/libgotool.a
+ @NATIVE_FALSE@GOCOMPILER = $(GOC)
+@@ -346,7 +347,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a
+ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+ AM_GOCFLAGS = -I $(libgodir)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \
++ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s
+ GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+ libgosrcdir = $(srcdir)/../libgo/go
+ cmdsrcdir = $(libgosrcdir)/cmd
diff --git a/external/subpack/devel/gcc/patches-12.x/970-macos_arm64-building-fix.patch b/external/subpack/devel/gcc/patches-12.x/970-macos_arm64-building-fix.patch
new file mode 100644
index 0000000..8973044
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-12.x/970-macos_arm64-building-fix.patch
@@ -0,0 +1,45 @@
+commit 9c6e71079b46ad5433165feaa2001450f2017b56
+Author: Przemysław Buczkowski <prem@prem.moe>
+Date: Mon Aug 16 13:16:21 2021 +0100
+
+ GCC: Patch for Apple Silicon compatibility
+
+ This patch fixes a linker error occuring when compiling
+ the cross-compiler on macOS and ARM64 architecture.
+
+ Adapted from:
+ https://github.com/richfelker/musl-cross-make/issues/116#issuecomment-823612404
+
+ Change-Id: Ia3ee98a163bbb62689f42e2da83a5ef36beb0913
+ Reviewed-on: https://review.haiku-os.org/c/buildtools/+/4329
+ Reviewed-by: John Scipione <jscipione@gmail.com>
+ Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
+
+--- a/gcc/config/aarch64/aarch64.h
++++ b/gcc/config/aarch64/aarch64.h
+@@ -1293,7 +1293,7 @@ extern const char *aarch64_rewrite_mcpu
+ #define MCPU_TO_MARCH_SPEC_FUNCTIONS \
+ { "rewrite_mcpu", aarch64_rewrite_mcpu },
+
+-#if defined(__aarch64__)
++#if defined(__aarch64__) && ! defined(__APPLE__)
+ extern const char *host_detect_local_cpu (int argc, const char **argv);
+ #define HAVE_LOCAL_CPU_DETECT
+ # define EXTRA_SPEC_FUNCTIONS \
+--- a/gcc/config/host-darwin.cc
++++ b/gcc/config/host-darwin.cc
+@@ -23,6 +23,8 @@
+ #include "options.h"
+ #include "diagnostic-core.h"
+ #include "config/host-darwin.h"
++#include "hosthooks.h"
++#include "hosthooks-def.h"
+ #include <errno.h>
+
+ /* For Darwin (macOS only) platforms, without ASLR (PIE) enabled on the
+@@ -181,3 +183,5 @@ darwin_gt_pch_use_address (void *&addr,
+
+ return 1;
+ }
++
++const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;
diff --git a/external/subpack/devel/gcc/patches-13.x/002-case_insensitive.patch b/external/subpack/devel/gcc/patches-13.x/002-case_insensitive.patch
new file mode 100644
index 0000000..409497e
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/002-case_insensitive.patch
@@ -0,0 +1,24 @@
+commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun Oct 19 21:45:51 2014 +0000
+
+ gcc: do not assume that the Mac OS X filesystem is case insensitive
+
+ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+
+ SVN-Revision: 42973
+
+--- a/include/filenames.h
++++ b/include/filenames.h
+@@ -44,11 +44,6 @@ extern "C" {
+ # define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c)
+ # define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f)
+ #else /* not DOSish */
+-# if defined(__APPLE__)
+-# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM
+-# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1
+-# endif
+-# endif /* __APPLE__ */
+ # define HAS_DRIVE_SPEC(f) (0)
+ # define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c)
+ # define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f)
diff --git a/external/subpack/devel/gcc/patches-13.x/003-dont-choke-when-building-32bit-on-64bit.patch b/external/subpack/devel/gcc/patches-13.x/003-dont-choke-when-building-32bit-on-64bit.patch
new file mode 100644
index 0000000..c41f35e
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/003-dont-choke-when-building-32bit-on-64bit.patch
@@ -0,0 +1,13 @@
+--- a/gcc/real.h
++++ b/gcc/real.h
+@@ -77,8 +77,10 @@ struct GTY(()) real_value {
+ + (REAL_VALUE_TYPE_SIZE%HOST_BITS_PER_WIDE_INT ? 1 : 0)) /* round up */
+
+ /* Verify the guess. */
++#ifndef __LP64__
+ extern char test_real_width
+ [sizeof (REAL_VALUE_TYPE) <= REAL_WIDTH * sizeof (HOST_WIDE_INT) ? 1 : -1];
++#endif
+
+ /* Calculate the format for CONST_DOUBLE. We need as many slots as
+ are necessary to overlay a REAL_VALUE_TYPE on them. This could be
diff --git a/external/subpack/devel/gcc/patches-13.x/010-documentation.patch b/external/subpack/devel/gcc/patches-13.x/010-documentation.patch
new file mode 100644
index 0000000..9646568
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/010-documentation.patch
@@ -0,0 +1,35 @@
+commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2
+Author: Luka Perkov <luka@openwrt.org>
+Date: Tue Feb 26 16:16:33 2013 +0000
+
+ gcc: don't build documentation
+
+ This closes #13039.
+
+ Signed-off-by: Luka Perkov <luka@openwrt.org>
+
+ SVN-Revision: 35807
+
+--- a/gcc/Makefile.in
++++ b/gcc/Makefile.in
+@@ -3397,18 +3397,10 @@ doc/gcc.info: $(TEXI_GCC_FILES)
+ doc/gccint.info: $(TEXI_GCCINT_FILES)
+ doc/cppinternals.info: $(TEXI_CPPINT_FILES)
+
+-doc/%.info: %.texi
+- if [ x$(BUILD_INFO) = xinfo ]; then \
+- $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \
+- -I $(gcc_docdir)/include -o $@ $<; \
+- fi
++doc/%.info:
+
+ # Duplicate entry to handle renaming of gccinstall.info
+-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES)
+- if [ x$(BUILD_INFO) = xinfo ]; then \
+- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
+- -I $(gcc_docdir)/include -o $@ $<; \
+- fi
++doc/gccinstall.info:
+
+ doc/cpp.dvi: $(TEXI_CPP_FILES)
+ doc/gcc.dvi: $(TEXI_GCC_FILES)
diff --git a/external/subpack/devel/gcc/patches-13.x/110-Fix-MIPS-PR-84790.patch b/external/subpack/devel/gcc/patches-13.x/110-Fix-MIPS-PR-84790.patch
new file mode 100644
index 0000000..856fd6a
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/110-Fix-MIPS-PR-84790.patch
@@ -0,0 +1,20 @@
+Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.
+MIPS16 functions have a static assembler prologue which clobbers
+registers v0 and v1. Add these register clobbers to function call
+instructions.
+
+--- a/gcc/config/mips/mips.cc
++++ b/gcc/config/mips/mips.cc
+@@ -3134,6 +3134,12 @@ mips_emit_call_insn (rtx pattern, rtx or
+ emit_insn (gen_update_got_version ());
+ }
+
++ if (TARGET_MIPS16 && TARGET_USE_GOT)
++ {
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));
++ }
++
+ if (TARGET_MIPS16
+ && TARGET_EXPLICIT_RELOCS
+ && TARGET_CALL_CLOBBERED_GP)
diff --git a/external/subpack/devel/gcc/patches-13.x/230-musl_libssp.patch b/external/subpack/devel/gcc/patches-13.x/230-musl_libssp.patch
new file mode 100644
index 0000000..fee068e
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/230-musl_libssp.patch
@@ -0,0 +1,13 @@
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -972,7 +972,9 @@ proper position among the other output f
+ #endif
+
+ #ifndef LINK_SSP_SPEC
+-#ifdef TARGET_LIBC_PROVIDES_SSP
++#if DEFAULT_LIBC == LIBC_MUSL
++#define LINK_SSP_SPEC "-lssp_nonshared"
++#elif defined(TARGET_LIBC_PROVIDES_SSP)
+ #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
+ "|fstack-protector-strong|fstack-protector-explicit:}"
+ #else
diff --git a/external/subpack/devel/gcc/patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch b/external/subpack/devel/gcc/patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch
new file mode 100644
index 0000000..2ca42ad
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch
@@ -0,0 +1,21 @@
+commit ecf7671b769fe96f7b5134be442089f8bdba55d2
+Author: Felix Fietkau <nbd@nbd.name>
+Date: Thu Aug 4 20:29:45 2016 +0200
+
+gcc: add a patch to generate better code with Os on mips
+
+Also happens to reduce compressed code size a bit
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+
+--- a/gcc/config/mips/mips.cc
++++ b/gcc/config/mips/mips.cc
+@@ -20219,7 +20219,7 @@ mips_option_override (void)
+ flag_pcc_struct_return = 0;
+
+ /* Decide which rtx_costs structure to use. */
+- if (optimize_size)
++ if (0 && optimize_size)
+ mips_cost = &mips_rtx_cost_optimize_size;
+ else
+ mips_cost = &mips_rtx_cost_data[mips_tune];
diff --git a/external/subpack/devel/gcc/patches-13.x/810-arm-softfloat-libgcc.patch b/external/subpack/devel/gcc/patches-13.x/810-arm-softfloat-libgcc.patch
new file mode 100644
index 0000000..5c9d86a
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/810-arm-softfloat-libgcc.patch
@@ -0,0 +1,33 @@
+commit 8570c4be394cff7282f332f97da2ff569a927ddb
+Author: Imre Kaloz <kaloz@openwrt.org>
+Date: Wed Feb 2 20:06:12 2011 +0000
+
+ fixup arm soft-float symbols
+
+ SVN-Revision: 25325
+
+--- a/libgcc/config/arm/t-linux
++++ b/libgcc/config/arm/t-linux
+@@ -1,6 +1,10 @@
+ LIB1ASMSRC = arm/lib1funcs.S
+ LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \
+- _ctzsi2 _arm_addsubdf3 _arm_addsubsf3
++ _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \
++ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \
++ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \
++ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \
++ _arm_fixsfsi _arm_fixunssfsi
+
+ # Just for these, we omit the frame pointer since it makes such a big
+ # difference.
+--- a/gcc/config/arm/linux-elf.h
++++ b/gcc/config/arm/linux-elf.h
+@@ -58,8 +58,6 @@
+ %{shared:-lc} \
+ %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
+
+-#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
+-
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #define LINUX_TARGET_LINK_SPEC "%{h*} \
diff --git a/external/subpack/devel/gcc/patches-13.x/820-libgcc_pic.patch b/external/subpack/devel/gcc/patches-13.x/820-libgcc_pic.patch
new file mode 100644
index 0000000..7d10298
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/820-libgcc_pic.patch
@@ -0,0 +1,44 @@
+commit c96312958c0621e72c9b32da5bc224ffe2161384
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Mon Oct 19 23:26:09 2009 +0000
+
+ gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow)
+
+ SVN-Revision: 18086
+
+--- a/libgcc/Makefile.in
++++ b/libgcc/Makefile.in
+@@ -933,11 +933,12 @@ $(libgcov-driver-objects): %$(objext): $
+
+ # Static libraries.
+ libgcc.a: $(libgcc-objects)
++libgcc_pic.a: $(libgcc-s-objects)
+ libgcov.a: $(libgcov-objects)
+ libunwind.a: $(libunwind-objects)
+ libgcc_eh.a: $(libgcc-eh-objects)
+
+-libgcc.a libgcov.a libunwind.a libgcc_eh.a:
++libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a:
+ -rm -f $@
+
+ objects="$(objects)"; \
+@@ -961,7 +962,7 @@ all: libunwind.a
+ endif
+
+ ifeq ($(enable_shared),yes)
+-all: libgcc_eh.a libgcc_s$(SHLIB_EXT)
++all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT)
+ ifneq ($(LIBUNWIND),)
+ all: libunwind$(SHLIB_EXT)
+ libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT)
+@@ -1167,6 +1168,10 @@ install-shared:
+ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a
+ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a
+
++ $(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/
++ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a
++ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a
++
+ $(subst @multilib_dir@,$(MULTIDIR),$(subst \
+ @shlib_base_name@,libgcc_s,$(subst \
+ @shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL))))
diff --git a/external/subpack/devel/gcc/patches-13.x/840-armv4_pass_fix-v4bx_to_ld.patch b/external/subpack/devel/gcc/patches-13.x/840-armv4_pass_fix-v4bx_to_ld.patch
new file mode 100644
index 0000000..82935f3
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/840-armv4_pass_fix-v4bx_to_ld.patch
@@ -0,0 +1,28 @@
+commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc
+Author: Imre Kaloz <kaloz@openwrt.org>
+Date: Wed Feb 2 19:34:36 2011 +0000
+
+ add armv4 fixup patches
+
+ SVN-Revision: 25322
+
+
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -88,10 +88,15 @@
+ #define MUSL_DYNAMIC_LINKER \
+ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1"
+
++/* For armv4 we pass --fix-v4bx to linker to support EABI */
++#undef TARGET_FIX_V4BX_SPEC
++#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\
++ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
+ use the GNU/Linux version, not the generic BPABI version. */
+ #undef LINK_SPEC
+-#define LINK_SPEC EABI_LINK_SPEC \
++#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC \
+ LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \
+ LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC)
+
diff --git a/external/subpack/devel/gcc/patches-13.x/850-use_shared_libgcc.patch b/external/subpack/devel/gcc/patches-13.x/850-use_shared_libgcc.patch
new file mode 100644
index 0000000..f4505ee
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/850-use_shared_libgcc.patch
@@ -0,0 +1,54 @@
+commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun Feb 12 20:25:47 2012 +0000
+
+ gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary
+
+ SVN-Revision: 30486
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -129,10 +129,6 @@
+ "%{Ofast|ffast-math|funsafe-math-optimizations:%{!shared:crtfastmath.o%s}} " \
+ LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)
+
+-/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we
+- do not use -lfloat. */
+-#undef LIBGCC_SPEC
+-
+ /* Clear the instruction cache from `beg' to `end'. This is
+ implemented in lib1funcs.S, so ensure an error if this definition
+ is used. */
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -58,6 +58,10 @@ see the files COPYING3 and COPYING.RUNTI
+ builtin_assert ("system=posix"); \
+ } while (0)
+
++#ifndef LIBGCC_SPEC
++#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}"
++#endif
++
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+ uClibc or Bionic or musl is the default C library and whether
+ -muclibc or -mglibc or -mbionic or -mmusl has been passed to change
+--- a/libgcc/mkmap-symver.awk
++++ b/libgcc/mkmap-symver.awk
+@@ -136,5 +136,5 @@ function output(lib) {
+ else if (inherit[lib])
+ printf("} %s;\n", inherit[lib]);
+ else
+- printf ("\n local:\n\t*;\n};\n");
++ printf ("\n\t*;\n};\n");
+ }
+--- a/gcc/config/rs6000/linux.h
++++ b/gcc/config/rs6000/linux.h
+@@ -67,6 +67,9 @@
+ #undef CPP_OS_DEFAULT_SPEC
+ #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)"
+
++#undef LIBGCC_SPEC
++#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc"
++
+ #undef LINK_SHLIB_SPEC
+ #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}} \
+ %{static-pie:-static -pie --no-dynamic-linker -z text}"
diff --git a/external/subpack/devel/gcc/patches-13.x/851-libgcc_no_compat.patch b/external/subpack/devel/gcc/patches-13.x/851-libgcc_no_compat.patch
new file mode 100644
index 0000000..d710e40
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/851-libgcc_no_compat.patch
@@ -0,0 +1,22 @@
+commit 64661de100da1ec1061ef3e5e400285dce115e6b
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun May 10 13:16:35 2015 +0000
+
+ gcc: add some size optimization patches
+
+ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+
+ SVN-Revision: 45664
+
+--- a/libgcc/config/t-libunwind
++++ b/libgcc/config/t-libunwind
+@@ -2,8 +2,7 @@
+
+ HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER
+
+-LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \
+- $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c
++LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
+ LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
+
+ # Override the default value from t-slibgcc-elf-ver and mention -lunwind
diff --git a/external/subpack/devel/gcc/patches-13.x/870-ppc_no_crtsavres.patch b/external/subpack/devel/gcc/patches-13.x/870-ppc_no_crtsavres.patch
new file mode 100644
index 0000000..0dca688
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/870-ppc_no_crtsavres.patch
@@ -0,0 +1,11 @@
+--- a/gcc/config/rs6000/rs6000-logue.cc
++++ b/gcc/config/rs6000/rs6000-logue.cc
+@@ -344,7 +344,7 @@ rs6000_savres_strategy (rs6000_stack_t *
+ /* Define cutoff for using out-of-line functions to save registers. */
+ if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
+ {
+- if (!optimize_size)
++ if (1)
+ {
+ strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
+ strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
diff --git a/external/subpack/devel/gcc/patches-13.x/881-no_tm_section.patch b/external/subpack/devel/gcc/patches-13.x/881-no_tm_section.patch
new file mode 100644
index 0000000..2029910
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/881-no_tm_section.patch
@@ -0,0 +1,11 @@
+--- a/libgcc/crtstuff.c
++++ b/libgcc/crtstuff.c
+@@ -152,7 +152,7 @@ call_ ## FUNC (void) \
+ #endif
+
+ #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF)
+-# define USE_TM_CLONE_REGISTRY 1
++# define USE_TM_CLONE_REGISTRY 0
+ #elif !defined(USE_TM_CLONE_REGISTRY)
+ # define USE_TM_CLONE_REGISTRY 0
+ #endif
diff --git a/external/subpack/devel/gcc/patches-13.x/900-bad-mips16-crt.patch b/external/subpack/devel/gcc/patches-13.x/900-bad-mips16-crt.patch
new file mode 100644
index 0000000..dd6e9dc
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/900-bad-mips16-crt.patch
@@ -0,0 +1,9 @@
+--- a/libgcc/config/mips/t-mips16
++++ b/libgcc/config/mips/t-mips16
+@@ -43,3 +43,6 @@ SYNC_CFLAGS = -mno-mips16
+
+ # Version these symbols if building libgcc.so.
+ SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver
++
++CRTSTUFF_T_CFLAGS += -mno-mips16
++CRTSTUFF_T_CFLAGS_S += -mno-mips16
diff --git a/external/subpack/devel/gcc/patches-13.x/910-mbsd_multi.patch b/external/subpack/devel/gcc/patches-13.x/910-mbsd_multi.patch
new file mode 100644
index 0000000..4138e79
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/910-mbsd_multi.patch
@@ -0,0 +1,146 @@
+commit 99368862e44740ff4fd33760893f04e14f9dbdf1
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Tue Jul 31 00:52:27 2007 +0000
+
+ Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly
+
+ SVN-Revision: 8256
+
+ This patch brings over a feature from MirBSD:
+ * -fhonour-copts
+ If this option is not given, it's warned (depending
+ on environment variables). This is to catch errors
+ of misbuilt packages which override CFLAGS themselves.
+
+ This patch was authored by Thorsten Glaser <tg at mirbsd.de>
+ with copyright assignment to the FSF in effect.
+
+--- a/gcc/c-family/c-opts.cc
++++ b/gcc/c-family/c-opts.cc
+@@ -104,6 +104,9 @@ static size_t include_cursor;
+ /* Whether any standard preincluded header has been preincluded. */
+ static bool done_preinclude;
+
++/* Check if a port honours COPTS. */
++static int honour_copts = 0;
++
+ static void handle_OPT_d (const char *);
+ static void set_std_cxx98 (int);
+ static void set_std_cxx11 (int);
+@@ -475,6 +478,12 @@ c_common_handle_option (size_t scode, co
+ flag_no_builtin = !value;
+ break;
+
++ case OPT_fhonour_copts:
++ if (c_language == clk_c) {
++ honour_copts++;
++ }
++ break;
++
+ case OPT_fconstant_string_class_:
+ constant_string_class_name = arg;
+ break;
+@@ -1228,6 +1237,47 @@ c_common_init (void)
+ return false;
+ }
+
++ if (c_language == clk_c) {
++ char *ev = getenv ("GCC_HONOUR_COPTS");
++ int evv;
++ if (ev == NULL)
++ evv = -1;
++ else if ((*ev == '0') || (*ev == '\0'))
++ evv = 0;
++ else if (*ev == '1')
++ evv = 1;
++ else if (*ev == '2')
++ evv = 2;
++ else if (*ev == 's')
++ evv = -1;
++ else {
++ warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1");
++ evv = 1; /* maybe depend this on something like MIRBSD_NATIVE? */
++ }
++ if (evv == 1) {
++ if (honour_copts == 0) {
++ error ("someone does not honour COPTS at all in lenient mode");
++ return false;
++ } else if (honour_copts != 1) {
++ warning (0, "someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ }
++ } else if (evv == 2) {
++ if (honour_copts == 0) {
++ error ("someone does not honour COPTS at all in strict mode");
++ return false;
++ } else if (honour_copts != 1) {
++ error ("someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ return false;
++ }
++ } else if (evv == 0) {
++ if (honour_copts != 1)
++ inform (UNKNOWN_LOCATION, "someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ }
++ }
++
+ return true;
+ }
+
+--- a/gcc/c-family/c.opt
++++ b/gcc/c-family/c.opt
+@@ -1837,6 +1837,9 @@ C++ ObjC++ Optimization Alias(fexception
+ fhonor-std
+ C++ ObjC++ WarnRemoved
+
++fhonour-copts
++C ObjC C++ ObjC++ RejectNegative
++
+ fhosted
+ C ObjC
+ Assume normal C execution environment.
+--- a/gcc/common.opt
++++ b/gcc/common.opt
+@@ -1801,6 +1801,9 @@ fharden-conditional-branches
+ Common Var(flag_harden_conditional_branches) Optimization
+ Harden conditional branches by checking reversed conditions.
+
++fhonour-copts
++Common RejectNegative
++
+ ; Nonzero means ignore `#ident' directives. 0 means handle them.
+ ; Generate position-independent code for executables if possible
+ ; On SVR4 targets, it also controls whether or not to emit a
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -10065,6 +10065,17 @@ This option is only supported for C and
+ @option{-Wall} and by @option{-Wpedantic}, which can be disabled with
+ @option{-Wno-pointer-sign}.
+
++@item -fhonour-copts
++@opindex fhonour-copts
++If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not
++given at least once, and warn if it is given more than once.
++If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not
++given exactly once.
++If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option
++is not given exactly once.
++The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}.
++This flag and environment variable only affect the C language.
++
+ @opindex Wstack-protector
+ @opindex Wno-stack-protector
+ @item -Wstack-protector
+--- a/gcc/opts.cc
++++ b/gcc/opts.cc
+@@ -2767,6 +2767,9 @@ common_handle_option (struct gcc_options
+ add_comma_separated_to_vector (&opts->x_flag_ignored_attributes, arg);
+ break;
+
++ case OPT_fhonour_copts:
++ break;
++
+ case OPT_Werror:
+ dc->warning_as_error_requested = value;
+ break;
diff --git a/external/subpack/devel/gcc/patches-13.x/920-specs_nonfatal_getenv.patch b/external/subpack/devel/gcc/patches-13.x/920-specs_nonfatal_getenv.patch
new file mode 100644
index 0000000..265ca22
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/920-specs_nonfatal_getenv.patch
@@ -0,0 +1,22 @@
+Author: Jo-Philipp Wich <jow@openwrt.org>
+Date: Sat Apr 21 03:02:39 2012 +0000
+
+ gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset
+
+ SVN-Revision: 31390
+
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -10174,8 +10174,10 @@ getenv_spec_function (int argc, const ch
+ }
+
+ if (!value)
+- fatal_error (input_location,
+- "environment variable %qs not defined", varname);
++ {
++ warning (input_location, "environment variable %qs not defined", varname);
++ value = "";
++ }
+
+ /* We have to escape every character of the environment variable so
+ they are not interpreted as active spec characters. A
diff --git a/external/subpack/devel/gcc/patches-13.x/960-gotools-fix-compilation-when-making-cross-compiler.patch b/external/subpack/devel/gcc/patches-13.x/960-gotools-fix-compilation-when-making-cross-compiler.patch
new file mode 100644
index 0000000..b1d7576
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/960-gotools-fix-compilation-when-making-cross-compiler.patch
@@ -0,0 +1,67 @@
+From dda6b050cd74a352670787a294596a9c56c21327 Mon Sep 17 00:00:00 2001
+From: Yousong Zhou <yszhou4tech@gmail.com>
+Date: Fri, 4 May 2018 18:20:53 +0800
+Subject: [PATCH] gotools: fix compilation when making cross compiler
+
+libgo is "the runtime support library for the Go programming language.
+This library is intended for use with the Go frontend."
+
+gccgo will link target files with libgo.so which depends on libgcc_s.so.1, but
+the linker will complain that it cannot find it. That's because shared libgcc
+is not present in the install directory yet. libgo.so was made without problem
+because gcc will emit -lgcc_s when compiled with -shared option. When gotools
+were being made, it was supplied with -static-libgcc thus no link option was
+provided. Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec
+for linking with libgo.so
+
+- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation
+- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html
+
+When 3-pass GCC compilation is used, shared libgcc runtime libraries will be
+available after gcc pass2 completed and will meet the gotools link requirement
+at gcc pass3
+---
+ gotools/Makefile.am | 4 +++-
+ gotools/Makefile.in | 4 +++-
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/gotools/Makefile.am
++++ b/gotools/Makefile.am
+@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+
+ libgodir = ../$(target_noncanonical)/libgo
++libgccdir = ../$(target_noncanonical)/libgcc
+ LIBGODEP = $(libgodir)/libgo.la
+
+ LIBGOTOOL = $(libgodir)/libgotool.a
+@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+
+ AM_GOCFLAGS = -I $(libgodir)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \
++ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s
+ GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+
+ libgosrcdir = $(srcdir)/../libgo/go
+--- a/gotools/Makefile.in
++++ b/gotools/Makefile.in
+@@ -337,6 +337,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd
+ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+ libgodir = ../$(target_noncanonical)/libgo
++libgccdir = ../$(target_noncanonical)/libgcc
+ LIBGODEP = $(libgodir)/libgo.la
+ LIBGOTOOL = $(libgodir)/libgotool.a
+ @NATIVE_FALSE@GOCOMPILER = $(GOC)
+@@ -346,7 +347,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a
+ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+ AM_GOCFLAGS = -I $(libgodir)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \
++ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s
+ GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+ libgosrcdir = $(srcdir)/../libgo/go
+ cmdsrcdir = $(libgosrcdir)/cmd
diff --git a/external/subpack/devel/gcc/patches-13.x/970-macos_arm64-building-fix.patch b/external/subpack/devel/gcc/patches-13.x/970-macos_arm64-building-fix.patch
new file mode 100644
index 0000000..a0470b1
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-13.x/970-macos_arm64-building-fix.patch
@@ -0,0 +1,45 @@
+commit 9c6e71079b46ad5433165feaa2001450f2017b56
+Author: Przemysław Buczkowski <prem@prem.moe>
+Date: Mon Aug 16 13:16:21 2021 +0100
+
+ GCC: Patch for Apple Silicon compatibility
+
+ This patch fixes a linker error occuring when compiling
+ the cross-compiler on macOS and ARM64 architecture.
+
+ Adapted from:
+ https://github.com/richfelker/musl-cross-make/issues/116#issuecomment-823612404
+
+ Change-Id: Ia3ee98a163bbb62689f42e2da83a5ef36beb0913
+ Reviewed-on: https://review.haiku-os.org/c/buildtools/+/4329
+ Reviewed-by: John Scipione <jscipione@gmail.com>
+ Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
+
+--- a/gcc/config/aarch64/aarch64.h
++++ b/gcc/config/aarch64/aarch64.h
+@@ -1195,7 +1195,7 @@ extern enum aarch64_code_model aarch64_c
+
+ /* Extra specs when building a native AArch64-hosted compiler.
+ Option rewriting rules based on host system. */
+-#if defined(__aarch64__)
++#if defined(__aarch64__) && ! defined(__APPLE__)
+ extern const char *host_detect_local_cpu (int argc, const char **argv);
+ #define HAVE_LOCAL_CPU_DETECT
+ # define EXTRA_SPEC_FUNCTIONS \
+--- a/gcc/config/host-darwin.cc
++++ b/gcc/config/host-darwin.cc
+@@ -23,6 +23,8 @@
+ #include "options.h"
+ #include "diagnostic-core.h"
+ #include "config/host-darwin.h"
++#include "hosthooks.h"
++#include "hosthooks-def.h"
+ #include <errno.h>
+
+ /* For Darwin (macOS only) platforms, without ASLR (PIE) enabled on the
+@@ -181,3 +183,5 @@ darwin_gt_pch_use_address (void *&addr,
+
+ return 1;
+ }
++
++const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;
diff --git a/external/subpack/devel/gcc/patches-14.x/002-case_insensitive.patch b/external/subpack/devel/gcc/patches-14.x/002-case_insensitive.patch
new file mode 100644
index 0000000..409497e
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/002-case_insensitive.patch
@@ -0,0 +1,24 @@
+commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun Oct 19 21:45:51 2014 +0000
+
+ gcc: do not assume that the Mac OS X filesystem is case insensitive
+
+ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+
+ SVN-Revision: 42973
+
+--- a/include/filenames.h
++++ b/include/filenames.h
+@@ -44,11 +44,6 @@ extern "C" {
+ # define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c)
+ # define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f)
+ #else /* not DOSish */
+-# if defined(__APPLE__)
+-# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM
+-# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1
+-# endif
+-# endif /* __APPLE__ */
+ # define HAS_DRIVE_SPEC(f) (0)
+ # define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c)
+ # define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f)
diff --git a/external/subpack/devel/gcc/patches-14.x/003-dont-choke-when-building-32bit-on-64bit.patch b/external/subpack/devel/gcc/patches-14.x/003-dont-choke-when-building-32bit-on-64bit.patch
new file mode 100644
index 0000000..c41f35e
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/003-dont-choke-when-building-32bit-on-64bit.patch
@@ -0,0 +1,13 @@
+--- a/gcc/real.h
++++ b/gcc/real.h
+@@ -77,8 +77,10 @@ struct GTY(()) real_value {
+ + (REAL_VALUE_TYPE_SIZE%HOST_BITS_PER_WIDE_INT ? 1 : 0)) /* round up */
+
+ /* Verify the guess. */
++#ifndef __LP64__
+ extern char test_real_width
+ [sizeof (REAL_VALUE_TYPE) <= REAL_WIDTH * sizeof (HOST_WIDE_INT) ? 1 : -1];
++#endif
+
+ /* Calculate the format for CONST_DOUBLE. We need as many slots as
+ are necessary to overlay a REAL_VALUE_TYPE on them. This could be
diff --git a/external/subpack/devel/gcc/patches-14.x/010-documentation.patch b/external/subpack/devel/gcc/patches-14.x/010-documentation.patch
new file mode 100644
index 0000000..7cf59d3
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/010-documentation.patch
@@ -0,0 +1,35 @@
+commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2
+Author: Luka Perkov <luka@openwrt.org>
+Date: Tue Feb 26 16:16:33 2013 +0000
+
+ gcc: don't build documentation
+
+ This closes #13039.
+
+ Signed-off-by: Luka Perkov <luka@openwrt.org>
+
+ SVN-Revision: 35807
+
+--- a/gcc/Makefile.in
++++ b/gcc/Makefile.in
+@@ -3549,18 +3549,10 @@ doc/gcc.info: $(TEXI_GCC_FILES)
+ doc/gccint.info: $(TEXI_GCCINT_FILES)
+ doc/cppinternals.info: $(TEXI_CPPINT_FILES)
+
+-doc/%.info: %.texi
+- if [ x$(BUILD_INFO) = xinfo ]; then \
+- $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \
+- -I $(gcc_docdir)/include -o $@ $<; \
+- fi
++doc/%.info:
+
+ # Duplicate entry to handle renaming of gccinstall.info
+-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES)
+- if [ x$(BUILD_INFO) = xinfo ]; then \
+- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
+- -I $(gcc_docdir)/include -o $@ $<; \
+- fi
++doc/gccinstall.info:
+
+ doc/cpp.dvi: $(TEXI_CPP_FILES)
+ doc/gcc.dvi: $(TEXI_GCC_FILES)
diff --git a/external/subpack/devel/gcc/patches-14.x/110-Fix-MIPS-PR-84790.patch b/external/subpack/devel/gcc/patches-14.x/110-Fix-MIPS-PR-84790.patch
new file mode 100644
index 0000000..bd5d1f3
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/110-Fix-MIPS-PR-84790.patch
@@ -0,0 +1,20 @@
+Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.
+MIPS16 functions have a static assembler prologue which clobbers
+registers v0 and v1. Add these register clobbers to function call
+instructions.
+
+--- a/gcc/config/mips/mips.cc
++++ b/gcc/config/mips/mips.cc
+@@ -3227,6 +3227,12 @@ mips_emit_call_insn (rtx pattern, rtx or
+ emit_insn (gen_update_got_version ());
+ }
+
++ if (TARGET_MIPS16 && TARGET_USE_GOT)
++ {
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));
++ }
++
+ if (TARGET_MIPS16
+ && TARGET_EXPLICIT_RELOCS
+ && TARGET_CALL_CLOBBERED_GP)
diff --git a/external/subpack/devel/gcc/patches-14.x/230-musl_libssp.patch b/external/subpack/devel/gcc/patches-14.x/230-musl_libssp.patch
new file mode 100644
index 0000000..3ce5e49
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/230-musl_libssp.patch
@@ -0,0 +1,13 @@
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -985,7 +985,9 @@ proper position among the other output f
+ #endif
+
+ #ifndef LINK_SSP_SPEC
+-#ifdef TARGET_LIBC_PROVIDES_SSP
++#if DEFAULT_LIBC == LIBC_MUSL
++#define LINK_SSP_SPEC "-lssp_nonshared"
++#elif defined(TARGET_LIBC_PROVIDES_SSP)
+ #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
+ "|fstack-protector-strong|fstack-protector-explicit:}"
+ #else
diff --git a/external/subpack/devel/gcc/patches-14.x/300-mips_Os_cpu_rtx_cost_model.patch b/external/subpack/devel/gcc/patches-14.x/300-mips_Os_cpu_rtx_cost_model.patch
new file mode 100644
index 0000000..2cbffe4
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/300-mips_Os_cpu_rtx_cost_model.patch
@@ -0,0 +1,21 @@
+commit ecf7671b769fe96f7b5134be442089f8bdba55d2
+Author: Felix Fietkau <nbd@nbd.name>
+Date: Thu Aug 4 20:29:45 2016 +0200
+
+gcc: add a patch to generate better code with Os on mips
+
+Also happens to reduce compressed code size a bit
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+
+--- a/gcc/config/mips/mips.cc
++++ b/gcc/config/mips/mips.cc
+@@ -20453,7 +20453,7 @@ mips_option_override (void)
+ flag_pcc_struct_return = 0;
+
+ /* Decide which rtx_costs structure to use. */
+- if (optimize_size)
++ if (0 && optimize_size)
+ mips_cost = &mips_rtx_cost_optimize_size;
+ else
+ mips_cost = &mips_rtx_cost_data[mips_tune];
diff --git a/external/subpack/devel/gcc/patches-14.x/810-arm-softfloat-libgcc.patch b/external/subpack/devel/gcc/patches-14.x/810-arm-softfloat-libgcc.patch
new file mode 100644
index 0000000..5c9d86a
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/810-arm-softfloat-libgcc.patch
@@ -0,0 +1,33 @@
+commit 8570c4be394cff7282f332f97da2ff569a927ddb
+Author: Imre Kaloz <kaloz@openwrt.org>
+Date: Wed Feb 2 20:06:12 2011 +0000
+
+ fixup arm soft-float symbols
+
+ SVN-Revision: 25325
+
+--- a/libgcc/config/arm/t-linux
++++ b/libgcc/config/arm/t-linux
+@@ -1,6 +1,10 @@
+ LIB1ASMSRC = arm/lib1funcs.S
+ LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \
+- _ctzsi2 _arm_addsubdf3 _arm_addsubsf3
++ _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \
++ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \
++ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \
++ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \
++ _arm_fixsfsi _arm_fixunssfsi
+
+ # Just for these, we omit the frame pointer since it makes such a big
+ # difference.
+--- a/gcc/config/arm/linux-elf.h
++++ b/gcc/config/arm/linux-elf.h
+@@ -58,8 +58,6 @@
+ %{shared:-lc} \
+ %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
+
+-#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
+-
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #define LINUX_TARGET_LINK_SPEC "%{h*} \
diff --git a/external/subpack/devel/gcc/patches-14.x/820-libgcc_pic.patch b/external/subpack/devel/gcc/patches-14.x/820-libgcc_pic.patch
new file mode 100644
index 0000000..3ab73f4
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/820-libgcc_pic.patch
@@ -0,0 +1,44 @@
+commit c96312958c0621e72c9b32da5bc224ffe2161384
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Mon Oct 19 23:26:09 2009 +0000
+
+ gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow)
+
+ SVN-Revision: 18086
+
+--- a/libgcc/Makefile.in
++++ b/libgcc/Makefile.in
+@@ -940,11 +940,12 @@ $(libgcov-driver-objects): %$(objext): $
+
+ # Static libraries.
+ libgcc.a: $(libgcc-objects)
++libgcc_pic.a: $(libgcc-s-objects)
+ libgcov.a: $(libgcov-objects)
+ libunwind.a: $(libunwind-objects)
+ libgcc_eh.a: $(libgcc-eh-objects)
+
+-libgcc.a libgcov.a libunwind.a libgcc_eh.a:
++libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a:
+ -rm -f $@
+
+ objects="$(objects)"; \
+@@ -968,7 +969,7 @@ all: libunwind.a
+ endif
+
+ ifeq ($(enable_shared),yes)
+-all: libgcc_eh.a libgcc_s$(SHLIB_EXT)
++all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT)
+ ifneq ($(LIBUNWIND),)
+ all: libunwind$(SHLIB_EXT)
+ libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT)
+@@ -1174,6 +1175,10 @@ install-shared:
+ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a
+ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a
+
++ $(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/
++ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a
++ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a
++
+ $(subst @multilib_dir@,$(MULTIDIR),$(subst \
+ @shlib_base_name@,libgcc_s,$(subst \
+ @shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL))))
diff --git a/external/subpack/devel/gcc/patches-14.x/840-armv4_pass_fix-v4bx_to_ld.patch b/external/subpack/devel/gcc/patches-14.x/840-armv4_pass_fix-v4bx_to_ld.patch
new file mode 100644
index 0000000..82935f3
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/840-armv4_pass_fix-v4bx_to_ld.patch
@@ -0,0 +1,28 @@
+commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc
+Author: Imre Kaloz <kaloz@openwrt.org>
+Date: Wed Feb 2 19:34:36 2011 +0000
+
+ add armv4 fixup patches
+
+ SVN-Revision: 25322
+
+
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -88,10 +88,15 @@
+ #define MUSL_DYNAMIC_LINKER \
+ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1"
+
++/* For armv4 we pass --fix-v4bx to linker to support EABI */
++#undef TARGET_FIX_V4BX_SPEC
++#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\
++ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
+ use the GNU/Linux version, not the generic BPABI version. */
+ #undef LINK_SPEC
+-#define LINK_SPEC EABI_LINK_SPEC \
++#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC \
+ LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \
+ LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC)
+
diff --git a/external/subpack/devel/gcc/patches-14.x/850-use_shared_libgcc.patch b/external/subpack/devel/gcc/patches-14.x/850-use_shared_libgcc.patch
new file mode 100644
index 0000000..66926ed
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/850-use_shared_libgcc.patch
@@ -0,0 +1,54 @@
+commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun Feb 12 20:25:47 2012 +0000
+
+ gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary
+
+ SVN-Revision: 30486
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -129,10 +129,6 @@
+ "%{Ofast|ffast-math|funsafe-math-optimizations:%{!shared:crtfastmath.o%s}} " \
+ LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)
+
+-/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we
+- do not use -lfloat. */
+-#undef LIBGCC_SPEC
+-
+ /* Clear the instruction cache from `beg' to `end'. This is
+ implemented in lib1funcs.S, so ensure an error if this definition
+ is used. */
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -58,6 +58,10 @@ see the files COPYING3 and COPYING.RUNTI
+ builtin_assert ("system=posix"); \
+ } while (0)
+
++#ifndef LIBGCC_SPEC
++#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}"
++#endif
++
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+ uClibc or Bionic or musl is the default C library and whether
+ -muclibc or -mglibc or -mbionic or -mmusl has been passed to change
+--- a/libgcc/mkmap-symver.awk
++++ b/libgcc/mkmap-symver.awk
+@@ -136,5 +136,5 @@ function output(lib) {
+ else if (inherit[lib])
+ printf("} %s;\n", inherit[lib]);
+ else
+- printf ("\n local:\n\t*;\n};\n");
++ printf ("\n\t*;\n};\n");
+ }
+--- a/gcc/config/rs6000/linux.h
++++ b/gcc/config/rs6000/linux.h
+@@ -70,6 +70,9 @@
+ #undef CPP_OS_DEFAULT_SPEC
+ #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)"
+
++#undef LIBGCC_SPEC
++#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc"
++
+ #undef LINK_SHLIB_SPEC
+ #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}} \
+ %{static-pie:-static -pie --no-dynamic-linker -z text}"
diff --git a/external/subpack/devel/gcc/patches-14.x/851-libgcc_no_compat.patch b/external/subpack/devel/gcc/patches-14.x/851-libgcc_no_compat.patch
new file mode 100644
index 0000000..d710e40
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/851-libgcc_no_compat.patch
@@ -0,0 +1,22 @@
+commit 64661de100da1ec1061ef3e5e400285dce115e6b
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun May 10 13:16:35 2015 +0000
+
+ gcc: add some size optimization patches
+
+ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+
+ SVN-Revision: 45664
+
+--- a/libgcc/config/t-libunwind
++++ b/libgcc/config/t-libunwind
+@@ -2,8 +2,7 @@
+
+ HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER
+
+-LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \
+- $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c
++LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
+ LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
+
+ # Override the default value from t-slibgcc-elf-ver and mention -lunwind
diff --git a/external/subpack/devel/gcc/patches-14.x/870-ppc_no_crtsavres.patch b/external/subpack/devel/gcc/patches-14.x/870-ppc_no_crtsavres.patch
new file mode 100644
index 0000000..0dca688
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/870-ppc_no_crtsavres.patch
@@ -0,0 +1,11 @@
+--- a/gcc/config/rs6000/rs6000-logue.cc
++++ b/gcc/config/rs6000/rs6000-logue.cc
+@@ -344,7 +344,7 @@ rs6000_savres_strategy (rs6000_stack_t *
+ /* Define cutoff for using out-of-line functions to save registers. */
+ if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
+ {
+- if (!optimize_size)
++ if (1)
+ {
+ strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
+ strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
diff --git a/external/subpack/devel/gcc/patches-14.x/881-no_tm_section.patch b/external/subpack/devel/gcc/patches-14.x/881-no_tm_section.patch
new file mode 100644
index 0000000..2029910
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/881-no_tm_section.patch
@@ -0,0 +1,11 @@
+--- a/libgcc/crtstuff.c
++++ b/libgcc/crtstuff.c
+@@ -152,7 +152,7 @@ call_ ## FUNC (void) \
+ #endif
+
+ #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF)
+-# define USE_TM_CLONE_REGISTRY 1
++# define USE_TM_CLONE_REGISTRY 0
+ #elif !defined(USE_TM_CLONE_REGISTRY)
+ # define USE_TM_CLONE_REGISTRY 0
+ #endif
diff --git a/external/subpack/devel/gcc/patches-14.x/900-bad-mips16-crt.patch b/external/subpack/devel/gcc/patches-14.x/900-bad-mips16-crt.patch
new file mode 100644
index 0000000..b355545
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/900-bad-mips16-crt.patch
@@ -0,0 +1,9 @@
+--- a/libgcc/config/mips/t-mips16
++++ b/libgcc/config/mips/t-mips16
+@@ -42,3 +42,6 @@ SYNC_CFLAGS = -mno-mips16
+
+ # Version these symbols if building libgcc.so.
+ SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver
++
++CRTSTUFF_T_CFLAGS += -mno-mips16
++CRTSTUFF_T_CFLAGS_S += -mno-mips16
diff --git a/external/subpack/devel/gcc/patches-14.x/910-mbsd_multi.patch b/external/subpack/devel/gcc/patches-14.x/910-mbsd_multi.patch
new file mode 100644
index 0000000..2a58df3
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/910-mbsd_multi.patch
@@ -0,0 +1,146 @@
+commit 99368862e44740ff4fd33760893f04e14f9dbdf1
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Tue Jul 31 00:52:27 2007 +0000
+
+ Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly
+
+ SVN-Revision: 8256
+
+ This patch brings over a feature from MirBSD:
+ * -fhonour-copts
+ If this option is not given, it's warned (depending
+ on environment variables). This is to catch errors
+ of misbuilt packages which override CFLAGS themselves.
+
+ This patch was authored by Thorsten Glaser <tg at mirbsd.de>
+ with copyright assignment to the FSF in effect.
+
+--- a/gcc/c-family/c-opts.cc
++++ b/gcc/c-family/c-opts.cc
+@@ -108,6 +108,9 @@ static size_t include_cursor;
+ /* Whether any standard preincluded header has been preincluded. */
+ static bool done_preinclude;
+
++/* Check if a port honours COPTS. */
++static int honour_copts = 0;
++
+ static void handle_OPT_d (const char *);
+ static void set_std_cxx98 (int);
+ static void set_std_cxx11 (int);
+@@ -498,6 +501,12 @@ c_common_handle_option (size_t scode, co
+ flag_no_builtin = !value;
+ break;
+
++ case OPT_fhonour_copts:
++ if (c_language == clk_c) {
++ honour_copts++;
++ }
++ break;
++
+ case OPT_fconstant_string_class_:
+ constant_string_class_name = arg;
+ break;
+@@ -1291,6 +1300,47 @@ c_common_init (void)
+ return false;
+ }
+
++ if (c_language == clk_c) {
++ char *ev = getenv ("GCC_HONOUR_COPTS");
++ int evv;
++ if (ev == NULL)
++ evv = -1;
++ else if ((*ev == '0') || (*ev == '\0'))
++ evv = 0;
++ else if (*ev == '1')
++ evv = 1;
++ else if (*ev == '2')
++ evv = 2;
++ else if (*ev == 's')
++ evv = -1;
++ else {
++ warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1");
++ evv = 1; /* maybe depend this on something like MIRBSD_NATIVE? */
++ }
++ if (evv == 1) {
++ if (honour_copts == 0) {
++ error ("someone does not honour COPTS at all in lenient mode");
++ return false;
++ } else if (honour_copts != 1) {
++ warning (0, "someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ }
++ } else if (evv == 2) {
++ if (honour_copts == 0) {
++ error ("someone does not honour COPTS at all in strict mode");
++ return false;
++ } else if (honour_copts != 1) {
++ error ("someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ return false;
++ }
++ } else if (evv == 0) {
++ if (honour_copts != 1)
++ inform (UNKNOWN_LOCATION, "someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ }
++ }
++
+ return true;
+ }
+
+--- a/gcc/c-family/c.opt
++++ b/gcc/c-family/c.opt
+@@ -1910,6 +1910,9 @@ C++ ObjC++ Optimization Alias(fexception
+ fhonor-std
+ C++ ObjC++ WarnRemoved
+
++fhonour-copts
++C ObjC C++ ObjC++ RejectNegative
++
+ fhosted
+ C ObjC
+ Assume normal C execution environment.
+--- a/gcc/common.opt
++++ b/gcc/common.opt
+@@ -1881,6 +1881,9 @@ Enum(hardcfr_check_noreturn_calls) Strin
+ EnumValue
+ Enum(hardcfr_check_noreturn_calls) String(always) Value(HCFRNR_ALWAYS)
+
++fhonour-copts
++Common RejectNegative
++
+ ; Nonzero means ignore `#ident' directives. 0 means handle them.
+ ; Generate position-independent code for executables if possible
+ ; On SVR4 targets, it also controls whether or not to emit a
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -10597,6 +10597,17 @@ This option is only supported for C and
+
+ This warning is upgraded to an error by @option{-pedantic-errors}.
+
++@item -fhonour-copts
++@opindex fhonour-copts
++If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not
++given at least once, and warn if it is given more than once.
++If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not
++given exactly once.
++If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option
++is not given exactly once.
++The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}.
++This flag and environment variable only affect the C language.
++
+ @opindex Wstack-protector
+ @opindex Wno-stack-protector
+ @item -Wstack-protector
+--- a/gcc/opts.cc
++++ b/gcc/opts.cc
+@@ -2833,6 +2833,9 @@ common_handle_option (struct gcc_options
+ add_comma_separated_to_vector (&opts->x_flag_ignored_attributes, arg);
+ break;
+
++ case OPT_fhonour_copts:
++ break;
++
+ case OPT_Werror:
+ dc->set_warning_as_error_requested (value);
+ break;
diff --git a/external/subpack/devel/gcc/patches-14.x/920-specs_nonfatal_getenv.patch b/external/subpack/devel/gcc/patches-14.x/920-specs_nonfatal_getenv.patch
new file mode 100644
index 0000000..121b684
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/920-specs_nonfatal_getenv.patch
@@ -0,0 +1,22 @@
+Author: Jo-Philipp Wich <jow@openwrt.org>
+Date: Sat Apr 21 03:02:39 2012 +0000
+
+ gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset
+
+ SVN-Revision: 31390
+
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -10319,8 +10319,10 @@ getenv_spec_function (int argc, const ch
+ }
+
+ if (!value)
+- fatal_error (input_location,
+- "environment variable %qs not defined", varname);
++ {
++ warning (input_location, "environment variable %qs not defined", varname);
++ value = "";
++ }
+
+ /* We have to escape every character of the environment variable so
+ they are not interpreted as active spec characters. A
diff --git a/external/subpack/devel/gcc/patches-14.x/960-gotools-fix-compilation-when-making-cross-compiler.patch b/external/subpack/devel/gcc/patches-14.x/960-gotools-fix-compilation-when-making-cross-compiler.patch
new file mode 100644
index 0000000..b1d7576
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/960-gotools-fix-compilation-when-making-cross-compiler.patch
@@ -0,0 +1,67 @@
+From dda6b050cd74a352670787a294596a9c56c21327 Mon Sep 17 00:00:00 2001
+From: Yousong Zhou <yszhou4tech@gmail.com>
+Date: Fri, 4 May 2018 18:20:53 +0800
+Subject: [PATCH] gotools: fix compilation when making cross compiler
+
+libgo is "the runtime support library for the Go programming language.
+This library is intended for use with the Go frontend."
+
+gccgo will link target files with libgo.so which depends on libgcc_s.so.1, but
+the linker will complain that it cannot find it. That's because shared libgcc
+is not present in the install directory yet. libgo.so was made without problem
+because gcc will emit -lgcc_s when compiled with -shared option. When gotools
+were being made, it was supplied with -static-libgcc thus no link option was
+provided. Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec
+for linking with libgo.so
+
+- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation
+- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html
+
+When 3-pass GCC compilation is used, shared libgcc runtime libraries will be
+available after gcc pass2 completed and will meet the gotools link requirement
+at gcc pass3
+---
+ gotools/Makefile.am | 4 +++-
+ gotools/Makefile.in | 4 +++-
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/gotools/Makefile.am
++++ b/gotools/Makefile.am
+@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+
+ libgodir = ../$(target_noncanonical)/libgo
++libgccdir = ../$(target_noncanonical)/libgcc
+ LIBGODEP = $(libgodir)/libgo.la
+
+ LIBGOTOOL = $(libgodir)/libgotool.a
+@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+
+ AM_GOCFLAGS = -I $(libgodir)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \
++ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s
+ GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+
+ libgosrcdir = $(srcdir)/../libgo/go
+--- a/gotools/Makefile.in
++++ b/gotools/Makefile.in
+@@ -337,6 +337,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd
+ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+ libgodir = ../$(target_noncanonical)/libgo
++libgccdir = ../$(target_noncanonical)/libgcc
+ LIBGODEP = $(libgodir)/libgo.la
+ LIBGOTOOL = $(libgodir)/libgotool.a
+ @NATIVE_FALSE@GOCOMPILER = $(GOC)
+@@ -346,7 +347,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a
+ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+ AM_GOCFLAGS = -I $(libgodir)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \
++ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s
+ GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+ libgosrcdir = $(srcdir)/../libgo/go
+ cmdsrcdir = $(libgosrcdir)/cmd
diff --git a/external/subpack/devel/gcc/patches-14.x/970-macos_arm64-building-fix.patch b/external/subpack/devel/gcc/patches-14.x/970-macos_arm64-building-fix.patch
new file mode 100644
index 0000000..da878df
--- /dev/null
+++ b/external/subpack/devel/gcc/patches-14.x/970-macos_arm64-building-fix.patch
@@ -0,0 +1,45 @@
+commit 9c6e71079b46ad5433165feaa2001450f2017b56
+Author: Przemysław Buczkowski <prem@prem.moe>
+Date: Mon Aug 16 13:16:21 2021 +0100
+
+ GCC: Patch for Apple Silicon compatibility
+
+ This patch fixes a linker error occuring when compiling
+ the cross-compiler on macOS and ARM64 architecture.
+
+ Adapted from:
+ https://github.com/richfelker/musl-cross-make/issues/116#issuecomment-823612404
+
+ Change-Id: Ia3ee98a163bbb62689f42e2da83a5ef36beb0913
+ Reviewed-on: https://review.haiku-os.org/c/buildtools/+/4329
+ Reviewed-by: John Scipione <jscipione@gmail.com>
+ Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
+
+--- a/gcc/config/aarch64/aarch64.h
++++ b/gcc/config/aarch64/aarch64.h
+@@ -1410,7 +1410,7 @@ extern enum aarch64_code_model aarch64_c
+
+ /* Extra specs when building a native AArch64-hosted compiler.
+ Option rewriting rules based on host system. */
+-#if defined(__aarch64__)
++#if defined(__aarch64__) && ! defined(__APPLE__)
+ extern const char *host_detect_local_cpu (int argc, const char **argv);
+ #define HAVE_LOCAL_CPU_DETECT
+ # define EXTRA_SPEC_FUNCTIONS \
+--- a/gcc/config/host-darwin.cc
++++ b/gcc/config/host-darwin.cc
+@@ -23,6 +23,8 @@
+ #include "options.h"
+ #include "diagnostic-core.h"
+ #include "config/host-darwin.h"
++#include "hosthooks.h"
++#include "hosthooks-def.h"
+ #include <errno.h>
+
+ /* For Darwin (macOS only) platforms, without ASLR (PIE) enabled on the
+@@ -181,3 +183,5 @@ darwin_gt_pch_use_address (void *&addr,
+
+ return 1;
+ }
++
++const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;