ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/linux/arch/arm/mach-mmp/irqs.h b/marvell/linux/arch/arm/mach-mmp/irqs.h
new file mode 100644
index 0000000..ccd0ec0
--- /dev/null
+++ b/marvell/linux/arch/arm/mach-mmp/irqs.h
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+#include <linux/irqchip/mmp.h>
+
+#ifndef IRQ_ASR1901_START
+#define IRQ_ASR1901_START (32)
+#endif
+#define IRQ_ASR1901_PMIC (IRQ_ASR1901_START + 43)
+#define IRQ_ASR1901_RTC_ALARM_SEC (IRQ_ASR1901_START + 46)
+#define IRQ_ASR1901_RTC_ALARM_NSEC (IRQ_ASR1901_START + 6)
+#define IRQ_ASR1901_KEYPAD (IRQ_ASR1901_START + 42)
+#define IRQ_ASR1901_AP0_TIMER1 (IRQ_ASR1901_START + 7)
+#define IRQ_ASR1901_AP0_TIMER2 (IRQ_ASR1901_START + 8)
+#define IRQ_ASR1901_AP0_TIMER3 (IRQ_ASR1901_START + 9)
+#define IRQ_ASR1901_AP1_TIMER1 (IRQ_ASR1901_START + 10)
+#define IRQ_ASR1901_AP1_TIMER2 (IRQ_ASR1901_START + 11)
+#define IRQ_ASR1901_AP1_TIMER3 (IRQ_ASR1901_START + 12)
+#define IRQ_ASR1901_AP2_TIMER1 (IRQ_ASR1901_START + 13)
+#define IRQ_ASR1901_AP2_TIMER2 (IRQ_ASR1901_START + 14)
+#define IRQ_ASR1901_AP2_TIMER3 (IRQ_ASR1901_START + 15)
+#define IRQ_ASR1901_MMC1 (IRQ_ASR1901_START + 83)
+#define IRQ_ASR1901_MMC2 (IRQ_ASR1901_START + 84)
+#define IRQ_ASR1901_MMC3 (IRQ_ASR1901_START + 85)
+#define IRQ_ASR1901_USB0 (IRQ_ASR1901_START + 89)
+#define IRQ_ASR1901_USB1 (IRQ_ASR1901_START + 90)
+
+#define IRQ_ASR1901_USB0_WAKEUP (IRQ_ASR1901_START + 106)
+#define IRQ_ASR1901_USB1_WAKEUP (IRQ_ASR1901_START + 107)
+
+#define IRQ_ASR1901_AP_GMAC (IRQ_ASR1901_START + 55)
+
+#define IRQ_ASR1901_DMA_INT_NONSEC (IRQ_ASR1901_START + 56)
+#define IRQ_ASR1901_DMA_INT_SEC (IRQ_ASR1901_START + 57)
+
+#define IRQ_ASR1901_GPIO_AP_NONSEC (IRQ_ASR1901_START + 37)
+#define IRQ_ASR1901_GPIO_AP_SEC (IRQ_ASR1901_START + 38)
+
+#define IRQ_ASR1901_AP_AUDIO (IRQ_ASR1901_START + 81)
+
+#define IRQ_ASR1901_PCIE_PORT0 (IRQ_ASR1901_START + 74)
+#define IRQ_ASR1901_PCIE_PORT1 (IRQ_ASR1901_START +116)
+
+/*
+ * Partial interrupt for PXA1826.
+ * The IRQ_PXA1822_START should not be 0 because irq domain is used
+ * which ignores the zero virq number, the virq= IRQ_PXA1822_START + hwirq
+ * dts file keep to use hwirq number in the mapping.
+ */
+
+/* FIXME: The following Macro will be refined by DT in future
+ * when Most of the Devices is configured in DT way.
+ * IRQ offset is defined as 0 in irq-mmp.c for kernel 5.4
+ */
+#define IRQ_ASR18XX_START 0
+
+#define IRQ_ASR18XX_PMIC (IRQ_ASR18XX_START + 4)
+#define IRQ_ASR18XX_RTC_ALARM (IRQ_ASR18XX_START + 6)
+#define IRQ_ASR18XX_KEYPAD (IRQ_ASR18XX_START + 9)
+#define IRQ_ASR18XX_AP_GMAC (IRQ_ASR18XX_START + 11)
+#define IRQ_ASR18XX_AP_TIMER1 (IRQ_ASR18XX_START + 13)
+#define IRQ_ASR18XX_AP_TIMER2_3 (IRQ_ASR18XX_START + 14)
+#define IRQ_ASR18XX_AP2_TIMER1 (IRQ_ASR18XX_START + 29)
+#define IRQ_ASR18XX_AP2_TIMER2_3 (IRQ_ASR18XX_START + 30)
+#define IRQ_ASR18XX_MMC (IRQ_ASR18XX_START + 39)
+#define IRQ_ASR18XX_USB1 (IRQ_ASR18XX_START + 44)
+#define IRQ_ASR18XX_HIFI_DMA (IRQ_ASR18XX_START + 46)
+#define IRQ_ASR18XX_DMA_INT0 (IRQ_ASR18XX_START + 47)
+#define IRQ_ASR18XX_GPIO_AP (IRQ_ASR18XX_START + 49)
+#define IRQ_ASR1826S_USB_WAKEUP (IRQ_ASR18XX_START + 53)
+
+/*
+ * Interrupt numbers for PXA168
+ */
+#define IRQ_PXA168_NONE (-1)
+#define IRQ_PXA168_SSP4 0
+#define IRQ_PXA168_SSP3 1
+#define IRQ_PXA168_SSP2 2
+#define IRQ_PXA168_SSP1 3
+#define IRQ_PXA168_PMIC_INT 4
+#define IRQ_PXA168_RTC_INT 5
+#define IRQ_PXA168_RTC_ALARM 6
+#define IRQ_PXA168_TWSI0 7
+#define IRQ_PXA168_GPU 8
+#define IRQ_PXA168_KEYPAD 9
+#define IRQ_PXA168_ONEWIRE 12
+#define IRQ_PXA168_TIMER1 13
+#define IRQ_PXA168_TIMER2 14
+#define IRQ_PXA168_TIMER3 15
+#define IRQ_PXA168_CMU 16
+#define IRQ_PXA168_SSP5 17
+#define IRQ_PXA168_MSP_WAKEUP 19
+#define IRQ_PXA168_CF_WAKEUP 20
+#define IRQ_PXA168_XD_WAKEUP 21
+#define IRQ_PXA168_MFU 22
+#define IRQ_PXA168_MSP 23
+#define IRQ_PXA168_CF 24
+#define IRQ_PXA168_XD 25
+#define IRQ_PXA168_DDR_INT 26
+#define IRQ_PXA168_UART1 27
+#define IRQ_PXA168_UART2 28
+#define IRQ_PXA168_UART3 29
+#define IRQ_PXA168_WDT 35
+#define IRQ_PXA168_MAIN_PMU 36
+#define IRQ_PXA168_FRQ_CHANGE 38
+#define IRQ_PXA168_SDH1 39
+#define IRQ_PXA168_SDH2 40
+#define IRQ_PXA168_LCD 41
+#define IRQ_PXA168_CI 42
+#define IRQ_PXA168_USB1 44
+#define IRQ_PXA168_NAND 45
+#define IRQ_PXA168_HIFI_DMA 46
+#define IRQ_PXA168_DMA_INT0 47
+#define IRQ_PXA168_DMA_INT1 48
+#define IRQ_PXA168_GPIOX 49
+#define IRQ_PXA168_USB2 51
+#define IRQ_PXA168_AC97 57
+#define IRQ_PXA168_TWSI1 58
+#define IRQ_PXA168_AP_PMU 60
+#define IRQ_PXA168_SM_INT 63
+
+/*
+ * Interrupt numbers for PXA910
+ */
+#define IRQ_PXA910_NONE (-1)
+#define IRQ_PXA910_AIRQ 0
+#define IRQ_PXA910_SSP3 1
+#define IRQ_PXA910_SSP2 2
+#define IRQ_PXA910_SSP1 3
+#define IRQ_PXA910_PMIC_INT 4
+#define IRQ_PXA910_RTC_INT 5
+#define IRQ_PXA910_RTC_ALARM 6
+#define IRQ_PXA910_TWSI0 7
+#define IRQ_PXA910_GPU 8
+#define IRQ_PXA910_KEYPAD 9
+#define IRQ_PXA910_ROTARY 10
+#define IRQ_PXA910_TRACKBALL 11
+#define IRQ_PXA910_ONEWIRE 12
+#define IRQ_PXA910_AP1_TIMER1 13
+#define IRQ_PXA910_AP1_TIMER2 14
+#define IRQ_PXA910_AP1_TIMER3 15
+#define IRQ_PXA910_IPC_AP0 16
+#define IRQ_PXA910_IPC_AP1 17
+#define IRQ_PXA910_IPC_AP2 18
+#define IRQ_PXA910_IPC_AP3 19
+#define IRQ_PXA910_IPC_AP4 20
+#define IRQ_PXA910_IPC_CP0 21
+#define IRQ_PXA910_IPC_CP1 22
+#define IRQ_PXA910_IPC_CP2 23
+#define IRQ_PXA910_IPC_CP3 24
+#define IRQ_PXA910_IPC_CP4 25
+#define IRQ_PXA910_L2_DDR 26
+#define IRQ_PXA910_UART2 27
+#define IRQ_PXA910_UART3 28
+#define IRQ_PXA910_AP2_TIMER1 29
+#define IRQ_PXA910_AP2_TIMER2 30
+#define IRQ_PXA910_CP2_TIMER1 31
+#define IRQ_PXA910_CP2_TIMER2 32
+#define IRQ_PXA910_CP2_TIMER3 33
+#define IRQ_PXA910_GSSP 34
+#define IRQ_PXA910_CP2_WDT 35
+#define IRQ_PXA910_MAIN_PMU 36
+#define IRQ_PXA910_CP_FREQ_CHG 37
+#define IRQ_PXA910_AP_FREQ_CHG 38
+#define IRQ_PXA910_MMC 39
+#define IRQ_PXA910_AEU 40
+#define IRQ_PXA910_LCD 41
+#define IRQ_PXA910_CCIC 42
+#define IRQ_PXA910_IRE 43
+#define IRQ_PXA910_USB1 44
+#define IRQ_PXA910_NAND 45
+#define IRQ_PXA910_HIFI_DMA 46
+#define IRQ_PXA910_DMA_INT0 47
+#define IRQ_PXA910_DMA_INT1 48
+#define IRQ_PXA910_AP_GPIO 49
+#define IRQ_PXA910_AP2_TIMER3 50
+#define IRQ_PXA910_USB2 51
+#define IRQ_PXA910_TWSI1 54
+#define IRQ_PXA910_CP_GPIO 55
+#define IRQ_PXA910_UART1 59 /* Slow UART */
+#define IRQ_PXA910_AP_PMU 60
+#define IRQ_PXA910_SM_INT 63 /* from PinMux */
+
+/*
+ * Interrupt numbers for MMP2
+ */
+#define IRQ_MMP2_NONE (-1)
+#define IRQ_MMP2_SSP1 0
+#define IRQ_MMP2_SSP2 1
+#define IRQ_MMP2_SSPA1 2
+#define IRQ_MMP2_SSPA2 3
+#define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */
+#define IRQ_MMP2_RTC_MUX 5
+#define IRQ_MMP2_TWSI1 7
+#define IRQ_MMP2_GPU 8
+#define IRQ_MMP2_KEYPAD_MUX 9
+#define IRQ_MMP2_ROTARY 10
+#define IRQ_MMP2_TRACKBALL 11
+#define IRQ_MMP2_ONEWIRE 12
+#define IRQ_MMP2_TIMER1 13
+#define IRQ_MMP2_TIMER2 14
+#define IRQ_MMP2_TIMER3 15
+#define IRQ_MMP2_RIPC 16
+#define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */
+#define IRQ_MMP2_HDMI 19
+#define IRQ_MMP2_SSP3 20
+#define IRQ_MMP2_SSP4 21
+#define IRQ_MMP2_USB_HS1 22
+#define IRQ_MMP2_USB_HS2 23
+#define IRQ_MMP2_UART3 24
+#define IRQ_MMP2_UART1 27
+#define IRQ_MMP2_UART2 28
+#define IRQ_MMP2_MIPI_DSI 29
+#define IRQ_MMP2_CI2 30
+#define IRQ_MMP2_PMU_TIMER1 31
+#define IRQ_MMP2_PMU_TIMER2 32
+#define IRQ_MMP2_PMU_TIMER3 33
+#define IRQ_MMP2_USB_FS 34
+#define IRQ_MMP2_MISC_MUX 35
+#define IRQ_MMP2_WDT1 36
+#define IRQ_MMP2_NAND_DMA 37
+#define IRQ_MMP2_USIM 38
+#define IRQ_MMP2_MMC 39
+#define IRQ_MMP2_WTM 40
+#define IRQ_MMP2_LCD 41
+#define IRQ_MMP2_CI 42
+#define IRQ_MMP2_IRE 43
+#define IRQ_MMP2_USB_OTG 44
+#define IRQ_MMP2_NAND 45
+#define IRQ_MMP2_UART4 46
+#define IRQ_MMP2_DMA_FIQ 47
+#define IRQ_MMP2_DMA_RIQ 48
+#define IRQ_MMP2_GPIO 49
+#define IRQ_MMP2_MIPI_HSI1_MUX 51
+#define IRQ_MMP2_MMC2 52
+#define IRQ_MMP2_MMC3 53
+#define IRQ_MMP2_MMC4 54
+#define IRQ_MMP2_MIPI_HSI0_MUX 55
+#define IRQ_MMP2_MSP 58
+#define IRQ_MMP2_MIPI_SLIM_DMA 59
+#define IRQ_MMP2_PJ4_FREQ_CHG 60
+#define IRQ_MMP2_MIPI_SLIM 62
+#define IRQ_MMP2_SM 63
+
+#define IRQ_MMP2_MUX_BASE 64
+
+/* secondary interrupt of INT #4 */
+#define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE)
+#define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0)
+#define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1)
+
+/* secondary interrupt of INT #5 */
+#define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2)
+#define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0)
+#define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1)
+
+/* secondary interrupt of INT #9 */
+#define IRQ_MMP2_KEYPAD_BASE (IRQ_MMP2_RTC_BASE + 2)
+#define IRQ_MMP2_KPC (IRQ_MMP2_KEYPAD_BASE + 0)
+#define IRQ_MMP2_ROTORY (IRQ_MMP2_KEYPAD_BASE + 1)
+#define IRQ_MMP2_TBALL (IRQ_MMP2_KEYPAD_BASE + 2)
+
+/* secondary interrupt of INT #17 */
+#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_KEYPAD_BASE + 3)
+#define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0)
+#define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1)
+#define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2)
+#define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3)
+#define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4)
+
+/* secondary interrupt of INT #35 */
+#define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5)
+#define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0)
+#define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1)
+#define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2)
+#define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3)
+#define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4)
+#define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5)
+#define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6)
+#define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7)
+#define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9)
+#define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10)
+#define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11)
+#define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12)
+#define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13)
+#define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14)
+
+/* secondary interrupt of INT #51 */
+#define IRQ_MMP2_MIPI_HSI1_BASE (IRQ_MMP2_MISC_BASE + 15)
+#define IRQ_MMP2_HSI1_CAWAKE (IRQ_MMP2_MIPI_HSI1_BASE + 0)
+#define IRQ_MMP2_MIPI_HSI_INT1 (IRQ_MMP2_MIPI_HSI1_BASE + 1)
+
+/* secondary interrupt of INT #55 */
+#define IRQ_MMP2_MIPI_HSI0_BASE (IRQ_MMP2_MIPI_HSI1_BASE + 2)
+#define IRQ_MMP2_HSI0_CAWAKE (IRQ_MMP2_MIPI_HSI0_BASE + 0)
+#define IRQ_MMP2_MIPI_HSI_INT0 (IRQ_MMP2_MIPI_HSI0_BASE + 1)
+
+#define IRQ_MMP2_MUX_END (IRQ_MMP2_MIPI_HSI0_BASE + 2)
+
+#define IRQ_GPIO_START 128
+#define MMP_NR_BUILTIN_GPIO 192
+#define MMP_GPIO_TO_IRQ(gpio) (IRQ_GPIO_START + (gpio))
+
+#define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO)
+#define MMP_NR_IRQS IRQ_BOARD_START
+
+#endif /* __ASM_MACH_IRQS_H */