ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/linux/arch/arm/mach-npcm/Kconfig b/marvell/linux/arch/arm/mach-npcm/Kconfig
new file mode 100644
index 0000000..7f7002d
--- /dev/null
+++ b/marvell/linux/arch/arm/mach-npcm/Kconfig
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menuconfig ARCH_NPCM
+ bool "Nuvoton NPCM Architecture"
+ depends on ARCH_MULTI_V7
+ select PINCTRL
+
+if ARCH_NPCM
+
+config ARCH_NPCM7XX
+ bool "Support for NPCM7xx BMC (Poleg)"
+ depends on ARCH_MULTI_V7
+ select PINCTRL_NPCM7XX
+ select NPCM7XX_TIMER
+ select GPIOLIB
+ select CACHE_L2X0
+ select ARM_GIC
+ select HAVE_ARM_TWD if SMP
+ select HAVE_ARM_SCU if SMP
+ select ARM_ERRATA_764369 if SMP
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_794072
+ select PL310_ERRATA_588369
+ select PL310_ERRATA_727915
+ select MFD_SYSCON
+ help
+ General support for NPCM7xx BMC (Poleg).
+
+ Nuvoton NPCM7xx BMC based on the Cortex A9.
+
+endif
diff --git a/marvell/linux/arch/arm/mach-npcm/Makefile b/marvell/linux/arch/arm/mach-npcm/Makefile
new file mode 100644
index 0000000..1bc3a70
--- /dev/null
+++ b/marvell/linux/arch/arm/mach-npcm/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+AFLAGS_headsmp.o += -march=armv7-a
+
+obj-$(CONFIG_ARCH_NPCM7XX) += npcm7xx.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/marvell/linux/arch/arm/mach-npcm/headsmp.S b/marvell/linux/arch/arm/mach-npcm/headsmp.S
new file mode 100644
index 0000000..c083fe0
--- /dev/null
+++ b/marvell/linux/arch/arm/mach-npcm/headsmp.S
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright 2018 Google, Inc.
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+
+/*
+ * The boot ROM does not start secondary CPUs in SVC mode, so we need to do that
+ * here.
+ */
+ENTRY(npcm7xx_secondary_startup)
+ safe_svcmode_maskall r0
+
+ b secondary_startup
+ENDPROC(npcm7xx_secondary_startup)
diff --git a/marvell/linux/arch/arm/mach-npcm/npcm7xx.c b/marvell/linux/arch/arm/mach-npcm/npcm7xx.c
new file mode 100644
index 0000000..c5f77d8
--- /dev/null
+++ b/marvell/linux/arch/arm/mach-npcm/npcm7xx.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright 2018 Google, Inc.
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+static const char *const npcm7xx_dt_match[] = {
+ "nuvoton,npcm750",
+ NULL
+};
+
+DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
+ .atag_offset = 0x100,
+ .dt_compat = npcm7xx_dt_match,
+ .l2c_aux_val = 0x0,
+ .l2c_aux_mask = ~0x0,
+MACHINE_END
diff --git a/marvell/linux/arch/arm/mach-npcm/platsmp.c b/marvell/linux/arch/arm/mach-npcm/platsmp.c
new file mode 100644
index 0000000..21633c7
--- /dev/null
+++ b/marvell/linux/arch/arm/mach-npcm/platsmp.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright 2018 Google, Inc.
+
+#define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/smp.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#define NPCM7XX_SCRPAD_REG 0x13c
+
+extern void npcm7xx_secondary_startup(void);
+
+static int npcm7xx_smp_boot_secondary(unsigned int cpu,
+ struct task_struct *idle)
+{
+ struct device_node *gcr_np;
+ void __iomem *gcr_base;
+ int ret = 0;
+
+ gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
+ if (!gcr_np) {
+ pr_err("no gcr device node\n");
+ ret = -ENODEV;
+ goto out;
+ }
+ gcr_base = of_iomap(gcr_np, 0);
+ if (!gcr_base) {
+ pr_err("could not iomap gcr");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ /* give boot ROM kernel start address. */
+ iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
+ NPCM7XX_SCRPAD_REG);
+ /* make sure the previous write is seen by all observers. */
+ dsb_sev();
+
+ iounmap(gcr_base);
+out:
+ return ret;
+}
+
+static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
+{
+ struct device_node *scu_np;
+ void __iomem *scu_base;
+
+ scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+ if (!scu_np) {
+ pr_err("no scu device node\n");
+ return;
+ }
+ scu_base = of_iomap(scu_np, 0);
+ if (!scu_base) {
+ pr_err("could not iomap scu");
+ return;
+ }
+
+ scu_enable(scu_base);
+
+ iounmap(scu_base);
+}
+
+static struct smp_operations npcm7xx_smp_ops __initdata = {
+ .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
+ .smp_boot_secondary = npcm7xx_smp_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm750-smp", &npcm7xx_smp_ops);