ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/linux/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h b/marvell/linux/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
new file mode 100644
index 0000000..63b4c88
--- /dev/null
+++ b/marvell/linux/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Ilya A. Volynets-Evenbakh
+ * Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
+
+
+/*
+ * R5000 has an interesting "restriction": ll(d)/sc(d)
+ * instructions to XKPHYS region simply do uncached bus
+ * requests. This breaks all the atomic bitops functions.
+ * so, for 64bit IP32 kernel we just don't use ll/sc.
+ * This does not affect luserland.
+ */
+#if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT)
+#define cpu_has_llsc 0
+#else
+#define cpu_has_llsc 1
+#endif
+
+/* Settings which are common for all ip32 CPUs */
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_32fpr 1
+#define cpu_has_counter 1
+#define cpu_has_mips16 0
+#define cpu_has_mips16e2 0
+#define cpu_has_vce 0
+#define cpu_has_cache_cdex_s 0
+#define cpu_has_mcheck 0
+#define cpu_has_ejtag 0
+#define cpu_has_vtag_icache 0
+#define cpu_has_ic_fills_f_dc 0
+#define cpu_has_dsp 0
+#define cpu_has_dsp2 0
+#define cpu_has_4k_cache 1
+#define cpu_has_mipsmt 0
+#define cpu_has_userlocal 0
+
+
+#define cpu_has_mips32r1 0
+#define cpu_has_mips32r2 0
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/marvell/linux/arch/mips/include/asm/mach-ip32/kmalloc.h b/marvell/linux/arch/mips/include/asm/mach-ip32/kmalloc.h
new file mode 100644
index 0000000..07a0146
--- /dev/null
+++ b/marvell/linux/arch/mips/include/asm/mach-ip32/kmalloc.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_IP32_KMALLOC_H
+#define __ASM_MACH_IP32_KMALLOC_H
+
+
+#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000)
+#define ARCH_DMA_MINALIGN 32
+#else
+#define ARCH_DMA_MINALIGN 128
+#endif
+
+#endif /* __ASM_MACH_IP32_KMALLOC_H */
diff --git a/marvell/linux/arch/mips/include/asm/mach-ip32/mangle-port.h b/marvell/linux/arch/mips/include/asm/mach-ip32/mangle-port.h
new file mode 100644
index 0000000..f1d0f17
--- /dev/null
+++ b/marvell/linux/arch/mips/include/asm/mach-ip32/mangle-port.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ladislav Michl
+ * Copyright (C) 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP32_MANGLE_PORT_H
+#define __ASM_MACH_IP32_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port) ((port) ^ 3)
+#define __swizzle_addr_w(port) ((port) ^ 2)
+#define __swizzle_addr_l(port) (port)
+#define __swizzle_addr_q(port) (port)
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) (x)
+# define __mem_ioswabw(a, x) cpu_to_le16(x)
+# define ioswabl(a, x) (x)
+# define __mem_ioswabl(a, x) cpu_to_le32(x)
+# define ioswabq(a, x) (x)
+# define __mem_ioswabq(a, x) cpu_to_le32(x)
+
+#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
diff --git a/marvell/linux/arch/mips/include/asm/mach-ip32/war.h b/marvell/linux/arch/mips/include/asm/mach-ip32/war.h
new file mode 100644
index 0000000..e77b9d1
--- /dev/null
+++ b/marvell/linux/arch/mips/include/asm/mach-ip32/war.h
@@ -0,0 +1,23 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_IP32_WAR_H
+#define __ASM_MIPS_MACH_IP32_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 1
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_IP32_WAR_H */