ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/linux/arch/mips/jz4740/Kconfig b/marvell/linux/arch/mips/jz4740/Kconfig
new file mode 100644
index 0000000..4dd0c44
--- /dev/null
+++ b/marvell/linux/arch/mips/jz4740/Kconfig
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0
+choice
+ prompt "Machine type"
+ depends on MACH_INGENIC
+ default JZ4740_QI_LB60
+
+config JZ4740_QI_LB60
+ bool "Qi Hardware Ben NanoNote"
+ select MACH_JZ4740
+
+config JZ4770_GCW0
+ bool "Game Consoles Worldwide GCW Zero"
+ select MACH_JZ4770
+
+config JZ4780_CI20
+ bool "MIPS Creator CI20"
+ select MACH_JZ4780
+
+endchoice
+
+config MACH_JZ4740
+ bool
+ select SYS_HAS_CPU_MIPS32_R1
+
+config MACH_JZ4770
+ bool
+ select MIPS_CPU_SCACHE
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_SUPPORTS_HIGHMEM
+
+config MACH_JZ4780
+ bool
+ select MIPS_CPU_SCACHE
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_SUPPORTS_HIGHMEM
diff --git a/marvell/linux/arch/mips/jz4740/Makefile b/marvell/linux/arch/mips/jz4740/Makefile
new file mode 100644
index 0000000..6de14c0
--- /dev/null
+++ b/marvell/linux/arch/mips/jz4740/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the Ingenic JZ4740.
+#
+
+# Object file lists.
+
+obj-y += prom.o time.o reset.o setup.o timer.o
+
+CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
+
+# PM support
+
+obj-$(CONFIG_PM) += pm.o
diff --git a/marvell/linux/arch/mips/jz4740/Platform b/marvell/linux/arch/mips/jz4740/Platform
new file mode 100644
index 0000000..a2a5a85
--- /dev/null
+++ b/marvell/linux/arch/mips/jz4740/Platform
@@ -0,0 +1,4 @@
+platform-$(CONFIG_MACH_INGENIC) += jz4740/
+cflags-$(CONFIG_MACH_INGENIC) += -I$(srctree)/arch/mips/include/asm/mach-jz4740
+load-$(CONFIG_MACH_INGENIC) += 0xffffffff80010000
+zload-$(CONFIG_MACH_INGENIC) += 0xffffffff81000000
diff --git a/marvell/linux/arch/mips/jz4740/pm.c b/marvell/linux/arch/mips/jz4740/pm.c
new file mode 100644
index 0000000..f9b551f
--- /dev/null
+++ b/marvell/linux/arch/mips/jz4740/pm.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ * JZ4740 SoC power management support
+ */
+
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/delay.h>
+#include <linux/suspend.h>
+
+static int jz4740_pm_enter(suspend_state_t state)
+{
+ __asm__(".set\tmips3\n\t"
+ "wait\n\t"
+ ".set\tmips0");
+
+
+
+ return 0;
+}
+
+static const struct platform_suspend_ops jz4740_pm_ops = {
+ .valid = suspend_valid_only_mem,
+ .enter = jz4740_pm_enter,
+};
+
+static int __init jz4740_pm_init(void)
+{
+ suspend_set_ops(&jz4740_pm_ops);
+ return 0;
+
+}
+late_initcall(jz4740_pm_init);
diff --git a/marvell/linux/arch/mips/jz4740/prom.c b/marvell/linux/arch/mips/jz4740/prom.c
new file mode 100644
index 0000000..ff4555c
--- /dev/null
+++ b/marvell/linux/arch/mips/jz4740/prom.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ * JZ4740 SoC prom code
+ */
+
+#include <linux/init.h>
+
+#include <asm/bootinfo.h>
+#include <asm/fw/fw.h>
+
+void __init prom_init(void)
+{
+ fw_init_cmdline();
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
diff --git a/marvell/linux/arch/mips/jz4740/reset.c b/marvell/linux/arch/mips/jz4740/reset.c
new file mode 100644
index 0000000..1f9f02e
--- /dev/null
+++ b/marvell/linux/arch/mips/jz4740/reset.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ */
+
+#include <asm/reboot.h>
+
+#include "reset.h"
+
+static void jz4740_halt(void)
+{
+ while (1) {
+ __asm__(".set push;\n"
+ ".set mips3;\n"
+ "wait;\n"
+ ".set pop;\n"
+ );
+ }
+}
+
+void jz4740_reset_init(void)
+{
+ _machine_halt = jz4740_halt;
+}
diff --git a/marvell/linux/arch/mips/jz4740/reset.h b/marvell/linux/arch/mips/jz4740/reset.h
new file mode 100644
index 0000000..4e8746e
--- /dev/null
+++ b/marvell/linux/arch/mips/jz4740/reset.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __MIPS_JZ4740_RESET_H__
+#define __MIPS_JZ4740_RESET_H__
+
+extern void jz4740_reset_init(void);
+
+#endif
diff --git a/marvell/linux/arch/mips/jz4740/setup.c b/marvell/linux/arch/mips/jz4740/setup.c
new file mode 100644
index 0000000..45e3279
--- /dev/null
+++ b/marvell/linux/arch/mips/jz4740/setup.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ * Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org>
+ * JZ4740 setup code
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/kernel.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+
+#include <asm/bootinfo.h>
+#include <asm/prom.h>
+
+#include "reset.h"
+
+#define JZ4740_EMC_BASE_ADDR 0x13010000
+
+#define JZ4740_EMC_SDRAM_CTRL 0x80
+
+static void __init jz4740_detect_mem(void)
+{
+ void __iomem *jz_emc_base;
+ u32 ctrl, bus, bank, rows, cols;
+ phys_addr_t size;
+
+ jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100);
+ ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL);
+ bus = 2 - ((ctrl >> 31) & 1);
+ bank = 1 + ((ctrl >> 19) & 1);
+ cols = 8 + ((ctrl >> 26) & 7);
+ rows = 11 + ((ctrl >> 20) & 3);
+ printk(KERN_DEBUG
+ "SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n",
+ bus, bank, rows, cols);
+ iounmap(jz_emc_base);
+
+ size = 1 << (bus + bank + cols + rows);
+ add_memory_region(0, size, BOOT_MEM_RAM);
+}
+
+static unsigned long __init get_board_mach_type(const void *fdt)
+{
+ if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1000"))
+ return MACH_INGENIC_X1000;
+ if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4780"))
+ return MACH_INGENIC_JZ4780;
+ if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4770"))
+ return MACH_INGENIC_JZ4770;
+
+ return MACH_INGENIC_JZ4740;
+}
+
+void __init plat_mem_setup(void)
+{
+ int offset;
+ void *dtb;
+
+ jz4740_reset_init();
+
+ if (&__dtb_start != &__dtb_end)
+ dtb = __dtb_start;
+ else
+ dtb = (void *)fw_passed_dtb;
+
+ __dt_setup_arch(dtb);
+
+ offset = fdt_path_offset(dtb, "/memory");
+ if (offset < 0)
+ jz4740_detect_mem();
+
+ mips_machtype = get_board_mach_type(dtb);
+}
+
+void __init device_tree_init(void)
+{
+ if (!initial_boot_params)
+ return;
+
+ unflatten_and_copy_device_tree();
+}
+
+const char *get_system_type(void)
+{
+ switch (mips_machtype) {
+ case MACH_INGENIC_X1000:
+ return "X1000";
+ case MACH_INGENIC_JZ4780:
+ return "JZ4780";
+ case MACH_INGENIC_JZ4770:
+ return "JZ4770";
+ default:
+ return "JZ4740";
+ }
+}
+
+void __init arch_init_irq(void)
+{
+ irqchip_init();
+}
diff --git a/marvell/linux/arch/mips/jz4740/time.c b/marvell/linux/arch/mips/jz4740/time.c
new file mode 100644
index 0000000..5476899
--- /dev/null
+++ b/marvell/linux/arch/mips/jz4740/time.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ * JZ4740 platform time support
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+
+#include <asm/mach-jz4740/timer.h>
+
+void __init plat_time_init(void)
+{
+ of_clk_init(NULL);
+ jz4740_timer_init();
+ timer_probe();
+}
diff --git a/marvell/linux/arch/mips/jz4740/timer.c b/marvell/linux/arch/mips/jz4740/timer.c
new file mode 100644
index 0000000..5c9f82d
--- /dev/null
+++ b/marvell/linux/arch/mips/jz4740/timer.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ * JZ4740 platform timer support
+ */
+
+#include <linux/export.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <asm/mach-jz4740/base.h>
+#include <asm/mach-jz4740/timer.h>
+
+void __iomem *jz4740_timer_base;
+EXPORT_SYMBOL_GPL(jz4740_timer_base);
+
+void jz4740_timer_enable_watchdog(void)
+{
+ writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog);
+
+void jz4740_timer_disable_watchdog(void)
+{
+ writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog);
+
+void __init jz4740_timer_init(void)
+{
+ jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
+
+ if (!jz4740_timer_base)
+ panic("Failed to ioremap timer registers");
+
+ /* Disable all timer clocks except for those used as system timers */
+ writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+
+ /* Timer irqs are unmasked by default, mask them */
+ writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
+}