ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/linux/drivers/crypto/asr/asr_aes_clk.c b/marvell/linux/drivers/crypto/asr/asr_aes_clk.c
new file mode 100644
index 0000000..d4510f5
--- /dev/null
+++ b/marvell/linux/drivers/crypto/asr/asr_aes_clk.c
@@ -0,0 +1,51 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+
+struct asr_crypto {
+ struct clk *aes_clk;
+ refcount_t refcount;
+ struct mutex clk_lock;
+};
+
+static struct asr_crypto asr_crypto = {
+ .aes_clk = 0,
+ .refcount = REFCOUNT_INIT(0),
+ .clk_lock = __MUTEX_INITIALIZER(asr_crypto.clk_lock),
+};
+
+int asr_aes_clk_get(struct clk *aes_clk)
+{
+ mutex_lock(&asr_crypto.clk_lock);
+
+ if (asr_crypto.aes_clk != aes_clk) {
+ asr_crypto.aes_clk = aes_clk;
+ }
+
+ if (refcount_read(&asr_crypto.refcount) == 0) {
+ clk_enable(asr_crypto.aes_clk);
+ refcount_set(&asr_crypto.refcount, 1);
+ } else {
+ refcount_inc(&asr_crypto.refcount);
+ }
+
+ mutex_unlock(&asr_crypto.clk_lock);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(asr_aes_clk_get);
+
+int asr_aes_clk_put(struct clk *aes_clk)
+{
+ mutex_lock(&asr_crypto.clk_lock);
+
+ if (refcount_dec_and_test(&asr_crypto.refcount)) {
+ clk_disable(asr_crypto.aes_clk);
+ }
+
+ mutex_unlock(&asr_crypto.clk_lock);
+ return 0;
+}
+
+EXPORT_SYMBOL_GPL(asr_aes_clk_put);
\ No newline at end of file