ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/linux/drivers/rtc/rtc-scs.c b/marvell/linux/drivers/rtc/rtc-scs.c
new file mode 100644
index 0000000..2096fb5
--- /dev/null
+++ b/marvell/linux/drivers/rtc/rtc-scs.c
@@ -0,0 +1,646 @@
+/*
+ * Base driver for ASR SCS RTC
+ *
+ * Copyright 2020 ASR Microelectronics (Shanghai) Co., Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/88pm80x.h>
+#include <linux/mfd/pm803.h>
+#include <linux/mfd/pm802.h>
+#include <linux/mfd/pm813.h>
+#include <linux/rtc.h>
+#include <linux/reboot.h>
+#include <linux/sysfs.h>
+#include <soc/asr/addr-map.h>
+#include <linux/cputype.h>
+
+#ifdef CONFIG_CPU_ASR1903
+#define SCS_RTC_FREQ (32765)
+#else
+#define SCS_RTC_FREQ (32787)
+#endif
+
+#define SCS_RTC_COUNTR (0x0)
+#define SCS_RTC_ALARM (0x4)
+#define SCS_RTC_TRIM (0x8)
+#define SCS_RTC_ALARM_EN (0x1 << 0)
+#define SCS_RTC_ALARM_MASK (0x1 << 0)
+#define SCS_RTC_ALARM_CLR (0x1 << 1)
+#define SCS_RTC_CNTL (0xc)
+#define SCS_IDAC_CODE (0x10)
+#define SCS_RTC_SYNC_CFG (0x14)
+#define SCS_DCS_MODE (0x1c)
+#define SCS_CLEAR_SYNC_DONE (0x1 << 0 | 0x1 << 6)
+#define SCS_SYNC_IDAC_CODE (0x1 << 0 | 0x1 << 5)
+#define SCS_SYNC_RTC_CNRL (0x1 << 0 | 0x1 << 4)
+#define SCS_SYNC_RTC_TRIM (0x1 << 0 | 0x1 << 3)
+#define SCS_SYNC_RTC_ALARM (0x1 << 0 | 0x1 << 2)
+#define SCS_SYNC_RTC_ALARM_CNTL (0x1 << 0 | 0x1 << 2 | 0x1 << 4)
+#define SCS_SYNC_RTC_COUNTER (0x1 << 0 | 0x1 << 1)
+#define SCS_RTC_VIRT_BASE (APB_VIRT_BASE + 0x03E000)
+#define ASR1903_SCS_RTC_VIRT_BASE (APB_VIRT_BASE + 0x0C0000)
+
+#define SCR_RTC_SYNC_UDELAY (130)
+
+struct scs_rtc_info {
+ spinlock_t lock;
+ void __iomem *base;
+ struct pm80x_chip *chip;
+ struct regmap *map;
+ struct rtc_device *rtc_dev;
+ struct device *dev;
+ int irq;
+ int vrtc;
+ int (*sync) (s64 ticks);
+
+#ifdef CONFIG_RTC_DRV_SA1100
+ struct delayed_work sa1100_sync_work;
+#endif
+};
+
+static s64 base_ticks;
+#ifdef CONFIG_RTC_DRV_SA1100
+extern int sync_time_to_soc(s64 ticks);
+#endif
+static int scs_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled);
+
+#ifdef CONFIG_RTC_DRV_SA1100
+static int scs_rtc_read_time(struct device *dev, struct rtc_time *tm);
+static void sa1100_sync_fn(struct work_struct *work)
+{
+ struct scs_rtc_info *info =
+ container_of(work, struct scs_rtc_info, sa1100_sync_work.work);
+ s64 ticks;
+ struct rtc_time tm;
+ int ret;
+
+ ret = scs_rtc_read_time(info->dev, &tm);
+ if (ret < 0) {
+ dev_err(info->dev, "Failed to read time.\n");
+ return;
+ }
+
+ ticks = rtc_tm_to_time64(&tm);
+ if (info->sync)
+ info->sync(ticks);
+}
+#endif
+
+static int pm80x_write_base_ticks(struct scs_rtc_info *info, s64 base_ticks)
+{
+ u8 buf[5];
+ u32 reg = PM802_RTC_EXPIRE2_1;
+
+ BUG_ON(CHIP_PM801 == info->chip->type);
+ buf[0] = base_ticks & 0xFF;
+ buf[1] = (base_ticks >> 8) & 0xFF;
+ buf[2] = (base_ticks >> 16) & 0xFF;
+ buf[3] = (base_ticks >> 24) & 0xFF;
+ buf[4] = (base_ticks >> 32) & 0xFF;
+ dev_dbg(info->dev, "set base ticks:0x%llx\n", base_ticks);
+
+ if (CHIP_PM803 != info->chip->type) {
+ regmap_raw_write(info->map, reg, buf, 4);
+ }
+
+ if (CHIP_PM802 == info->chip->type) {
+ if (CHIP_PM802_ID_B1 == info->chip->chip_id ||
+ CHIP_PM802_ID_B0 == info->chip->chip_id) {
+ regmap_raw_read(info->map, PM802_RTC_MISC14, buf, 1);
+ buf[0] &= 0x0f;
+ buf[0] |= ((buf[4] & 0xf) << 4);
+ /* F1[7:4] */
+ regmap_raw_write(info->map, PM802_RTC_MISC14, &buf[0], 1);
+ } else {
+ /* CD[7:0] */
+ regmap_raw_write(info->map, PM802S_RTC_SPARED, &buf[4], 1);
+ }
+ } else if (CHIP_PM803 == info->chip->type) {
+ regmap_raw_write(info->map, PM803_RTC_MISC18, &buf[0], 3);
+ regmap_raw_write(info->map, PM803_RTC_SPARE5, &buf[3], 2);
+ } else if (CHIP_PM813 == info->chip->type) {
+ if (CHIP_PM813_ID == info->chip->chip_id) {
+ /* F6[7:0] */
+ regmap_raw_write(info->map, PM813_RTC_MISC19, &buf[4], 1);
+ } else {
+ /* CD[7:0] */
+ regmap_raw_write(info->map, PM813S_RTC_SPARED, &buf[4], 1);
+ }
+ } else {
+ BUG();
+ }
+
+ return 0;
+}
+
+static int pm80x_read_base_ticks(struct scs_rtc_info *info, s64 *base_ticks)
+{
+ u8 buf[5];
+ u32 reg = PM802_RTC_EXPIRE2_1;
+
+ BUG_ON(CHIP_PM801 == info->chip->type);
+
+ if (CHIP_PM803 != info->chip->type) {
+ regmap_raw_read(info->map, reg, buf, 4);
+ }
+
+ if (CHIP_PM802 == info->chip->type) {
+ if (CHIP_PM802_ID_B1 == info->chip->chip_id ||
+ CHIP_PM802_ID_B0 == info->chip->chip_id) {
+ /* F1[7:4] */
+ regmap_raw_read(info->map, PM802_RTC_MISC14, &buf[4], 1);
+ buf[4] = (buf[4] >> 4) & 0xf;
+ } else {
+ /* CD[7:0] */
+ regmap_raw_read(info->map, PM802S_RTC_SPARED, &buf[4], 1);
+ }
+ } else if (CHIP_PM803 == info->chip->type) {
+ regmap_raw_read(info->map, PM803_RTC_MISC18, &buf[0], 3);
+ regmap_raw_read(info->map, PM803_RTC_SPARE5, &buf[3], 2);
+ } else if (CHIP_PM813 == info->chip->type) {
+ if (CHIP_PM813_ID == info->chip->chip_id) {
+ /* F6[7:0] */
+ regmap_raw_read(info->map, PM813_RTC_MISC19, &buf[4], 1);
+ } else {
+ /* CD[7:0] */
+ regmap_raw_read(info->map, PM813S_RTC_SPARED, &buf[4], 1);
+ }
+ }
+
+ *base_ticks = (((s64)buf[4]) << 60) >> 28;
+ *base_ticks |= (((u32)buf[3]) << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
+
+ dev_dbg(info->dev, "%x-%x-%x-%x-%x, base_ticks: %llx\n",
+ buf[0], buf[1], buf[2], buf[3], buf[4], *base_ticks);
+
+ return 0;
+}
+
+static int scs_rtc_alarm_clear(struct device *dev)
+{
+ struct scs_rtc_info *info = dev_get_drvdata(dev);
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&info->lock, flags);
+ writel(readl(info->base + SCS_RTC_CNTL) | SCS_RTC_ALARM_CLR,
+ info->base + SCS_RTC_CNTL);
+ writel(SCS_SYNC_RTC_CNRL, info->base + SCS_RTC_SYNC_CFG);
+ udelay(SCR_RTC_SYNC_UDELAY);
+ writel(SCS_CLEAR_SYNC_DONE, info->base + SCS_RTC_SYNC_CFG);
+ spin_unlock_irqrestore(&info->lock, flags);
+
+ return ret;
+}
+
+static int scs_rtc_update_trim(struct device *dev)
+{
+ struct scs_rtc_info *info = dev_get_drvdata(dev);
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&info->lock, flags);
+ if (cpu_is_asr1803_a0())
+ writel(0xffff, info->base + SCS_RTC_TRIM);
+ else
+ writel((SCS_RTC_FREQ - 1), info->base + SCS_RTC_TRIM);
+ writel(SCS_SYNC_RTC_TRIM, info->base + SCS_RTC_SYNC_CFG);
+ udelay(SCR_RTC_SYNC_UDELAY);
+ writel(SCS_CLEAR_SYNC_DONE, info->base + SCS_RTC_SYNC_CFG);
+
+ if (cpu_is_asr1903()) {
+ writel(0x14, info->base + SCS_IDAC_CODE);
+ writel(SCS_SYNC_IDAC_CODE, info->base + SCS_RTC_SYNC_CFG);
+ udelay(SCR_RTC_SYNC_UDELAY);
+ writel(SCS_CLEAR_SYNC_DONE, info->base + SCS_RTC_SYNC_CFG);
+ }
+ spin_unlock_irqrestore(&info->lock, flags);
+
+ return ret;
+}
+
+static irqreturn_t rtc_update_handler(int irq, void *data)
+{
+ struct scs_rtc_info *info = (struct scs_rtc_info *)data;
+
+ scs_rtc_alarm_clear(info->dev);
+ rtc_update_irq(info->rtc_dev, 1, RTC_AF);
+ return IRQ_HANDLED;
+}
+
+static int scs_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ unsigned long time_sec;
+ u64 tmp_sec;
+ u32 val1, val2;
+ s64 ticks;
+ struct scs_rtc_info *info = dev_get_drvdata(dev);
+
+ do {
+ val1 = readl(info->base + SCS_RTC_COUNTR);
+ val2 = readl(info->base + SCS_RTC_COUNTR);
+ } while (val2 != val1);
+
+ if (cpu_is_asr1803_a0()) {
+ tmp_sec = ((u64)val1) * 261993;
+ do_div(tmp_sec, (3 * 128 * 1024));
+ time_sec = (u32)tmp_sec;
+ } else {
+ time_sec = val1;
+ }
+
+ pm80x_read_base_ticks(info, &base_ticks);
+ ticks = time_sec + base_ticks;
+ rtc_time64_to_tm(ticks, tm);
+
+ return 0;
+}
+
+static int scs_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ unsigned long time;
+ u64 tmp_sec;
+ s64 ticks;
+ u32 val1, val2;
+ struct scs_rtc_info *info = dev_get_drvdata(dev);
+ int ret = 0;
+ unsigned long flags;
+
+ if ((tm->tm_year < 70) || (tm->tm_year > 300)) {
+ dev_err(info->dev,
+ "SCSRTC: Set time %d out of range. Please set time between 1970 to 2200.\n",
+ 1900 + tm->tm_year);
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&info->lock, flags);
+ ticks = rtc_tm_to_time64(tm);
+ do {
+ val1 = readl(info->base + SCS_RTC_COUNTR);
+ val2 = readl(info->base + SCS_RTC_COUNTR);
+ } while (val2 != val1);
+
+ if (cpu_is_asr1803_a0()) {
+ tmp_sec = ((u64)val1) * 261993;
+ do_div(tmp_sec, (3 * 128 * 1024));
+ time = (u32)tmp_sec;
+ } else {
+ time = val1;
+ }
+
+ base_ticks = ticks - time;
+ spin_unlock_irqrestore(&info->lock, flags);
+ pm80x_write_base_ticks(info, base_ticks);
+ spin_lock_irqsave(&info->lock, flags);
+#if 0
+ if (cpu_is_asr1803_a0()) {
+ tmp_sec = ((u64)time) * (3 * 128 * 1024);
+ do_div(tmp_sec, 261993);
+ time = (unsigned long)tmp_sec;
+ }
+ writel(time, info->base + SCS_RTC_COUNTR);
+
+ writel(SCS_SYNC_RTC_COUNTER, info->base + SCS_RTC_SYNC_CFG);
+ udelay(SCR_RTC_SYNC_UDELAY);
+ writel(SCS_CLEAR_SYNC_DONE, info->base + SCS_RTC_SYNC_CFG);
+#endif
+ if (info->sync)
+ info->sync(ticks);
+ spin_unlock_irqrestore(&info->lock, flags);
+
+ return ret;
+}
+
+static int scs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ unsigned long ticks;
+ u64 tmp_sec;
+ s64 time;
+ struct scs_rtc_info *info = dev_get_drvdata(dev);
+
+ ticks = readl(info->base + SCS_RTC_ALARM);
+ if (cpu_is_asr1803_a0()) {
+ tmp_sec = ((u64)ticks) * 261993;
+ do_div(tmp_sec, (3 * 128 * 1024));
+ ticks = (u32)tmp_sec;
+ }
+
+ pm80x_read_base_ticks(info, &base_ticks);
+ time = ticks + base_ticks;
+
+ rtc_time64_to_tm(time, &alrm->time);
+ ticks = readl(info->base + SCS_RTC_CNTL);
+ alrm->enabled = ((ticks & SCS_RTC_ALARM_MASK) == SCS_RTC_ALARM_EN) ? 1 : 0;
+ alrm->pending = 0;
+ return 0;
+}
+
+static int scs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct scs_rtc_info *info = dev_get_drvdata(dev);
+ unsigned long flags;
+ u64 tmp_sec;
+ s64 ticks;
+ u32 time;
+
+ ticks = rtc_tm_to_time64(&alrm->time);
+ pm80x_read_base_ticks(info, &base_ticks);
+ ticks = ticks - base_ticks;
+ if (cpu_is_asr1803_a0()) {
+ tmp_sec = ((u64)ticks) * (3 * 128 * 1024);
+ //time = tmp_sec / 261993;
+ do_div(tmp_sec, 261993);
+ time = (u32)tmp_sec;
+ } else {
+ time = (u32)ticks;
+ }
+
+ spin_lock_irqsave(&info->lock, flags);
+ writel(time, info->base + SCS_RTC_ALARM);
+ writel(SCS_SYNC_RTC_ALARM_CNTL, info->base + SCS_RTC_SYNC_CFG);
+ udelay(SCR_RTC_SYNC_UDELAY);
+ writel(SCS_CLEAR_SYNC_DONE, info->base + SCS_RTC_SYNC_CFG);
+ spin_unlock_irqrestore(&info->lock, flags);
+ scs_rtc_alarm_irq_enable(dev, alrm->enabled);
+ return 0;
+}
+
+static int scs_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+{
+ struct scs_rtc_info *info = dev_get_drvdata(dev);
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&info->lock, flags);
+ if (enabled)
+ writel(readl(info->base + SCS_RTC_CNTL) | SCS_RTC_ALARM_MASK,
+ info->base + SCS_RTC_CNTL);
+ else
+ writel(readl(info->base + SCS_RTC_CNTL) & (~SCS_RTC_ALARM_MASK),
+ info->base + SCS_RTC_CNTL);
+ writel(SCS_SYNC_RTC_CNRL, info->base + SCS_RTC_SYNC_CFG);
+ udelay(SCR_RTC_SYNC_UDELAY);
+ writel(SCS_CLEAR_SYNC_DONE, info->base + SCS_RTC_SYNC_CFG);
+ spin_unlock_irqrestore(&info->lock, flags);
+
+ return ret;
+}
+
+static const struct rtc_class_ops scs_rtc_ops = {
+ .read_time = scs_rtc_read_time,
+ .set_time = scs_rtc_set_time,
+ .read_alarm = scs_rtc_read_alarm,
+ .set_alarm = scs_rtc_set_alarm,
+ .alarm_irq_enable = scs_rtc_alarm_irq_enable,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int scs_rtc_suspend(struct device *dev)
+{
+ return pm80x_dev_suspend(dev);
+}
+
+static int scs_rtc_resume(struct device *dev)
+{
+ return pm80x_dev_resume(dev);
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(scs_rtc_pm_ops, scs_rtc_suspend, scs_rtc_resume);
+
+static struct delayed_work sync_work;
+static unsigned int print_tstamp_delay = 30;
+static void sync_timestamp(struct work_struct *work)
+{
+ struct timespec64 ts;
+ struct rtc_time tm;
+
+ ktime_get_real_ts64(&ts);
+ rtc_time64_to_tm(ts.tv_sec - sys_tz.tz_minuteswest * 60, &tm);
+ pr_info("Timestamp is: %02d-%02d %02d:%02d:%02d.%03lu UTC\n",
+ tm.tm_mon + 1, tm.tm_mday, tm.tm_hour, tm.tm_min,
+ tm.tm_sec, ts.tv_nsec);
+ /* print timestamp every 30 minutes */
+ schedule_delayed_work(&sync_work, print_tstamp_delay*60*HZ);
+}
+
+#ifdef CONFIG_SYSFS
+static ssize_t tstamp_show_delay(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return snprintf(buf, PAGE_SIZE, "%u\n", print_tstamp_delay);
+}
+static ssize_t tstamp_store_delay(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ char *end;
+ unsigned long new = simple_strtoul(buf, &end, 0);
+ if (end == buf)
+ return -EINVAL;
+ print_tstamp_delay = new;
+ cancel_delayed_work(&sync_work);
+ schedule_delayed_work(&sync_work, print_tstamp_delay*60*HZ);
+ return size;
+}
+static DEVICE_ATTR(tstamp_delay, 0664, tstamp_show_delay, tstamp_store_delay);
+
+static int add_tstamp_delay(struct device *dev)
+{
+ return device_create_file(dev, &dev_attr_tstamp_delay);
+}
+
+static void remove_tstamp_delay(struct device *dev)
+{
+ device_remove_file(dev, &dev_attr_tstamp_delay);
+}
+
+#else
+#define add_tstamp_delay(dev) 0
+#define remove_tstamp_delay(dev) do {} while (0)
+#endif /* CONFIG_SYSFS */
+
+static int scs_rtc_probe(struct platform_device *pdev)
+{
+ struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
+ struct pm80x_rtc_pdata *pdata = NULL;
+ struct scs_rtc_info *info;
+ struct rtc_time tm;
+ int ret;
+
+ if (cpu_is_asr1803_z1())
+ return -ENODEV;
+
+ INIT_DEFERRABLE_WORK(&sync_work, sync_timestamp);
+ schedule_delayed_work(&sync_work, 1*60*HZ);
+ add_tstamp_delay(&pdev->dev);
+
+ pdata = pdev->dev.platform_data;
+ if (IS_ENABLED(CONFIG_OF)) {
+ if (!pdata) {
+ pdata = devm_kzalloc(&pdev->dev,
+ sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+ }
+ } else if (!pdata) {
+ return -EINVAL;
+ }
+
+ info =
+ devm_kzalloc(&pdev->dev, sizeof(struct scs_rtc_info), GFP_KERNEL);
+ if (!info)
+ return -ENOMEM;
+ info->irq = platform_get_irq(pdev, 0);
+ if (info->irq < 0) {
+ dev_err(&pdev->dev, "No IRQ resource!\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ info->chip = chip;
+ info->map = chip->regmap;
+ if (!info->map) {
+ dev_err(&pdev->dev, "no regmap!\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ if (cpu_is_asr1903())
+ info->base = ASR1903_SCS_RTC_VIRT_BASE;
+ else
+ info->base = SCS_RTC_VIRT_BASE;
+ spin_lock_init(&info->lock);
+
+ info->dev = &pdev->dev;
+ dev_set_drvdata(&pdev->dev, info);
+
+ scs_rtc_alarm_clear(&pdev->dev);
+ scs_rtc_update_trim(&pdev->dev);
+ scs_rtc_alarm_irq_enable(&pdev->dev, 0);
+ ret = scs_rtc_read_time(&pdev->dev, &tm);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to read initial time.\n");
+ goto out;
+ }
+
+ if ((tm.tm_year < 70) || (tm.tm_year > 1157)) {
+ tm.tm_year = 70;
+ tm.tm_mon = 0;
+ tm.tm_mday = 1;
+ tm.tm_hour = 0;
+ tm.tm_min = 0;
+ tm.tm_sec = 0;
+ ret = scs_rtc_set_time(&pdev->dev, &tm);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to set initial time.\n");
+ goto out;
+ }
+ }
+
+ info->sync = NULL; /*initialize*/
+#ifdef CONFIG_RTC_DRV_SA1100
+ info->sync = sync_time_to_soc;
+ INIT_DELAYED_WORK(&info->sa1100_sync_work, sa1100_sync_fn);
+ schedule_delayed_work(&info->sa1100_sync_work, 2 * HZ);
+#endif
+
+ dev_info(&pdev->dev, "%d-%d-%d-->%d: %d: %d\n",
+ tm.tm_year, tm.tm_mon, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec);
+
+ info->rtc_dev = devm_rtc_device_register(&pdev->dev, "scs-rtc",
+ &scs_rtc_ops, THIS_MODULE);
+ if (IS_ERR(info->rtc_dev)) {
+ ret = PTR_ERR(info->rtc_dev);
+ dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
+ goto out;
+ }
+
+ /* remeber whether this power up is caused by PMIC RTC or not. */
+ info->rtc_dev->dev.platform_data = &pdata->rtc_wakeup;
+ ret = pm80x_request_irq(chip, info->irq, rtc_update_handler,
+ IRQF_ONESHOT | IRQF_NO_SUSPEND , "rtc", info);
+ if (ret < 0) {
+ dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+ info->irq, ret);
+ goto out;
+ }
+
+ BUG_ON((CHIP_PM801 == info->chip->type) || (CHIP_PM800 == info->chip->type));
+
+ device_init_wakeup(&pdev->dev, 1);
+
+ return 0;
+out:
+ return ret;
+}
+
+static int scs_rtc_remove(struct platform_device *pdev)
+{
+ struct scs_rtc_info *info = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+ pm80x_free_irq(info->chip, info->irq, info);
+ remove_tstamp_delay(&pdev->dev);
+ return 0;
+}
+
+static void scs_rtc_shutdown(struct platform_device *pdev)
+{
+ struct timespec64 now;
+ struct rtc_time tm;
+ struct scs_rtc_info *info = platform_get_drvdata(pdev);
+
+ /* sync timekeeping time to pmic rtc */
+ ktime_get_real_ts64(&now);
+ if (now.tv_nsec < (NSEC_PER_SEC >> 1))
+ rtc_time64_to_tm(now.tv_sec, &tm);
+ else
+ rtc_time64_to_tm(now.tv_sec + 1, &tm);
+ scs_rtc_set_time(info->dev, &tm);
+ pm80x_free_irq(info->chip, info->irq, info);
+}
+
+static struct platform_driver scs_rtc_driver = {
+ .driver = {
+ .name = "scs-rtc",
+ .owner = THIS_MODULE,
+ .pm = &scs_rtc_pm_ops,
+ },
+ .probe = scs_rtc_probe,
+ .remove = scs_rtc_remove,
+ .shutdown = scs_rtc_shutdown,
+};
+
+static int __init scs_rtc_init(void)
+{
+ return platform_driver_register(&scs_rtc_driver);
+}
+module_init(scs_rtc_init);
+
+static void __exit scs_rtc_exit(void)
+{
+ platform_driver_unregister(&scs_rtc_driver);
+}
+module_exit(scs_rtc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ASR PM803 and SCS RTC driver");