ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/linux/drivers/usb/dwc2/platform.c b/marvell/linux/drivers/usb/dwc2/platform.c
new file mode 100644
index 0000000..188d0cd
--- /dev/null
+++ b/marvell/linux/drivers/usb/dwc2/platform.c
@@ -0,0 +1,720 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * platform.c - DesignWare HS OTG Controller platform driver
+ *
+ * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions, and the following disclaimer,
+ * without modification.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The names of the above-listed copyright holders may not be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/of_device.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_data/s3c-hsotg.h>
+#include <linux/reset.h>
+
+#include <linux/usb/of.h>
+#include <soc/asr/regs-addr.h>
+#include <linux/platform_data/mv_usb.h>
+#include <linux/usb/mv_usb2_phy.h>
+
+#include "core.h"
+#include "hcd.h"
+#include "debug.h"
+
+static const char dwc2_driver_name[] = "dwc2";
+
+#define USB_HANDLE_TIME_MSEC (5000)
+
+#define APMU_USB_WAKE_CLR (0x07c)
+
+#define USB_VBUS_WAKE_EN (0x1 << 11)
+#define USB_ID_WAKE_EN (0x1 << 22)
+#define USB_LINEST_WAKE_EN ((0x1 << 9) | (0x1 << 10))
+
+#define USB_VBUS_WAKE_CLR (0x1 << 4)
+#define USB_ID_WAKE_CLR (0x1 << 23)
+#define USB_LINEST_WAKE_CLR (0x1 << 7)
+extern void dwc2_release_pm_qos(void);
+extern void dwc2_acquire_pm_qos(void);
+
+static irqreturn_t vbus_irq(int irq, void *dev)
+{
+ struct dwc2_hsotg *hsotg_dev = (struct dwc2_hsotg *)dev;
+ void __iomem *apmu_base = regs_addr_get_va(REGS_ADDR_APMU);
+
+ /* wait 50ms for vbus to be stable */
+ msleep(50);
+ writel(readl(apmu_base + APMU_USB_WAKE_CLR)
+ | (USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR
+ | USB_ID_WAKE_CLR),
+ apmu_base + APMU_USB_WAKE_CLR);
+
+ pm_wakeup_event(hsotg_dev->dev, USB_HANDLE_TIME_MSEC);
+ pxa_usb_notify(PXA_USB_DEV_OTG, EVENT_VBUS, 0);
+ dev_info(hsotg_dev->dev, "asr-usb vbus interrupt is served..\n");
+ return IRQ_HANDLED;
+}
+
+/*
+ * Check the dr_mode against the module configuration and hardware
+ * capabilities.
+ *
+ * The hardware, module, and dr_mode, can each be set to host, device,
+ * or otg. Check that all these values are compatible and adjust the
+ * value of dr_mode if possible.
+ *
+ * actual
+ * HW MOD dr_mode dr_mode
+ * ------------------------------
+ * HST HST any : HST
+ * HST DEV any : ---
+ * HST OTG any : HST
+ *
+ * DEV HST any : ---
+ * DEV DEV any : DEV
+ * DEV OTG any : DEV
+ *
+ * OTG HST any : HST
+ * OTG DEV any : DEV
+ * OTG OTG any : dr_mode
+ */
+static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
+{
+ enum usb_dr_mode mode;
+
+ hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
+ if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
+ hsotg->dr_mode = USB_DR_MODE_OTG;
+
+ mode = hsotg->dr_mode;
+
+ if (dwc2_hw_is_device(hsotg)) {
+ if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
+ dev_err(hsotg->dev,
+ "Controller does not support host mode.\n");
+ return -EINVAL;
+ }
+ mode = USB_DR_MODE_PERIPHERAL;
+ } else if (dwc2_hw_is_host(hsotg)) {
+ if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
+ dev_err(hsotg->dev,
+ "Controller does not support device mode.\n");
+ return -EINVAL;
+ }
+ mode = USB_DR_MODE_HOST;
+ } else {
+ if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
+ mode = USB_DR_MODE_HOST;
+ else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
+ mode = USB_DR_MODE_PERIPHERAL;
+ }
+
+ if (mode != hsotg->dr_mode) {
+ dev_warn(hsotg->dev,
+ "Configuration mismatch. dr_mode forced to %s\n",
+ mode == USB_DR_MODE_HOST ? "host" : "device");
+
+ hsotg->dr_mode = mode;
+ }
+
+ return 0;
+}
+
+static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
+{
+ struct platform_device *pdev = to_platform_device(hsotg->dev);
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
+ hsotg->supplies);
+ if (ret)
+ return ret;
+
+ if (hsotg->clk) {
+ ret = clk_prepare_enable(hsotg->clk);
+ if (ret)
+ return ret;
+ }
+
+ if (hsotg->uphy) {
+ ret = usb_phy_init(hsotg->uphy);
+ } else if (hsotg->plat && hsotg->plat->phy_init) {
+ ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
+ } else {
+ ret = phy_init(hsotg->phy);
+ if (ret == 0)
+ ret = phy_power_on(hsotg->phy);
+ }
+
+ return ret;
+}
+
+/**
+ * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
+ * @hsotg: The driver state
+ *
+ * A wrapper for platform code responsible for controlling
+ * low-level USB platform resources (phy, clock, regulators)
+ */
+int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
+{
+ int ret = __dwc2_lowlevel_hw_enable(hsotg);
+
+ if (ret == 0)
+ hsotg->ll_hw_enabled = true;
+ return ret;
+}
+
+static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
+{
+ struct platform_device *pdev = to_platform_device(hsotg->dev);
+ int ret = 0;
+
+#ifdef CONFIG_CPU_ASR18XX
+ return 0;
+#endif
+
+ if (hsotg->uphy) {
+ usb_phy_shutdown(hsotg->uphy);
+ } else if (hsotg->plat && hsotg->plat->phy_exit) {
+ ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
+ } else {
+ ret = phy_power_off(hsotg->phy);
+ if (ret == 0)
+ ret = phy_exit(hsotg->phy);
+ }
+ if (ret)
+ return ret;
+
+ if (hsotg->clk)
+ clk_disable_unprepare(hsotg->clk);
+
+ ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
+ hsotg->supplies);
+
+ return ret;
+}
+
+/**
+ * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
+ * @hsotg: The driver state
+ *
+ * A wrapper for platform code responsible for controlling
+ * low-level USB platform resources (phy, clock, regulators)
+ */
+int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
+{
+ int ret = __dwc2_lowlevel_hw_disable(hsotg);
+
+ if (ret == 0)
+ hsotg->ll_hw_enabled = false;
+ return ret;
+}
+
+static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
+{
+ int i, ret;
+
+ hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
+ if (IS_ERR(hsotg->reset)) {
+ ret = PTR_ERR(hsotg->reset);
+ dev_err(hsotg->dev, "error getting reset control %d\n", ret);
+ return ret;
+ }
+
+ reset_control_deassert(hsotg->reset);
+
+ hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
+ if (IS_ERR(hsotg->reset_ecc)) {
+ ret = PTR_ERR(hsotg->reset_ecc);
+ dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
+ return ret;
+ }
+
+ reset_control_deassert(hsotg->reset_ecc);
+
+ /*
+ * Attempt to find a generic PHY, then look for an old style
+ * USB PHY and then fall back to pdata
+ */
+ hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
+ if (IS_ERR(hsotg->phy)) {
+ ret = PTR_ERR(hsotg->phy);
+ switch (ret) {
+ case -ENODEV:
+ case -ENOSYS:
+ hsotg->phy = NULL;
+ break;
+ case -EPROBE_DEFER:
+ return ret;
+ default:
+ dev_err(hsotg->dev, "error getting phy %d\n", ret);
+ return ret;
+ }
+ }
+
+ if (!hsotg->phy) {
+ hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(hsotg->uphy)) {
+ ret = PTR_ERR(hsotg->uphy);
+ switch (ret) {
+ case -ENODEV:
+ case -ENXIO:
+ hsotg->uphy = NULL;
+ break;
+ case -EPROBE_DEFER:
+ return ret;
+ default:
+ dev_err(hsotg->dev, "error getting usb phy %d\n",
+ ret);
+ return ret;
+ }
+ }
+ }
+
+ hsotg->plat = dev_get_platdata(hsotg->dev);
+
+ /* Clock */
+ hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
+ if (IS_ERR(hsotg->clk)) {
+ dev_err(hsotg->dev, "cannot get otg clock\n");
+ return PTR_ERR(hsotg->clk);
+ }
+
+ /* Regulators */
+ for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
+ hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
+
+ ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
+ hsotg->supplies);
+ if (ret) {
+ dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+/**
+ * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
+ * DWC_otg driver
+ *
+ * @dev: Platform device
+ *
+ * This routine is called, for example, when the rmmod command is executed. The
+ * device may or may not be electrically present. If it is present, the driver
+ * stops device processing. Any resources used on behalf of this device are
+ * freed.
+ */
+static int dwc2_driver_remove(struct platform_device *dev)
+{
+ struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
+
+ dwc2_debugfs_exit(hsotg);
+ if (hsotg->hcd_enabled)
+ dwc2_hcd_remove(hsotg);
+ if (hsotg->gadget_enabled)
+ dwc2_hsotg_remove(hsotg);
+
+ if (hsotg->ll_hw_enabled)
+ dwc2_lowlevel_hw_disable(hsotg);
+
+ reset_control_assert(hsotg->reset);
+ reset_control_assert(hsotg->reset_ecc);
+
+ return 0;
+}
+
+/**
+ * dwc2_driver_shutdown() - Called on device shutdown
+ *
+ * @dev: Platform device
+ *
+ * In specific conditions (involving usb hubs) dwc2 devices can create a
+ * lot of interrupts, even to the point of overwhelming devices running
+ * at low frequencies. Some devices need to do special clock handling
+ * at shutdown-time which may bring the system clock below the threshold
+ * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
+ * prevents reboots/poweroffs from getting stuck in such cases.
+ */
+static void dwc2_driver_shutdown(struct platform_device *dev)
+{
+ struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
+
+ dwc2_disable_global_interrupts(hsotg);
+ synchronize_irq(hsotg->irq);
+}
+
+/**
+ * dwc2_check_core_endianness() - Returns true if core and AHB have
+ * opposite endianness.
+ * @hsotg: Programming view of the DWC_otg controller.
+ */
+static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
+{
+ u32 snpsid;
+
+ snpsid = ioread32(hsotg->regs + GSNPSID);
+ if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
+ (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
+ (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
+ return false;
+ return true;
+}
+
+/**
+ * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
+ * driver
+ *
+ * @dev: Platform device
+ *
+ * This routine creates the driver components required to control the device
+ * (core, HCD, and PCD) and initializes the device. The driver components are
+ * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
+ * in the device private data. This allows the driver to access the dwc2_hsotg
+ * structure on subsequent calls to driver methods for this device.
+ */
+static int dwc2_driver_probe(struct platform_device *dev)
+{
+ struct dwc2_hsotg *hsotg;
+ struct resource *res;
+ int retval;
+ void __iomem *apmu_base;
+
+ hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
+ if (!hsotg)
+ return -ENOMEM;
+
+ hsotg->dev = &dev->dev;
+
+ /*
+ * Use reasonable defaults so platforms don't have to provide these.
+ */
+ if (!dev->dev.dma_mask)
+ dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
+ retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
+ if (retval) {
+ dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
+ return retval;
+ }
+
+ res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ hsotg->regs = devm_ioremap_resource(&dev->dev, res);
+ if (IS_ERR(hsotg->regs))
+ return PTR_ERR(hsotg->regs);
+
+ dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
+ (unsigned long)res->start, hsotg->regs);
+
+ retval = dwc2_lowlevel_hw_init(hsotg);
+ if (retval)
+ return retval;
+
+ spin_lock_init(&hsotg->lock);
+
+ hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
+ if (IS_ERR(hsotg->vbus_supply)) {
+ retval = PTR_ERR(hsotg->vbus_supply);
+ hsotg->vbus_supply = NULL;
+ if (retval != -ENODEV)
+ return retval;
+ }
+
+ retval = dwc2_lowlevel_hw_enable(hsotg);
+ if (retval)
+ return retval;
+
+ hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
+
+ retval = dwc2_get_dr_mode(hsotg);
+ if (retval)
+ goto error;
+
+ hsotg->need_phy_for_wake =
+ of_property_read_bool(dev->dev.of_node,
+ "snps,need-phy-for-wake");
+ hsotg->no_acchg_det =
+ of_property_read_bool(dev->dev.of_node,
+ "snps,no-acchg-det");
+
+ /*
+ * Reset before dwc2_get_hwparams() then it could get power-on real
+ * reset value form registers.
+ */
+ retval = dwc2_core_reset(hsotg, false);
+ if (retval)
+ goto error;
+
+ /* Detect config values from hardware */
+ retval = dwc2_get_hwparams(hsotg);
+ if (retval)
+ goto error;
+
+ hsotg->irq = platform_get_irq(dev, 0);
+ if (hsotg->irq < 0) {
+ retval = hsotg->irq;
+ goto error;
+ }
+
+ dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
+ hsotg->irq);
+ retval = devm_request_irq(hsotg->dev, hsotg->irq,
+ dwc2_handle_common_intr, IRQF_SHARED,
+ dev_name(hsotg->dev), hsotg);
+ if (retval)
+ goto error;
+
+ /*
+ * For OTG cores, set the force mode bits to reflect the value
+ * of dr_mode. Force mode bits should not be touched at any
+ * other time after this.
+ */
+ dwc2_force_dr_mode(hsotg);
+
+ retval = dwc2_init_params(hsotg);
+ if (retval)
+ goto error;
+
+ if (hsotg->dr_mode != USB_DR_MODE_HOST) {
+ retval = dwc2_gadget_init(hsotg);
+ if (retval)
+ goto error;
+ hsotg->gadget_enabled = 1;
+ }
+
+ /*
+ * If we need PHY for wakeup we must be wakeup capable.
+ * When we have a device that can wake without the PHY we
+ * can adjust this condition.
+ */
+ if (hsotg->need_phy_for_wake)
+ device_set_wakeup_capable(&dev->dev, true);
+
+ hsotg->reset_phy_on_wake =
+ of_property_read_bool(dev->dev.of_node,
+ "snps,reset-phy-on-wake");
+ if (hsotg->reset_phy_on_wake && !hsotg->phy) {
+ dev_warn(hsotg->dev,
+ "Quirk reset-phy-on-wake only supports generic PHYs\n");
+ hsotg->reset_phy_on_wake = false;
+ }
+
+ if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
+ retval = dwc2_hcd_init(hsotg);
+ if (retval) {
+ if (hsotg->gadget_enabled)
+ dwc2_hsotg_remove(hsotg);
+ goto error;
+ }
+ hsotg->hcd_enabled = 1;
+ }
+
+ platform_set_drvdata(dev, hsotg);
+ hsotg->hibernated = 0;
+
+ dwc2_debugfs_init(hsotg);
+
+ /* Gadget code manages lowlevel hw on its own */
+ if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
+ dwc2_lowlevel_hw_disable(hsotg);
+
+#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
+ IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
+ /* Postponed adding a new gadget to the udc class driver list */
+ if (hsotg->gadget_enabled) {
+ retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
+ if (retval) {
+ hsotg->gadget.udc = NULL;
+ dwc2_hsotg_remove(hsotg);
+ goto error;
+ }
+ }
+#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
+
+ hsotg->vbus_irq = platform_get_irq(dev, 1);
+ if (hsotg->vbus_irq < 0) {
+ dev_err(&dev->dev, "failed to get vbus irq\n");
+ retval = -ENXIO;
+ goto error;
+ }
+
+ retval = devm_request_threaded_irq(&dev->dev, hsotg->vbus_irq,
+ NULL, vbus_irq,
+ IRQF_ONESHOT | IRQF_NO_SUSPEND,
+ "asr-usb-vbus", hsotg);
+ if (retval) {
+ dev_info(&dev->dev,
+ "Can not request irq for VBUS\n");
+ goto error;
+ }
+ apmu_base = regs_addr_get_va(REGS_ADDR_APMU);
+ writel(readl(apmu_base + APMU_USB_WAKE_CLR) | USB_VBUS_WAKE_EN,
+ apmu_base + APMU_USB_WAKE_CLR);
+ writel(readl(apmu_base + APMU_USB_WAKE_CLR)
+ | (USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR | USB_ID_WAKE_CLR),
+ apmu_base + APMU_USB_WAKE_CLR);
+
+ device_init_wakeup(&dev->dev, 1);
+ pm_stay_awake(&dev->dev);
+ dev_info(hsotg->dev, "probe done\n");
+
+ return 0;
+
+error:
+ if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL)
+ dwc2_lowlevel_hw_disable(hsotg);
+ return retval;
+}
+
+static int __maybe_unused dwc2_suspend(struct device *dev)
+{
+ struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
+ bool is_device_mode = dwc2_is_device_mode(dwc2);
+ int ret = 0;
+
+ /* asr private */
+ return 0;
+
+ if (is_device_mode)
+ dwc2_hsotg_suspend(dwc2);
+
+ if (dwc2->ll_hw_enabled &&
+ (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
+ ret = __dwc2_lowlevel_hw_disable(dwc2);
+ dwc2->phy_off_for_suspend = true;
+ }
+
+ return ret;
+}
+
+static int __maybe_unused dwc2_resume(struct device *dev)
+{
+ struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
+ int ret = 0;
+
+ /* asr private */
+ return 0;
+
+ if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
+ ret = __dwc2_lowlevel_hw_enable(dwc2);
+ if (ret)
+ return ret;
+ }
+ dwc2->phy_off_for_suspend = false;
+
+ if (dwc2_is_device_mode(dwc2))
+ ret = dwc2_hsotg_resume(dwc2);
+
+ return ret;
+}
+
+static int dwc2_noirq_suspend(struct device *dev)
+{
+ struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
+ void __iomem *apmu_base = regs_addr_get_va(REGS_ADDR_APMU);
+
+ writel(readl(apmu_base + APMU_USB_WAKE_CLR)
+ | (USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR | USB_ID_WAKE_CLR
+ | USB_VBUS_WAKE_EN | USB_LINEST_WAKE_EN | USB_ID_WAKE_EN),
+ apmu_base + APMU_USB_WAKE_CLR);
+
+ if (dwc2->allow_suspend) {
+ if (dwc2->lx_state == DWC2_L2)
+ usb_phy_set_suspend2(dwc2->uphy, 1);
+ else
+ pr_info("dwc2 lx_state: %d\n", dwc2->lx_state);
+ }
+
+ enable_irq_wake(dwc2->vbus_irq);
+
+ dwc2_release_pm_qos();
+ return 0;
+}
+
+static int dwc2_noirq_resume(struct device *dev)
+{
+ volatile u32 value;
+ struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
+ void __iomem *apmu_base = regs_addr_get_va(REGS_ADDR_APMU);
+
+ if (dwc2->vbus_active)
+ dwc2_acquire_pm_qos();
+
+ disable_irq_wake(dwc2->vbus_irq);
+ if (dwc2->allow_suspend) {
+ if (dwc2->vbus_active) {
+ usb_phy_set_suspend2(dwc2->uphy, 0);
+ } else {
+ pr_info("dwc2 vbus off, lx_state: %d\n", dwc2->lx_state);
+ }
+ }
+
+ /* clear linestat wakeup and disable linestat/pmu wake en */
+ value = readl(apmu_base + APMU_USB_WAKE_CLR);
+ value |= (USB_LINEST_WAKE_CLR);
+ writel(value, apmu_base + APMU_USB_WAKE_CLR);
+ udelay(50);
+ value = readl(apmu_base + APMU_USB_WAKE_CLR);
+ value &= ~(USB_LINEST_WAKE_EN);
+ writel(value, apmu_base + APMU_USB_WAKE_CLR);
+
+ dev_info(dwc2->dev, "dwc2 resume\n");
+ return 0;
+}
+
+static const struct dev_pm_ops dwc2_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dwc2_noirq_suspend, dwc2_noirq_resume)
+};
+
+static struct platform_driver dwc2_platform_driver = {
+ .driver = {
+ .name = dwc2_driver_name,
+ .of_match_table = dwc2_of_match_table,
+ .pm = &dwc2_dev_pm_ops,
+ },
+ .probe = dwc2_driver_probe,
+ .remove = dwc2_driver_remove,
+ .shutdown = dwc2_driver_shutdown,
+};
+
+module_platform_driver(dwc2_platform_driver);
+
+MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
+MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
+MODULE_LICENSE("Dual BSD/GPL");