ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/linux/drivers/usb/dwc3/dwc3-asr-otg.c b/marvell/linux/drivers/usb/dwc3/dwc3-asr-otg.c
new file mode 100644
index 0000000..c1ce798
--- /dev/null
+++ b/marvell/linux/drivers/usb/dwc3/dwc3-asr-otg.c
@@ -0,0 +1,746 @@
+/*
+ * Base driver for ASR USB
+ *
+ * Copyright 2024 ASR Microelectronics Co., Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/platform_data/mv_usb.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <soc/asr/regs-addr.h>
+#include <linux/delay.h>
+#include <linux/cputype.h>
+#include <linux/usb/phy.h>
+#include <linux/usb.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/hcd.h>
+#include <linux/pm_qos.h>
+#include <linux/gpio.h>
+#include <linux/edge_wakeup_mmp.h>
+#include <linux/mutex.h>
+
+#include "core.h"
+
+#define ENNUM -1
+#define USB_HANDLE_TIME_MSEC (5000)
+#define VBUS_RISE_FALL_MS (10)
+
+#ifdef CONFIG_CPU_ASR1901
+#define APMU_USB_WAKE_CLR (0x07c)
+#define USB_WAKE_INT_EN (0x1 << 15)
+#define USB_WAKE_PMU_EN (0x1 << 14)
+
+#define USB_VBUS_WAKE_EN (0x1 << 10)
+#define USB_ID_WAKE_EN (0x1 << 12)
+#define USB_LINEST_WAKE_EN ((0x1 << 8) | (0x1 << 9))
+#define USB_RXELEC_WAKE_EN (0x1 << 11)
+
+#define USB_VBUS_WAKE_CLR (0x1 << 18)
+#define USB_ID_WAKE_CLR (0x1 << 20)
+#define USB_LINEST_WAKE_CLR ((0x1 << 16) | (0x1 << 17))
+#define USB_RXELEC_WAKE_CLR (0x1 << 19)
+#elif defined(CONFIG_CPU_ASR1903)
+#define APMU_USB_WAKE_CLR (0x07c)
+
+#define USB_WAKE_INT_EN (0x1 << 29)
+#define USB_WAKE_PMU_EN (0x1 << 29)
+
+#define USB_VBUS_WAKE_EN (0x1 << 11)
+#define USB_ID_WAKE_EN (0x1 << 22)
+#define USB_LINEST_WAKE_EN ((0x1 << 9) | (0x1 << 10))
+#define USB_RXELEC_WAKE_EN ((0x1 << 9) | (0x1 << 10))
+
+#define USB_VBUS_WAKE_CLR (0x1 << 4)
+#define USB_ID_WAKE_CLR (0x1 << 23)
+#define USB_LINEST_WAKE_CLR (0x1 << 7)
+#define USB_RXELEC_WAKE_CLR (0x1 << 7)
+#else
+#define APMU_USB_WAKE_CLR (0x07c)
+
+#define USB_WAKE_INT_EN (0x1 << 16)
+#define USB_WAKE_PMU_EN (0x1 << 16)
+
+#define USB_VBUS_WAKE_EN (0x1 << 11)
+#define USB_ID_WAKE_EN (0x1 << 12)
+#define USB_LINEST_WAKE_EN ((0x1 << 9) | (0x1 << 10))
+#define USB_RXELEC_WAKE_EN (0x1 << 28)
+
+#define USB_VBUS_WAKE_CLR (0x1 << 4)
+#define USB_ID_WAKE_CLR (0x1 << 23)
+#define USB_LINEST_WAKE_CLR (0x1 << 7)
+#define USB_RXELEC_WAKE_CLR (0x1 << 29)
+#endif
+
+struct dwc3_asr {
+ struct device *dev;
+ struct clk *usb_clk;
+ int vbus_irq;
+
+#ifdef CONFIG_DWC3_HWSULOG
+ int sulog_irq;
+#endif
+
+ int usbid_irq;
+ spinlock_t lock;
+ u32 usbid_gpio;
+ u32 edge_det_gpio;
+ u32 cur_usbid_val;
+ u32 cur_vbus_val;
+ int gpio_num;
+ int otg_state;
+
+ struct usb_gadget *gadget;
+ struct usb_hcd *hcd;
+ struct usb_hcd *shared_hcd;
+ struct dwc3 *dwc;
+
+ struct usb_phy *usb2_phy;
+ struct usb_phy *usb3_phy;
+ struct delayed_work otg_work;
+
+ struct pm_qos_request qos_idle;
+ s32 lpm_qos;
+ struct mutex mtx_lock;
+};
+
+extern void dwc3_release_pm_qos(void);
+extern void dwc3_release_pm_qos_timeout(u32 sec);
+extern void dwc3_acquire_pm_qos(void);
+extern void dwc3_acquire_wakeup_event(void);
+
+extern struct dwc3 *dwc3_get_controller(void);
+#ifdef CONFIG_DWC3_HWSULOG
+extern void dwc3_hwsulog_clear_int(void);
+#endif
+static u32 force_host = 0;
+static u32 force_dev = 0;
+static bool usb_host_vbus_on;
+static struct dwc3_asr *g_adwc;
+
+module_param(force_dev, uint, S_IRUGO|S_IWUSR);
+MODULE_PARM_DESC(force_dev, "dwc3 otg force device mode");
+
+module_param(force_host, uint, S_IRUGO|S_IWUSR);
+MODULE_PARM_DESC(force_host, "dwc3 otg force host mode");
+bool is_otg_host_vbus_on(void)
+{
+ return usb_host_vbus_on;
+}
+
+int usb_otg_set_vbus(struct dwc3_asr *adwc, bool on)
+{
+ int ret = 0;
+
+ usb_host_vbus_on = on;
+ if (adwc->gpio_num >= 0)
+ ret = gpio_direction_output(adwc->gpio_num , on);
+ return ret;
+}
+
+int usb_otg_set_host(struct usb_hcd *hcd, struct usb_hcd *shared_hcd)
+{
+ g_adwc->hcd = hcd;
+ g_adwc->shared_hcd = shared_hcd;
+ g_adwc->hcd->usb_phy = g_adwc->shared_hcd->usb_phy = g_adwc->usb2_phy;
+
+ return 0;
+}
+
+int usb_otg_set_peripheral(struct usb_gadget *gadget)
+{
+ g_adwc->gadget = gadget;
+
+ return 0;
+}
+
+int usb_otg_set_phy(struct usb_phy *usb2phy, struct usb_phy *usb3phy)
+{
+ g_adwc->usb2_phy = usb2phy;
+ g_adwc->usb3_phy = usb3phy;
+
+ return 0;
+}
+
+int usb_otg_set_controller(struct dwc3 *dwc)
+{
+ dwc->otg_state = g_adwc->otg_state;
+ g_adwc->dwc = dwc;
+
+ return 0;
+}
+
+static void dwc3_otg_start_host(struct dwc3_asr *adwc, int on)
+{
+ struct usb_hcd *hcd = g_adwc->hcd;
+ struct usb_hcd *shared_hcd = g_adwc->shared_hcd;
+
+ if (!hcd || !shared_hcd) {
+ dev_err(g_adwc->dev, "adwc->hcd is not set!\n");
+ return;
+ }
+
+ dev_info(g_adwc->dev, "%s host\n", on ? "start" : "stop");
+ adwc->dwc->otg_state = adwc->otg_state;
+
+ if (on) {
+ /* set constraint before turn on vbus */
+ pm_stay_awake(adwc->dev);
+ pm_qos_update_request(&adwc->qos_idle, adwc->lpm_qos);
+ dwc3_controller_reset(adwc->dwc);
+ usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
+ usb_add_hcd(shared_hcd, shared_hcd->irq, IRQF_SHARED);
+ } else {
+ usb_remove_hcd(shared_hcd);
+ usb_remove_hcd(hcd);
+ dwc3_controller_reset(adwc->dwc);
+ usb_phy_set_suspend(adwc->dwc->usb2_phy, 1);
+ usb_phy_set_suspend(adwc->dwc->usb3_phy, 1);
+ pm_qos_update_request(&adwc->qos_idle, PM_QOS_CPUIDLE_BLOCK_DEFAULT_VALUE);
+ pm_relax(adwc->dev);
+ }
+}
+
+static void dwc3_otg_start_peripherals(struct dwc3_asr *adwc, int on)
+{
+ struct usb_gadget *gadget = g_adwc->gadget;
+
+ if (!gadget) {
+ dev_err(g_adwc->dev, "adwc->gadget is not set!\n");
+ return;
+ }
+
+ dev_info(g_adwc->dev, "gadget %s\n", on ? "on" : "off");
+ adwc->dwc->otg_state = adwc->otg_state;
+ pm_wakeup_event(adwc->dev, USB_HANDLE_TIME_MSEC);
+ pm_qos_update_request_timeout(&adwc->qos_idle, adwc->lpm_qos, USB_HANDLE_TIME_MSEC * 1000);
+ if (on) {
+ /* dwc3_controller_reset(adwc->dwc); */
+ usb_gadget_vbus_connect(adwc->gadget);
+ } else {
+ usb_gadget_vbus_disconnect(adwc->gadget);
+ /* usb_phy_set_suspend(adwc->uphy, 1); */
+ }
+}
+
+static void usb_otg_work_fn(struct work_struct *work)
+{
+ int vbus, ret;
+ struct dwc3_asr *adwc = g_adwc;
+ int old_otg_state;
+
+ /* check ID and VBUS and update cable state */
+ if (adwc->usbid_gpio >= 0)
+ adwc->cur_usbid_val = gpio_get_value(adwc->usbid_gpio);
+ else
+ adwc->cur_usbid_val = 1;
+
+ mutex_lock(&adwc->mtx_lock);
+ ret = pxa_usb_extern_call(PXA_USB_DEV_OTG, vbus, get_vbus, &vbus);
+ if (ret) {
+ vbus = usb_phy_get_vbus(adwc->usb2_phy);
+ }
+ adwc->cur_vbus_val = vbus;
+
+ if (force_host)
+ adwc->cur_usbid_val = 0;
+ else if (force_dev)
+ adwc->cur_usbid_val = 1;
+
+ old_otg_state = adwc->otg_state;
+ pr_info("=>old_otg_state: %d, usbid: %d vbus: %d\n",
+ adwc->otg_state, adwc->cur_usbid_val, adwc->cur_vbus_val);
+
+ /* at first we clean states which are no longer active */
+ if (adwc->otg_state == OTG_STATE_B_IDLE) {
+ if (!adwc->cur_usbid_val) {
+ printk("disable vbus irq\n");
+ disable_irq(adwc->vbus_irq);
+ adwc->otg_state = OTG_STATE_A_HOST;
+ usb_phy_set_suspend(adwc->dwc->usb2_phy, 0);
+ usb_phy_set_suspend(adwc->dwc->usb3_phy, 0);
+ dwc3_otg_start_host(adwc, 1);
+ msleep(VBUS_RISE_FALL_MS);
+ usb_otg_set_vbus(adwc, true);
+ } else {
+ if (vbus)
+ adwc->otg_state = OTG_STATE_B_PERIPHERAL;
+ else
+ adwc->otg_state = OTG_STATE_B_IDLE;
+ dwc3_otg_start_peripherals(adwc, vbus);
+ }
+ } else if (adwc->otg_state == OTG_STATE_B_PERIPHERAL) {
+ if (!adwc->cur_vbus_val) {
+ adwc->otg_state = OTG_STATE_B_IDLE;
+ dwc3_otg_start_peripherals(adwc, 0);
+ }
+ } else if (adwc->otg_state == OTG_STATE_A_HOST) {
+ if (adwc->cur_usbid_val) {
+ adwc->otg_state = OTG_STATE_B_IDLE;
+ dwc3_otg_start_host(adwc, 0);
+ msleep(1);
+ usb_otg_set_vbus(adwc, false);
+ msleep(VBUS_RISE_FALL_MS);
+ /* usb_phy_set_suspend(adwc->dwc->usb2_phy, 1);
+ usb_phy_set_suspend(adwc->dwc->usb3_phy, 1); */
+ printk("enable vbus irq\n");
+ enable_irq(adwc->vbus_irq);
+ }
+ }
+ mutex_unlock(&adwc->mtx_lock);
+ pr_info("cur_otg_state: [%d->%d], usbid: %d vbus: %d\n",
+ old_otg_state, adwc->otg_state,
+ adwc->cur_usbid_val, adwc->cur_vbus_val);
+}
+
+static irqreturn_t vbus_irq(int irq, void *dev)
+{
+ struct dwc3_asr *adwc = (struct dwc3_asr *)dev;
+ void __iomem *apmu_base = regs_addr_get_va(REGS_ADDR_APMU);
+
+ dev_info(adwc->dev, "asr-usb vbus int enter..\n");
+#ifdef CONFIG_DWC3_HWSULOG
+ dwc3_hwsulog_clear_int();
+#endif
+
+ /* wait 50ms for vbus to be stable */
+ msleep(50);
+ if (cpu_is_asr1901() || cpu_is_asr1906())
+ writel(readl(apmu_base + APMU_USB_WAKE_CLR)
+ | USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR
+ | USB_ID_WAKE_CLR | USB_RXELEC_WAKE_CLR,
+ apmu_base + APMU_USB_WAKE_CLR);
+ else
+ writel(readl(apmu_base + APMU_USB_WAKE_CLR)
+ | (USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR | USB_RXELEC_WAKE_CLR
+ | USB_ID_WAKE_CLR | USB_WAKE_INT_EN),
+ apmu_base + APMU_USB_WAKE_CLR);
+
+ pm_wakeup_event(adwc->dev, USB_HANDLE_TIME_MSEC);
+ //pxa_usb_notify(PXA_USB_DEV_OTG, EVENT_VBUS, 0);
+ if (work_pending(&g_adwc->otg_work.work)) {
+ dev_info(adwc->dev, "cancel otg work...");
+ cancel_delayed_work_sync(&g_adwc->otg_work);
+ dev_info(adwc->dev, "done\n");
+ pm_wakeup_event(adwc->dev, USB_HANDLE_TIME_MSEC);
+ }
+ schedule_delayed_work(&g_adwc->otg_work, 0);
+ dev_info(adwc->dev, "asr-usb vbus interrupt is served..\n");
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t usbid_irq(int irq, void *dev_id)
+{
+ struct dwc3_asr *adwc = (struct dwc3_asr *)g_adwc;
+ dev_info(adwc->dev, "dwc3 usbid_irq is served..\n");
+ vbus_irq(irq, dev_id);
+ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_DWC3_HWSULOG
+static irqreturn_t sulog_irq_handler(int irq, void *dev)
+{
+ hwsulog_error_handler();
+
+ return IRQ_HANDLED;
+}
+#endif
+
+static void usbid_wakeup_handler(int gpio, void *data)
+{
+}
+
+static int usbid_irq_init(struct platform_device *pdev, struct dwc3_asr *adwc)
+{
+ int ret = -1;
+
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "usbid_gpio", &adwc->usbid_gpio);
+ pr_info("dwc3:usbid_gpio: %d\n", adwc->usbid_gpio);
+
+ if (ret) {
+ adwc->usbid_gpio = -1;
+ pr_err("%s no usbid-gpio defined\n", __func__);
+ return ret;
+ }
+
+ of_property_read_u32(pdev->dev.of_node,
+ "edge_detect_gpio", &adwc->edge_det_gpio);
+ if (adwc->edge_det_gpio > 0) {
+ ret = request_mfp_edge_wakeup(adwc->edge_det_gpio,
+ usbid_wakeup_handler,
+ NULL, &pdev->dev);
+ if (ret) {
+ dev_err(adwc->dev, "failed to request edge wakeup.\n");
+ goto out;
+ }
+ }
+
+ adwc->cur_usbid_val = gpio_get_value(adwc->usbid_gpio);
+ ret = gpio_request(adwc->usbid_gpio, "dwc3-usbid");
+ gpio_direction_input(adwc->usbid_gpio);
+
+ adwc->usbid_irq = gpio_to_irq(adwc->usbid_gpio);
+ ret =
+ request_threaded_irq(adwc->usbid_irq, NULL, usbid_irq,
+ IRQF_SHARED | IRQF_TRIGGER_RISING |
+ IRQF_TRIGGER_FALLING | IRQF_ONESHOT, "dwc3-usbid",
+ adwc);
+ if (ret < 0) {
+ dev_err(adwc->dev, "%s: request irq failed!\n",
+ __func__);
+ }
+
+out:
+ return ret;
+}
+
+static ssize_t otg_mode_store(struct device *pdev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct dwc3_asr *adwc = dev_get_drvdata(pdev);
+
+ mutex_lock(&adwc->mtx_lock);
+ if (!strncmp(buf, "host", 4)) {
+ if(adwc->otg_state == OTG_STATE_A_HOST) {
+ pr_err("already in host mode\n");
+ goto out;
+ }
+ disable_irq(adwc->vbus_irq);
+ pr_info("disable vbus irq\n");
+
+ if (adwc->otg_state == OTG_STATE_B_PERIPHERAL) {
+ adwc->otg_state = OTG_STATE_B_IDLE;
+ dwc3_otg_start_peripherals(adwc, 0);
+ }
+
+ if (adwc->otg_state == OTG_STATE_B_IDLE) {
+ force_host = 1;
+ force_dev = 0;
+ usb_otg_set_vbus(adwc, true);
+ msleep(VBUS_RISE_FALL_MS);
+ adwc->otg_state = OTG_STATE_A_HOST;
+ dwc3_otg_start_host(adwc, 1);
+ dev_info(pdev, "userspace set host: otg_mode: %d\n", adwc->otg_state);
+ }
+ } else if (!strncmp(buf, "device", 6)) {
+ if(adwc->otg_state == OTG_STATE_B_PERIPHERAL) {
+ pr_err("already in device mode\n");
+ goto out;
+ }
+
+ if (adwc->otg_state == OTG_STATE_A_HOST) {
+ adwc->otg_state = OTG_STATE_B_IDLE;
+ dwc3_otg_start_host(adwc, 0);
+ msleep(1);
+ usb_otg_set_vbus(adwc, false);
+ msleep(VBUS_RISE_FALL_MS);
+ }
+
+ if (adwc->otg_state == OTG_STATE_B_IDLE) {
+ force_host = 0;
+ force_dev = 1;
+ adwc->otg_state = OTG_STATE_B_PERIPHERAL;
+ dwc3_otg_start_peripherals(adwc, 1);
+ dev_info(pdev, "userspace set device: otg_mode: %d\n", adwc->otg_state);
+ }
+
+ enable_irq(adwc->vbus_irq);
+ pr_err("enable vbus irq\n");
+ } else {
+ force_host = 0;
+ force_dev = 0;
+ if (adwc->otg_state == OTG_STATE_B_PERIPHERAL) {
+ adwc->otg_state = OTG_STATE_B_IDLE;
+ dwc3_otg_start_peripherals(adwc, 0);
+ } else if (adwc->otg_state == OTG_STATE_A_HOST) {
+ adwc->otg_state = OTG_STATE_B_IDLE;
+ dwc3_otg_start_host(adwc, 0);
+ msleep(1);
+ usb_otg_set_vbus(adwc, false);
+ msleep(VBUS_RISE_FALL_MS);
+ printk("enable vbus irq\n");
+ enable_irq(adwc->vbus_irq);
+ } else {
+ dev_info(pdev, "already in idle none host/device mode: %d\n", adwc->otg_state);
+ }
+ }
+
+out:
+ mutex_unlock(&adwc->mtx_lock);
+
+ return count;
+}
+
+static ssize_t otg_mode_show(struct device *pdev, struct device_attribute *attr, char *buf)
+{
+ struct dwc3_asr *adwc = dev_get_drvdata(pdev);
+ char *host_dev_str;
+
+ if (adwc->otg_state == OTG_STATE_A_HOST)
+ host_dev_str = "host";
+ else if (adwc->otg_state == OTG_STATE_B_PERIPHERAL)
+ host_dev_str = "device";
+ else
+ host_dev_str = "idle";
+
+ return sprintf(buf, "otg_state:%d, otg mode: %s\n", adwc->otg_state, host_dev_str);
+}
+
+static DEVICE_ATTR(otg_mode, S_IWUSR |S_IRUGO, otg_mode_show, otg_mode_store);
+
+static int dwc3_asr_otg_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct dwc3_asr *adwc;
+ int ret;
+ void __iomem *apmu_base;
+ const __be32 *prop;
+ unsigned int proplen;
+ u32 data;
+
+ adwc = devm_kzalloc(&pdev->dev, sizeof(*adwc), GFP_KERNEL);
+ if (!adwc)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, adwc);
+
+ adwc->dev = &pdev->dev;
+ adwc->usb_clk = devm_clk_get(adwc->dev, NULL);
+ if (IS_ERR(adwc->usb_clk)) {
+ dev_err(adwc->dev, "failed to get core clock\n");
+ return PTR_ERR(adwc->usb_clk);
+ }
+
+ ret = clk_prepare_enable(adwc->usb_clk);
+ if (ret) {
+ dev_err(adwc->dev, "failed to enable core clock\n");
+ goto err_core;
+ }
+
+ adwc->vbus_irq = platform_get_irq(pdev, 0);
+ if (adwc->vbus_irq < 0) {
+ dev_err(&pdev->dev, "failed to get vbus irq\n");
+ ret = -ENXIO;
+ goto err_iface;
+ }
+
+ ret = devm_request_threaded_irq(&pdev->dev, adwc->vbus_irq,
+ NULL, vbus_irq,
+ IRQF_ONESHOT | IRQF_NO_SUSPEND,
+ "asr-usb-vbus", adwc);
+ if (ret) {
+ dev_info(&pdev->dev,
+ "Can not request irq for VBUS\n");
+ goto err_iface;
+ }
+
+#ifdef CONFIG_DWC3_HWSULOG
+ adwc->sulog_irq = platform_get_irq(pdev, 1);
+ if (adwc->sulog_irq < 0) {
+ dev_info(&pdev->dev, "no sulog irq\n");
+ } else {
+ ret = devm_request_threaded_irq(&pdev->dev, adwc->sulog_irq,
+ NULL, sulog_irq_handler,
+ IRQF_ONESHOT | IRQF_SHARED,
+ "dwc3-sulog-irq", adwc);
+ if (ret) {
+ dev_info(&pdev->dev,
+ "Can not request irq for dwc3 sulog %d\n", ret);
+ goto err_iface;
+ }
+ }
+#endif
+
+ usbid_irq_init(pdev, adwc);
+ INIT_DELAYED_WORK(&adwc->otg_work, usb_otg_work_fn);
+
+ if (of_property_read_bool(node , "otg,use-gpio-vbus")) {
+ if (of_property_read_u32(node , "gpio-num", &adwc->gpio_num)) {
+ adwc->gpio_num = ENNUM;
+ dev_info(&pdev->dev, "failed to find GPIO number in dts\n");
+ } else {
+ if (gpio_request(adwc->gpio_num, "OTGVBUS")) {
+ dev_err(&pdev->dev , "OTG Request GPIO failed, gpio: %d\n" ,
+ adwc->gpio_num);
+ adwc->gpio_num = ENNUM;
+ } else
+ gpio_direction_output(adwc->gpio_num , 0);
+ }
+ } else
+ adwc->gpio_num = ENNUM;
+
+ if (!of_property_read_u32(node, "otg-force-host-mode", &data)) {
+ dev_info(&pdev->dev, "otg force host mode\n");
+ force_host = 1;
+ force_dev = 0;
+ } else if (!of_property_read_u32(node, "otg-force-dev-mode", &data)) {
+ dev_info(&pdev->dev, "otg force dev mode\n");
+ force_dev = 1;
+ force_host = 0;
+ }
+
+ prop = of_get_property(node, "lpm-qos", &proplen);
+ if (!prop) {
+ pr_err("lpm-qos for dwc otg is not defined\n");
+ goto err_iface;
+ } else
+ adwc->lpm_qos = be32_to_cpup(prop);
+
+ adwc->qos_idle.name = "dwc3-otg";
+ pm_qos_add_request(&adwc->qos_idle, PM_QOS_CPUIDLE_BLOCK,
+ PM_QOS_CPUIDLE_BLOCK_DEFAULT_VALUE);
+
+ platform_set_drvdata(pdev, adwc);
+ device_init_wakeup(&pdev->dev, 1);
+ g_adwc = adwc;
+ ret = of_platform_populate(node, NULL, NULL, adwc->dev);
+ if (ret) {
+ dev_err(adwc->dev, "failed to register core - %d\n", ret);
+ goto err_iface;
+ }
+
+ schedule_delayed_work(&g_adwc->otg_work, HZ);
+ adwc->otg_state = OTG_STATE_B_IDLE;
+ mutex_init(&adwc->mtx_lock);
+ ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_otg_mode.attr);
+ if(ret){
+ dev_err(&pdev->dev, "create host_dev mode failed");
+ goto err_iface;
+ }
+
+ apmu_base = regs_addr_get_va(REGS_ADDR_APMU);
+ writel(readl(apmu_base + APMU_USB_WAKE_CLR)
+ | (USB_WAKE_INT_EN | USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR | USB_ID_WAKE_CLR),
+ apmu_base + APMU_USB_WAKE_CLR);
+ writel(readl(apmu_base + APMU_USB_WAKE_CLR) | USB_WAKE_INT_EN | USB_VBUS_WAKE_EN,
+ apmu_base + APMU_USB_WAKE_CLR);
+ dev_info(&pdev->dev, "%s done\n", __func__);
+
+ return 0;
+
+err_iface:
+ clk_disable_unprepare(adwc->usb_clk);
+err_core:
+ return ret;
+}
+
+static int dwc3_asr_otg_remove(struct platform_device *pdev)
+{
+ struct dwc3_asr *adwc = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(adwc->usb_clk);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int dwc3_asr_suspend_noirq(struct device *dev)
+{
+ struct dwc3_asr *adwc = dev_get_drvdata(dev);
+ void __iomem *apmu_base = regs_addr_get_va(REGS_ADDR_APMU);
+ struct dwc3 *dwc = dwc3_get_controller();
+
+ writel(readl(apmu_base + APMU_USB_WAKE_CLR)
+ | (USB_WAKE_INT_EN | USB_WAKE_PMU_EN
+ | USB_LINEST_WAKE_EN | USB_ID_WAKE_EN | USB_RXELEC_WAKE_EN
+ | USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR
+ | USB_ID_WAKE_CLR | USB_RXELEC_WAKE_CLR),
+ apmu_base + APMU_USB_WAKE_CLR);
+
+ if (dwc->allow_suspend) {
+ if (dwc->link_state == DWC3_LINK_STATE_U3)
+ usb_phy_set_suspend2(dwc->usb2_phy, 1);
+ else
+ pr_info("dwc3 linkst: %d\n", dwc->link_state);
+ }
+
+ enable_irq_wake(adwc->vbus_irq);
+
+ dwc3_release_pm_qos();
+ return 0;
+}
+
+static int dwc3_asr_resume_noirq(struct device *dev)
+{
+ volatile u32 value;
+ void __iomem *apmu_base = regs_addr_get_va(REGS_ADDR_APMU);
+ struct dwc3_asr *adwc = dev_get_drvdata(dev);
+ struct dwc3 *dwc = dwc3_get_controller();
+
+ if (dwc->allow_suspend) {
+ if (dwc->vbus_active) {
+ dwc3_acquire_pm_qos();
+ usb_phy_set_suspend2(dwc->usb2_phy, 0);
+ } else {
+ pr_info("dwc3 vbus off, linkst: %d\n", dwc->link_state);
+ }
+ }
+
+ /* clear linestat wakeup and disable linestat/pmu wake en */
+ value = readl(apmu_base + APMU_USB_WAKE_CLR);
+ value |= (USB_WAKE_INT_EN | USB_LINEST_WAKE_CLR | USB_RXELEC_WAKE_CLR);
+ writel(value, apmu_base + APMU_USB_WAKE_CLR);
+ udelay(50);
+
+ value = readl(apmu_base + APMU_USB_WAKE_CLR);
+ value &= ~(USB_WAKE_PMU_EN | USB_LINEST_WAKE_EN | USB_RXELEC_WAKE_EN);
+ value |= (USB_VBUS_WAKE_EN | USB_ID_WAKE_EN | USB_WAKE_INT_EN);
+ writel(value, apmu_base + APMU_USB_WAKE_CLR);
+
+ disable_irq_wake(adwc->vbus_irq);
+ return 0;
+}
+
+static const struct dev_pm_ops dwc3_asr_pm_ops = {
+ .suspend_noirq = dwc3_asr_suspend_noirq,
+ .resume_noirq = dwc3_asr_resume_noirq,
+};
+#endif
+
+static const struct of_device_id of_dwc3_match[] = {
+ { .compatible = "asr,dwc3" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_dwc3_match);
+
+static struct platform_driver dwc3_asr_driver = {
+ .probe = dwc3_asr_otg_probe,
+ .remove = dwc3_asr_otg_remove,
+ .driver = {
+ .name = "asr-dwc3",
+ .of_match_table = of_dwc3_match,
+#ifdef CONFIG_PM_SLEEP
+ .pm = &dwc3_asr_pm_ops,
+#endif
+ },
+};
+
+module_platform_driver(dwc3_asr_driver);
+
+MODULE_ALIAS("platform:asr-dwc3");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("ASR USB Glue Layer");