ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/linux/include/soc/asr/addr-map.h b/marvell/linux/include/soc/asr/addr-map.h
new file mode 100644
index 0000000..2ff13d4
--- /dev/null
+++ b/marvell/linux/include/soc/asr/addr-map.h
@@ -0,0 +1,104 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/addr-map.h
+ *
+ * Common address map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ADDR_MAP_H
+#define __ASM_MACH_ADDR_MAP_H
+
+/* APB - Application Subsystem Peripheral Bus
+ *
+ * NOTE: the DMA controller registers are actually on the AXI fabric #1
+ * slave port to AHB/APB bridge, due to its close relationship to those
+ * peripherals on APB, let's count it into the ABP mapping area.
+ */
+#define APB_PHYS_BASE 0xd4000000
+#define APB_VIRT_BASE IOMEM(0xfe000000)
+
+#ifdef CONFIG_CPU_PXA1986
+#define APB_PHYS_SIZE 0x00a00000
+#else
+#define APB_PHYS_SIZE 0x00200000
+#endif
+
+#define AXI_PHYS_BASE 0xd4200000
+#define AXI_VIRT_BASE IOMEM(APB_VIRT_BASE + APB_PHYS_SIZE)
+#define AXI_PHYS_SIZE 0x00200000
+
+#ifdef CONFIG_CPU_ASR18XX
+#define DMCU_PHYS_BASE 0xc0100000
+#define DMCU_VIRT_BASE IOMEM(0xfe500000)
+#define DMCU_PHYS_SIZE 0x00010000
+#endif
+
+#ifdef CONFIG_CPU_ASR1901
+#define DMCU_PHYS_BASE 0xc0000000
+#define DMCU_VIRT_BASE IOMEM(0xfe500000)
+#define DMCU_PHYS_SIZE 0x00010000
+#endif
+
+#if defined(CONFIG_CPU_PXA1928)
+#define DMCU_PHYS_BASE 0xd0000000
+#define DMCU_VIRT_BASE IOMEM(0xfe500000)
+#define DMCU_PHYS_SIZE 0x00010000
+#endif
+
+#if defined(CONFIG_CPU_PXA1986)
+#define MMP_CORE_PERIPH_PHYS_BASE 0xd0020000
+#define MMP_CORE_PERIPH_PHYS_SIZE 0x0000a000
+#else
+#define MMP_CORE_PERIPH_PHYS_BASE 0xd1dfe000
+#define MMP_CORE_PERIPH_PHYS_SIZE 0x00002000
+#endif
+
+#define MMP_CORE_PERIPH_VIRT_BASE IOMEM(AXI_VIRT_BASE + AXI_PHYS_SIZE)
+
+/* Static Memory Controller - Chip Select 0 and 1 */
+#define SMC_CS0_PHYS_BASE 0x80000000
+#define SMC_CS0_PHYS_SIZE 0x10000000
+#define SMC_CS1_PHYS_BASE 0x90000000
+#define SMC_CS1_PHYS_SIZE 0x10000000
+
+/*
+ * below definition is used in pxa1928-dt.c, and will be removed
+ * after pxa1928-Zx stepping is not supported.
+ */
+#define AUD_PHYS_BASE 0xc0ffd800
+
+#define AUD_PHYS_BASE2 0xc0140000
+
+/* audio MAP base */
+#define AUD_MAP_BASE 0xd1200000
+#define AUD_AUX_BASE 0xd1230000
+
+#ifdef CONFIG_CPU_PXA1986
+#define APMU_VIRT_BASE (APB_VIRT_BASE + 0x80000)
+#else
+#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800)
+#endif
+#define APMU_REG(x) IOMEM(APMU_VIRT_BASE + (x))
+
+#define APMU_PHY_BASE (AXI_PHYS_BASE + 0x82800)
+
+#define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000)
+#define APBC_REG(x) (APBC_VIRT_BASE + (x))
+#define APBCP_REG(x) (APBC_VIRT_BASE + (x) + 0x03b000)
+
+#define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000)
+#define MPMU_REG(x) (MPMU_VIRT_BASE + (x))
+
+#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00)
+#define CIU_REG(x) (CIU_VIRT_BASE + (x))
+
+#define SCU_VIRT_BASE (MMP_CORE_PERIPH_VIRT_BASE)
+
+#define GIC_DIST_VIRT_BASE (MMP_CORE_PERIPH_VIRT_BASE + 0x1000)
+#define GIC_DIST_PHYS_BASE (MMP_CORE_PERIPH_PHYS_BASE + 0x1000)
+
+
+#endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/marvell/linux/include/soc/asr/asr18xx_lowpower.h b/marvell/linux/include/soc/asr/asr18xx_lowpower.h
new file mode 100644
index 0000000..966cc5e
--- /dev/null
+++ b/marvell/linux/include/soc/asr/asr18xx_lowpower.h
@@ -0,0 +1,162 @@
+/*
+ * include/soc/asr/asr18xx_lowpower.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MMP_MACH_PXA182X_LOWPOWER_H__
+#define __MMP_MACH_PXA182X_LOWPOWER_H__
+
+/* APMU regs offset */
+/* Core IDLE configuration */
+#define CORE0_IDLE 0x124
+#define CORE1_IDLE 0x128
+#define CORE2_IDLE 0x160
+#define CORE3_IDLE 0x164
+
+/* MP IDLE configuration */
+#define MP_CFG0 0x120
+#define MP_CFG1 0x0e4
+#define MP_CFG2 0x150
+#define MP_CFG3 0x154
+
+#define STBL_TIMER 0x084
+#define DEBUG_REG 0x088
+
+/* MPMU regs offset */
+#define CPCR 0x0
+#define CWUCRS 0x0048
+#define CWUCRM 0x004c
+#define APCR 0x1000
+#ifdef CONFIG_CPU_ASR18XX
+#define PM_STATUS 0x1058
+#else
+#define PM_STATUS 0x1030
+#endif
+#define AWUCRS 0x1048
+#define AWUCRM 0x104c
+/* ICU regs offset */
+#define CORE0_CA9_GLB_INT_MASK 0x114
+#define CORE1_CA9_GLB_INT_MASK 0x144
+
+#define CORE0_CA7_GLB_INT_MASK 0x228
+#define CORE1_CA7_GLB_INT_MASK 0x238
+#define CORE2_CA7_GLB_INT_MASK 0x248
+#define CORE3_CA7_GLB_INT_MASK 0x258
+
+/* bits definition */
+#define PMUA_CORE_IDLE (1 << 0)
+#define PMUA_CORE_POWER_DOWN (1 << 1)
+#define PMUA_CORE_L1_SRAM_POWER_DOWN (1 << 2)
+#define PMUA_GIC_IRQ_GLOBAL_MASK (1 << 3)
+#define PMUA_GIC_FIQ_GLOBAL_MASK (1 << 4)
+
+#define PMUA_MP_IDLE (1 << 0)
+#define PMUA_MP_POWER_DOWN (1 << 1)
+#define PMUA_MP_L2_SRAM_POWER_DOWN (1 << 2)
+#define PMUA_MP_SCU_SRAM_POWER_DOWN (1 << 3)
+#define PMUA_MP_MASK_CLK_OFF (1 << 11)
+#define PMUA_DIS_MP_SLP (1 << 18)
+
+#define AP_GBL_IRQ_MASK_CLR_DIS (1 << 30)
+
+#define ICU_MASK_FIQ (1 << 0)
+#define ICU_MASK_IRQ (1 << 1)
+
+#define PMUM_AXISD (1 << 31)
+#define PMUM_DSPSD (1 << 30)
+#define PMUM_SLPEN (1 << 29)
+#define PMUM_DTCMSD (1 << 28)
+#define PMUM_DDRCORSD (1 << 27)
+#define PMUM_APBSD (1 << 26)
+#define PMUM_BBSD (1 << 25)
+#define PMUM_INTCLR (1 << 24)
+#define PMUM_SLPWP0 (1 << 23)
+#define PMUM_SLPWP1 (1 << 22)
+#define PMUM_SLPWP2 (1 << 21)
+#define PMUM_SLPWP3 (1 << 20)
+#define PMUM_VCTCXOSD (1 << 19)
+#define PMUM_SLPWP4 (1 << 18)
+#define PMUM_SLPWP5 (1 << 17)
+#define PMUM_SLPWP6 (1 << 16)
+#define PMUM_SLPWP7 (1 << 15)
+#define PMUM_MSASLPEN (1 << 14)
+#define PMUM_STBYEN (1 << 13)
+#define PMUM_SPDTCMSD (1 << 12)
+#define PMUM_LDMA_MASK (1 << 3)
+
+#define PMUM_GSM_WAKEUPWMX (1 << 29)
+#define PMUM_WCDMA_WAKEUPX (1 << 28)
+#define PMUM_GSM_WAKEUPWM (1 << 27)
+#define PMUM_WCDMA_WAKEUPWM (1 << 26)
+#define PMUM_AP_ASYNC_INT (1 << 25)
+#define PMUM_AP_FULL_IDLE (1 << 24)
+#define PMUM_SQU_SDH1 (1 << 23)
+#define PMUM_SDH_23 (1 << 22)
+#define PMUM_KEYPRESS (1 << 21)
+#define PMUM_TRACKBALL (1 << 20)
+#define PMUM_NEWROTARY (1 << 19)
+#define PMUM_WDT (1 << 18)
+#define PMUM_RTC_ALARM (1 << 17)
+#define PMUM_CP_TIMER_3 (1 << 16)
+#define PMUM_CP_TIMER_2 (1 << 15)
+#define PMUM_CP_TIMER_1 (1 << 14)
+#define PMUM_AP1_TIMER_3 (1 << 13)
+#define PMUM_AP1_TIMER_2 (1 << 12)
+#define PMUM_AP1_TIMER_1 (1 << 11)
+#define PMUM_AP0_2_TIMER_3 (1 << 10)
+#define PMUM_AP0_2_TIMER_2 (1 << 9)
+#define PMUM_AP0_2_TIMER_1 (1 << 8)
+#define PMUM_WAKEUP7 (1 << 7)
+#define PMUM_WAKEUP6 (1 << 6)
+#define PMUM_WAKEUP5 (1 << 5)
+#define PMUM_WAKEUP4 (1 << 4)
+#define PMUM_WAKEUP3 (1 << 3)
+#define PMUM_WAKEUP2 (1 << 2)
+#define PMUM_WAKEUP1 (1 << 1)
+#define PMUM_WAKEUP0 (1 << 0)
+#define PMUM_AP_WAKEUP_MASK (0xFFFFFFFF & ~(PMUM_GSM_WAKEUPWM | PMUM_WCDMA_WAKEUPWM))
+
+#ifndef __ASSEMBLER__
+
+enum asr18xx_lowpower_state {
+ POWER_MODE_CORE_INTIDLE, /* used for C1 */
+ POWER_MODE_CORE_POWERDOWN, /* used for C2 */
+ POWER_MODE_APPS_IDLE, /* used for D1P */
+ POWER_MODE_SYS_SLEEP, /* used for non-udr chip sleep, D1 */
+ /* POWER_MODE_UDR_VCTCXO, */ /* used for udr with vctcxo, D2 */
+ POWER_MODE_UDR, /* used for udr D2, suspend */
+ POWER_MODE_MAX = 15, /* maximum lowpower states */
+};
+
+struct mfpr_udr_cfg {
+ u32 offset;
+ u32 value;
+ u32 restore;
+};
+
+#define MAX_MFPR_UDR_CFG_NUM 256 /* big enough for ASR SoCs */
+
+extern void __iomem *scu_get_base_addr(void);
+extern void __iomem *icu_get_base_addr(void);
+extern void ca7_power_up_setup(unsigned int);
+#ifdef CONFIG_CPU_ASR18XX
+extern void pxa18xx_lowpower_config(u32 power_state, u32 lowpower_enable);
+extern void asr18xx_set_pmu(u32 cpu, u32 power_mode);
+extern void asr18xx_clr_pmu(u32 cpu);
+extern void asr18xx_restore_wakeup(void);
+extern void asr18xx_save_wakeup(void);
+#ifdef CONFIG_PCIE_NZ3
+extern bool pcie_nz3_initialized(void);
+#endif
+#ifdef CONFIG_PCIE_ASR1803
+extern int falcon_pcie_device(void);
+#endif
+#endif
+#endif
+#ifdef CONFIG_CPU_ASR18XX
+extern bool asr1802s_is_a2plus(void);
+#endif
+#endif
diff --git a/marvell/linux/include/soc/asr/asr1901_lowpower.h b/marvell/linux/include/soc/asr/asr1901_lowpower.h
new file mode 100644
index 0000000..2967401
--- /dev/null
+++ b/marvell/linux/include/soc/asr/asr1901_lowpower.h
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __MMP_MACH_ASR1901_LOWPOWER_H__
+#define __MMP_MACH_ASR1901_LOWPOWER_H__
+
+/* APMU regs offset */
+/* Core IDLE configuration */
+#define CORE0_IDLE 0x124
+#define CORE1_IDLE 0x128
+#define CORE2_IDLE 0x160
+#define CORE3_IDLE 0x164
+
+/* MP IDLE configuration */
+#define MP_CFG0 0x120
+#define MP_CFG1 0x0e4
+#define MP_CFG2 0x150
+#define MP_CFG3 0x154
+
+#define CORE_STATUS 0x90
+
+#define STBL_TIMER 0x084
+/* MPMU regs offset */
+#define CPCR 0x0
+#define CWUCRS 0x0048
+#define CWUCRM 0x004c
+#define APCR_C0 0x1090
+#define APCR_C1 0x1094
+#define APCR_PER 0x1098
+#define APCR_C2 0x109C
+#define APSLPW 0x1000
+
+#define PM_STATUS 0x1030
+#define AWUCRS 0x1048
+#define AWUCRM 0x104c
+/* ICU regs offset */
+#define CORE0_CA9_GLB_INT_MASK 0x114
+#define CORE1_CA9_GLB_INT_MASK 0x144
+
+#define CORE0_CA7_GLB_INT_MASK 0x228
+#define CORE1_CA7_GLB_INT_MASK 0x238
+#define CORE2_CA7_GLB_INT_MASK 0x248
+#define CORE3_CA7_GLB_INT_MASK 0x258
+
+/* bits definition */
+#define PMUA_CORE_IDLE (1 << 0)
+#define PMUA_CORE_POWER_DOWN (1 << 1)
+#define PMUA_CORE_L1_SRAM_POWER_DOWN (1 << 2)
+#define PMUA_GIC_IRQ_GLOBAL_MASK (1 << 3)
+#define PMUA_GIC_FIQ_GLOBAL_MASK (1 << 4)
+
+#define PMUA_MP_IDLE (1 << 0)
+#define PMUA_MP_POWER_DOWN (1 << 1)
+#define PMUA_MP_L2_SRAM_POWER_DOWN (1 << 2)
+#define PMUA_MP_SCU_SRAM_POWER_DOWN (1 << 3)
+#define PMUA_MP_MASK_CLK_OFF (1 << 11)
+#define PMUA_DIS_MP_SLP (1 << 18)
+
+#define INT_MASK_FIQ (1 << 3)
+#define INT_MASK_IRQ (1 << 4)
+
+#define PMUM_AXISD (1 << 31)
+#define PMUM_DSPSD (1 << 30)
+#define PMUM_SLPEN (1 << 29)
+#define PMUM_DTCMSD (1 << 28)
+#define PMUM_DDRCORSD (1 << 27)
+#define PMUM_APBSD (1 << 26)
+#define PMUM_BBSD (1 << 25)
+#define PMUM_INTCLR (1 << 24)
+#define PMUM_SLPWP0 (1 << 23)
+#define PMUM_SLPWP1 (1 << 22)
+#define PMUM_SLPWP2 (1 << 21)
+#define PMUM_SLPWP3 (1 << 20)
+#define PMUM_VCTCXOSD (1 << 19)
+#define PMUM_SLPWP4 (1 << 18)
+#define PMUM_SLPWP5 (1 << 17)
+#define PMUM_SLPWP6 (1 << 16)
+#define PMUM_SLPWP7 (1 << 15)
+#define PMUM_MSASLPEN (1 << 14)
+#define PMUM_STBYEN (1 << 13)
+#define PMUM_SPDTCMSD (1 << 12)
+#define PMUM_LDMA_MASK (1 << 3)
+
+#define PMUM_GSM_WAKEUPWMX (1 << 29)
+#define PMUM_WCDMA_WAKEUPX (1 << 28)
+#define PMUM_GSM_WAKEUPWM (1 << 27)
+#define PMUM_WCDMA_WAKEUPWM (1 << 26)
+#define PMUM_AP_ASYNC_INT (1 << 25)
+#define PMUM_AP_FULL_IDLE (1 << 24)
+#define PMUM_SQU_SDH1 (1 << 23)
+#define PMUM_SDH_23 (1 << 22)
+#define PMUM_KEYPRESS (1 << 21)
+#define PMUM_TRACKBALL (1 << 20)
+#define PMUM_NEWROTARY (1 << 19)
+#define PMUM_WDT (1 << 18)
+#define PMUM_RTC_ALARM (1 << 17)
+#define PMUM_CP_TIMER_3 (1 << 16)
+#define PMUM_CP_TIMER_2 (1 << 15)
+#define PMUM_CP_TIMER_1 (1 << 14)
+#define PMUM_AP1_TIMER_3 (1 << 13)
+#define PMUM_AP1_TIMER_2 (1 << 12)
+#define PMUM_AP1_TIMER_1 (1 << 11)
+#define PMUM_AP0_2_TIMER_3 (1 << 10)
+#define PMUM_AP0_2_TIMER_2 (1 << 9)
+#define PMUM_AP0_2_TIMER_1 (1 << 8)
+#define PMUM_WAKEUP7 (1 << 7)
+#define PMUM_WAKEUP6 (1 << 6)
+#define PMUM_WAKEUP5 (1 << 5)
+#define PMUM_WAKEUP4 (1 << 4)
+#define PMUM_WAKEUP3 (1 << 3)
+#define PMUM_WAKEUP2 (1 << 2)
+#define PMUM_WAKEUP1 (1 << 1)
+#define PMUM_WAKEUP0 (1 << 0)
+#define PMUM_AP_WAKEUP_MASK (0xFFFFFFFF & ~(PMUM_GSM_WAKEUPWM | PMUM_WCDMA_WAKEUPWM))
+
+#ifndef __ASSEMBLER__
+
+enum asr1901_lowpower_state {
+ POWER_MODE_CORE_INTIDLE, /* used for C1 */
+ POWER_MODE_CORE_POWERDOWN, /* used for C2 */
+ POWER_MODE_APPS_IDLE, /* used for D1P */
+ POWER_MODE_SYS_SLEEP, /* used for non-udr chip sleep, D1 */
+ /* POWER_MODE_UDR_VCTCXO, */ /* used for udr with vctcxo, D2 */
+ POWER_MODE_UDR, /* used for udr D2, suspend */
+ POWER_MODE_MAX = 15, /* maximum lowpower states */
+};
+
+struct mfpr_udr_cfg {
+ u32 offset;
+ u32 value;
+ u32 restore;
+};
+
+#define MAX_MFPR_UDR_CFG_NUM 256 /* big enough for ASR SoCs */
+
+extern void __iomem *scu_get_base_addr(void);
+extern void __iomem *icu_get_base_addr(void);
+extern void ca9_power_up_setup(unsigned int arg);
+extern void ca7_power_up_setup(unsigned int arg);
+#if defined(CONFIG_CPU_ASR18XX) || defined(CONFIG_CPU_ASR1901)
+extern void asr18xx_lowpower_config(u32 power_state, u32 lowpower_enable);
+extern void asr18xx_set_pmu(u32 cpu, u32 power_mode);
+extern void asr18xx_clr_pmu(u32 cpu);
+extern void asr18xx_restore_wakeup(void);
+extern void asr18xx_save_wakeup(void);
+
+#endif
+#endif
+extern u32 uart_is_wake_from_d1pp(void);
+#endif
diff --git a/marvell/linux/include/soc/asr/asr_mflag.h b/marvell/linux/include/soc/asr/asr_mflag.h
new file mode 100644
index 0000000..a68541c
--- /dev/null
+++ b/marvell/linux/include/soc/asr/asr_mflag.h
@@ -0,0 +1,31 @@
+/*
+ * include/soc/asr/asr_mflag.h
+ *
+ */
+#ifndef __ASR_MFLAG_H__
+#define __ASR_MFLAG_H__
+
+#include <linux/kernel.h>
+
+#define ASR_MFLAG_OFFSET_FROM_CRASHKERNEL (0x300)
+
+#define AP_DIAG_BUF_SET_MAGIC (0x41504447) /* APDG */
+#define AP_DIAG_BUF_SET_MAGIC2 (0x41504467) /* APDg */
+
+/* resever a 128 bytes(0x300 to 0x380) structure to save asr memory flags */
+struct asr_mflag {
+ u32 reserved1[0x28 / sizeof(u32)];
+
+ u32 diag_buff_magic;
+ u32 diag_buff_addr;
+ u32 diag_buff_len;
+
+ u32 fastboot_flag; /* fast boot mode flag, offset 0x34 */
+ u32 ubifs_error_magic; /* ubifs error magic offset 0x38 */
+ u32 ubifs_error_type; /* ubifs error magic offset 0x3c */
+ u32 reserved2[0x40 / sizeof(u32)];
+} __attribute__ ((__packed__));
+
+extern struct asr_mflag * get_asr_mflag(void);
+#endif
+
diff --git a/marvell/linux/include/soc/asr/asrcpdvc.h b/marvell/linux/include/soc/asr/asrcpdvc.h
new file mode 100644
index 0000000..e88092d
--- /dev/null
+++ b/marvell/linux/include/soc/asr/asrcpdvc.h
@@ -0,0 +1,31 @@
+#ifndef __ASR_CPDVC_H
+#define __ASR_CPDVC_H
+
+
+#define MAX_CP_PPNUM 5
+
+struct cpdvc_info {
+ unsigned int cpfreq; /* Mhz */
+ unsigned int cpvl; /* range from 0~7/0~15 */
+};
+
+struct cpmsa_dvc_info {
+ struct cpdvc_info cpdvcinfo[MAX_CP_PPNUM]; /* we only use four CP PPs now as max */
+ struct cpdvc_info cpaxidvcinfo[MAX_CP_PPNUM];
+ struct cpdvc_info lteaxidvcinfo[MAX_CP_PPNUM];
+ struct cpdvc_info msadvcvl[MAX_CP_PPNUM];
+};
+
+struct ddr_dfc_info {
+ unsigned int ddr_idle;
+ unsigned int ddr_active;
+ unsigned int ddr_high;
+};
+
+extern int fillddrdfcinfo(struct ddr_dfc_info *dfc_info);
+extern int getddrdfcinfo(struct ddr_dfc_info *dfc_info);
+
+extern int fillcpdvcinfo(struct cpmsa_dvc_info *dvc_info);
+extern int getcpdvcinfo(struct cpmsa_dvc_info *dvc_info);
+
+#endif
diff --git a/marvell/linux/include/soc/asr/asrdcstat.h b/marvell/linux/include/soc/asr/asrdcstat.h
new file mode 100644
index 0000000..fdba66c
--- /dev/null
+++ b/marvell/linux/include/soc/asr/asrdcstat.h
@@ -0,0 +1,276 @@
+#ifndef __ASRDCSTAT_H
+#define __ASRDCSTAT_H
+
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+//TODO #include <linux/clk/dvfs-dvc.h>
+#include <linux/fs.h>
+#include <linux/time.h>
+//TODO #include <asm/cputime.h>
+#include <asm/div64.h>
+#include <linux/kernel_stat.h>
+#include <linux/tick.h>
+
+enum lowpower_mode {
+ LPM_C1,
+ LPM_C2,
+#ifdef CONFIG_ARM64
+ LPM_MP2,
+#endif
+ LPM_D1P,
+ LPM_D1,
+ LPM_D2,
+ LPM_D2_UDR,
+ MAX_LPM_INDEX = 15,
+};
+
+#define MAX_BREAKDOWN_TIME 11
+/* use the largest possible number is 10 */
+#define MAX_LPM_INDEX_DC 10
+
+struct op_dcstat_info {
+ unsigned int ppindex;
+ unsigned long pprate;
+ struct timespec64 prev_ts;
+
+ u64 clk_idle_time; /* ns */
+ u64 clk_busy_time; /* ns */
+ u64 pwr_off_time; /* ns */
+
+ /* used for ddr ticks ratio */
+ long ddr_glob_ratio;
+ long ddr_idle_ratio;
+ long ddr_busy_ratio;
+ long ddr_data_ratio;
+ long ddr_util_ratio;
+
+};
+
+struct clk_dc_stat_info {
+ bool stat_start;
+ struct op_dcstat_info *ops_dcstat;
+ u32 power_mode;
+ unsigned int ops_stat_size;
+ unsigned int curopindex;
+ unsigned int idle_flag;
+ unsigned int online;
+ u64 C1_idle_start;
+ u64 C1_idle_end;
+ u64 C1_op_total[MAX_LPM_INDEX_DC];
+ int C1_op_index;
+ u64 C1_count[MAX_LPM_INDEX_DC];
+ u64 C2_idle_start;
+ u64 C2_idle_end;
+ u64 C2_op_total[MAX_LPM_INDEX_DC];
+ int C2_op_index;
+ u64 C2_count[MAX_LPM_INDEX_DC];
+ u64 breakdown_start;
+ u64 breakdown_end;
+ u64 breakdown_time_total[MAX_BREAKDOWN_TIME+1];
+ u64 breakdown_time_count[MAX_BREAKDOWN_TIME+1];
+ u64 runtime_start;
+ u64 runtime_end;
+ u64 runtime_op_total[MAX_LPM_INDEX_DC];
+ u64 idle_op_total[MAX_LPM_INDEX_DC];
+ int runtime_op_index;
+};
+
+struct clk_dcstat {
+ struct clk *clk;
+ struct clk_dc_stat_info clk_dcstat;
+ struct list_head node;
+ struct notifier_block nb;
+};
+
+struct core_dcstat {
+ struct clk *clk;
+ int cpu_num;
+ int *cpu_id;
+ struct list_head node;
+};
+
+
+enum clk_stat_msg {
+ CLK_STAT_START = 0,
+ CLK_STAT_STOP,
+ CLK_STATE_ON,
+ CLK_STATE_OFF,
+ CLK_RATE_CHANGE,
+ PWR_ON,
+ PWR_OFF,
+ CLK_DYNVOL_CHANGE,
+ CPU_IDLE_ENTER,
+ CPU_IDLE_EXIT,
+ CPU_M2_OR_DEEPER_ENTER,
+};
+
+struct idle_dcstat_info {
+ u64 all_idle_start;
+ u64 all_idle_end;
+ u64 total_all_idle;
+ u64 total_all_idle_count;
+ u64 all_active_start;
+ u64 all_active_end;
+ u64 total_all_active;
+ u64 total_all_active_count;
+ u64 M2_idle_start;
+ u64 M2_idle_total;
+ u64 M2_count;
+ u64 D1P_idle_start;
+ u64 D1P_idle_total;
+ u64 D1p_count;
+ u64 D1_idle_start;
+ u64 D1_idle_total;
+ u64 D1_count;
+ u64 D2_idle_start;
+ u64 D2_idle_total;
+ u64 D2_count;
+ u64 cal_duration;
+ u64 all_idle_op_total[MAX_LPM_INDEX_DC];
+ int all_idle_op_index;
+ u64 all_idle_count[MAX_LPM_INDEX_DC];
+};
+
+#define CLK_DCSTAT_OPS(clk, name) \
+static int name##_dc_show(struct seq_file *seq, void *data) \
+{ \
+ if (!clk) \
+ return -ENODEV; \
+ \
+ show_dc_stat_info(clk, seq, data); \
+ if (seq->count == PAGE_SIZE) \
+ pr_warn("%s The dump buf is larger than one page!\n", \
+ __func__); \
+ return 0; \
+} \
+static ssize_t name##_dc_write(struct file *filp, \
+ const char __user *buffer, size_t count, loff_t *ppos) \
+{ \
+ unsigned int start; \
+ char buf[10] = { 0 }; \
+ size_t ret = 0; \
+ \
+ if (!clk) \
+ return -ENODEV; \
+ \
+ if (copy_from_user(buf, buffer, count)) \
+ return -EFAULT; \
+ sscanf(buf, "%d", &start); \
+ ret = start_stop_dc_stat(clk, start); \
+ if (ret < 0) \
+ return ret; \
+ return count; \
+} \
+static int name##_dc_open(struct inode *inode, struct file *file) \
+{ \
+ return single_open(file, name##_dc_show, NULL); \
+} \
+static const struct file_operations name##_dc_ops = { \
+ .owner = THIS_MODULE, \
+ .open = name##_dc_open, \
+ .read = seq_read, \
+ .write = name##_dc_write, \
+ .llseek = seq_lseek, \
+ .release = single_release, \
+}; \
+
+/* function used for clk duty cycle stat */
+static inline u64 ts2ns(struct timespec64 cur, struct timespec64 prev)
+{
+ u64 time_ns = 0;
+
+ if ((cur.tv_sec > prev.tv_sec) ||
+ ((cur.tv_sec == prev.tv_sec) && (cur.tv_nsec > prev.tv_nsec))) {
+ time_ns = (u64)(cur.tv_sec - prev.tv_sec);
+ time_ns *= NSEC_PER_SEC;
+ time_ns += (u64)(cur.tv_nsec - prev.tv_nsec);
+ }
+
+ return time_ns;
+}
+
+static inline u32 calculate_dc(u32 busy, u32 total, u32 *fraction)
+{
+ u32 result, remainder;
+ u64 busy64, remainder64;
+
+ busy64 = (u64)busy;
+ result = div_u64_rem(busy64 * 100, total, &remainder);
+ remainder64 = (u64)remainder;
+ *fraction = div_u64(remainder64 * 100, total);
+
+ return result;
+}
+
+int show_dc_stat_info(struct clk *clk, struct seq_file *seq, void *data);
+int start_stop_dc_stat(struct clk *clk, unsigned int start);
+int clk_register_dcstat(struct clk *clk,
+ unsigned long *opt, unsigned int opt_size);
+#ifdef CONFIG_ARM_PSCI
+extern void asr_cpuidle_enter_dcstat(int index);
+extern void asr_cpuidle_exit_dcstat(void);
+#else
+static inline void asr_cpuidle_enter_dcstat(int index)
+{
+}
+static inline void asr_cpuidle_exit_dcstat(void)
+{
+}
+#endif
+typedef int (*powermode)(u32);
+#ifdef CONFIG_DEBUG_FS
+extern void cpu_dcstat_event(struct clk *clk, unsigned int cpuid,
+ enum clk_stat_msg msg, unsigned int tgtop);
+extern void clk_dcstat_event(struct clk *clk,
+ enum clk_stat_msg msg, unsigned int tgtstate);
+extern void clk_dcstat_event_check(struct clk *clk,
+ enum clk_stat_msg msg, unsigned int tgtstate);
+extern int register_cpu_dcstat(struct clk *clk, unsigned int cpunum,
+ unsigned int *op_table, unsigned int opt_size, powermode func);
+extern struct dentry *cpu_dcstat_file_create(const char *file_name,
+ struct dentry *parent);
+extern struct dentry *clk_dcstat_file_create(const char *file_name,
+ struct dentry *parent, const struct file_operations *fops);
+
+extern struct clk *cpu_dcstat_clk;
+extern void vol_dcstat_event(u32);
+extern void vol_ledstatus_event(u32);
+#else
+static inline void cpu_dcstat_event(struct clk *clk, unsigned int cpuid,
+ enum clk_stat_msg msg, unsigned int tgtop)
+{
+
+}
+static inline void clk_dcstat_event(struct clk *clk,
+ enum clk_stat_msg msg, unsigned int tgtstate)
+{
+
+}
+static inline void clk_dcstat_event_check(struct clk *clk,
+ enum clk_stat_msg msg, unsigned int tgtstate)
+{
+
+}
+static int register_cpu_dcstat(struct clk *clk, unsigned int cpunum,
+ unsigned int *op_table, unsigned int opt_size, powermode func);
+{
+
+}
+static struct dentry *cpu_dcstat_file_create(const char *file_name,
+ struct dentry *parent);
+{
+
+}
+static struct dentry *clk_dcstat_file_create(const char *file_name,
+ struct dentry *parent, const struct file_operations *fops);
+{
+
+}
+void vol_dcstat_event(u32) {}
+void vol_ledstatus_event(u32) {}
+#endif
+
+extern int ddr_profiling_show(struct clk_dc_stat_info *dc_stat_info);
+extern int ddr_profiling_store(int start);
+extern u64 suspended_time;
+#endif /* __ASRDCSTAT_H */
diff --git a/marvell/linux/include/soc/asr/cputype.h b/marvell/linux/include/soc/asr/cputype.h
new file mode 100644
index 0000000..a96abcf
--- /dev/null
+++ b/marvell/linux/include/soc/asr/cputype.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_CPUTYPE_H
+#define __ASM_MACH_CPUTYPE_H
+
+#include <asm/cputype.h>
+
+/*
+ * CPU Stepping CPU_ID CHIP_ID
+ *
+ * PXA168 S0 0x56158400 0x0000C910
+ * PXA168 A0 0x56158400 0x00A0A168
+ * PXA910 Y1 0x56158400 0x00F2C920
+ * PXA910 A0 0x56158400 0x00F2C910
+ * PXA910 A1 0x56158400 0x00A0C910
+ * PXA920 Y0 0x56158400 0x00F2C920
+ * PXA920 A0 0x56158400 0x00A0C920
+ * PXA920 A1 0x56158400 0x00A1C920
+ * MMP2 Z0 0x560f5811 0x00F00410
+ * MMP2 Z1 0x560f5811 0x00E00410
+ * MMP2 A0 0x560f5811 0x00A0A610
+ */
+
+extern unsigned int mmp_chip_id;
+
+#ifdef CONFIG_CPU_PXA168
+static inline int cpu_is_pxa168(void)
+{
+ return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
+ ((mmp_chip_id & 0xfff) == 0x168);
+}
+#else
+#define cpu_is_pxa168() (0)
+#endif
+
+/* cpu_is_pxa910() is shared on both pxa910 and pxa920 */
+#ifdef CONFIG_CPU_PXA910
+static inline int cpu_is_pxa910(void)
+{
+ return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
+ (((mmp_chip_id & 0xfff) == 0x910) ||
+ ((mmp_chip_id & 0xfff) == 0x920));
+}
+#else
+#define cpu_is_pxa910() (0)
+#endif
+
+#if defined(CONFIG_CPU_MMP2) || defined(CONFIG_MACH_MMP2_DT)
+static inline int cpu_is_mmp2(void)
+{
+ return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&
+ (((mmp_chip_id & 0xfff) == 0x410) ||
+ ((mmp_chip_id & 0xfff) == 0x610));
+}
+#else
+#define cpu_is_mmp2() (0)
+#endif
+
+#endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/marvell/linux/include/soc/asr/debugfs-asr.h b/marvell/linux/include/soc/asr/debugfs-asr.h
new file mode 100644
index 0000000..09185c9
--- /dev/null
+++ b/marvell/linux/include/soc/asr/debugfs-asr.h
@@ -0,0 +1,6 @@
+#ifndef __DEBUGFS_ASR_H_
+#define __DEBUGFS_ASR_H_
+
+extern struct dentry *asr_debug_entry;
+
+#endif /* __DEBUGFS_PXA_H_ */
\ No newline at end of file
diff --git a/marvell/linux/include/soc/asr/devices.h b/marvell/linux/include/soc/asr/devices.h
new file mode 100644
index 0000000..21217ef
--- /dev/null
+++ b/marvell/linux/include/soc/asr/devices.h
@@ -0,0 +1,56 @@
+#ifndef __MACH_DEVICE_H
+#define __MACH_DEVICE_H
+
+#include <linux/types.h>
+
+#define MAX_RESOURCE_DMA 2
+
+/* structure for describing the on-chip devices */
+struct pxa_device_desc {
+ const char *dev_name;
+ const char *drv_name;
+ int id;
+ int irq;
+ unsigned long start;
+ unsigned long size;
+ int dma[MAX_RESOURCE_DMA];
+};
+
+#define PXA168_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
+struct pxa_device_desc pxa168_device_##_name __initdata = { \
+ .dev_name = "pxa168-" #_name, \
+ .drv_name = _drv, \
+ .id = _id, \
+ .irq = IRQ_PXA168_##_irq, \
+ .start = _start, \
+ .size = _size, \
+ .dma = { _dma }, \
+};
+
+#define PXA910_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
+struct pxa_device_desc pxa910_device_##_name __initdata = { \
+ .dev_name = "pxa910-" #_name, \
+ .drv_name = _drv, \
+ .id = _id, \
+ .irq = IRQ_PXA910_##_irq, \
+ .start = _start, \
+ .size = _size, \
+ .dma = { _dma }, \
+};
+
+#define MMP2_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
+struct pxa_device_desc mmp2_device_##_name __initdata = { \
+ .dev_name = "mmp2-" #_name, \
+ .drv_name = _drv, \
+ .id = _id, \
+ .irq = IRQ_MMP2_##_irq, \
+ .start = _start, \
+ .size = _size, \
+ .dma = { _dma }, \
+}
+
+extern int pxa_register_device(struct pxa_device_desc *, void *, size_t);
+extern int pxa_usb_phy_init(void __iomem *phy_reg);
+extern void pxa_usb_phy_deinit(void __iomem *phy_reg);
+
+#endif /* __MACH_DEVICE_H */
diff --git a/marvell/linux/include/soc/asr/dma.h b/marvell/linux/include/soc/asr/dma.h
new file mode 100644
index 0000000..5e2650b
--- /dev/null
+++ b/marvell/linux/include/soc/asr/dma.h
@@ -0,0 +1,13 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/dma.h
+ */
+
+#ifndef __ASM_MACH_DMA_H
+#define __ASM_MACH_DMA_H
+
+#include <soc/asr/addr-map.h>
+
+#define DMAC_REGS_VIRT (APB_VIRT_BASE + 0x00000)
+
+#include <plat/dma.h>
+#endif /* __ASM_MACH_DMA_H */
diff --git a/marvell/linux/include/soc/asr/emmc_rsv.h b/marvell/linux/include/soc/asr/emmc_rsv.h
new file mode 100644
index 0000000..bb81923
--- /dev/null
+++ b/marvell/linux/include/soc/asr/emmc_rsv.h
@@ -0,0 +1,30 @@
+/*
+ * EMMC RESERVE PAGE APIs
+ *
+ * Copyright (C) 2014 Marvell International Ltd.
+ * Jialing Fu <jlfu@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#ifndef _EMMC_RSV_H_
+#define _EMMC_RSV_H_
+
+/*
+ * How to use these APIs
+ * 1. Put attention that the memory size is limit
+ * 2. When you call rsv_page_update, all the rsv_page memory will be flushed
+ * to eMMC block, so you need to avoid that some data is still being modified.
+ */
+enum rsv_page_index {
+ RSV_PAGE_SDH_EMMC,
+ RSV_PAGE_SDH_SD,
+ RSV_PAGE_SDH_SDIO,
+ RSV_PAGE_INDEX_MAX,
+};
+
+extern void *rsv_page_get_kaddr(enum rsv_page_index index, size_t want);
+extern void rsv_page_update(void);
+
+#endif /* _EMMC_RSV_H_ */
diff --git a/marvell/linux/include/soc/asr/emmd_rsv.h b/marvell/linux/include/soc/asr/emmd_rsv.h
new file mode 100644
index 0000000..ac3d0e4
--- /dev/null
+++ b/marvell/linux/include/soc/asr/emmd_rsv.h
@@ -0,0 +1,53 @@
+/*
+ * EMMD RESERVE PAGE APIs
+ *
+ * Copyright (C) 2014 Marvell International Ltd.
+ * Qing Zhu <qzhu@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#ifndef _EMMD_RSV_H_
+#define _EMMD_RSV_H_
+/*
+ * MRVL: the emmd reserve page share APIs to
+ * below items, they are aligned with uboot's:
+ * 1. emmd indicator;
+ * 2. dump style: USB or SD;
+ * 3. super kmalloc flags;
+ * 4. ram tags info;
+ * 5. held status registers in SQU;
+ * 6. (eden)PMIC power up/down log;
+ * 7. (eden)reset status registers;
+ *
+ * note: RDC for RAMDUMP is defined @0x8140400,size is 0x400, so we will
+ * use 0x8140000~0x8140400 to save above info.
+ */
+#define CRASH_PAGE_SIZE_SKM 8
+#define CRASH_PAGE_SIZE_RAMTAG 9
+#define CRASH_PAGE_SIZE_HELDSTATUS 64
+#define CRASH_PAGE_SIZE_PMIC 2
+#define CRASH_PAGE_SIZE_RESET_STATUS 4
+
+struct ram_tag_info {
+ char name[24];
+ unsigned long data;
+#ifdef CONFIG_ARM
+ unsigned int reserved;
+#endif
+};
+
+struct emmd_page {
+ unsigned int indicator;
+ unsigned int dump_style;
+ unsigned int p_rsvbuf[CRASH_PAGE_SIZE_SKM];
+ struct ram_tag_info ram_tag[CRASH_PAGE_SIZE_RAMTAG];
+ unsigned int held_status[CRASH_PAGE_SIZE_HELDSTATUS];
+ unsigned int pmic_regs[CRASH_PAGE_SIZE_PMIC];
+ unsigned int reset_status[CRASH_PAGE_SIZE_RESET_STATUS];
+ unsigned int pmic_power_status;
+};
+extern struct emmd_page *emmd_page;
+
+#endif /* _EMMD_RSV_H_ */
diff --git a/marvell/linux/include/soc/asr/gpio.h b/marvell/linux/include/soc/asr/gpio.h
new file mode 100644
index 0000000..047255d
--- /dev/null
+++ b/marvell/linux/include/soc/asr/gpio.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_MACH_GPIO_H
+#define __ASM_MACH_GPIO_H
+
+
+#include <linux/cputype.h>
+
+#include <asm-generic/gpio.h>
+
+#endif /* __ASM_MACH_GPIO_H */
diff --git a/marvell/linux/include/soc/asr/gpu_mem.h b/marvell/linux/include/soc/asr/gpu_mem.h
new file mode 100644
index 0000000..54518ad
--- /dev/null
+++ b/marvell/linux/include/soc/asr/gpu_mem.h
@@ -0,0 +1,19 @@
+/*
+* arch/arm/plat-pxa/include/plat/gpu_mem.h
+*
+* GPU reserved memory management
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+* (C) Copyright 2011 Marvell International Ltd.
+* All Rights Reserved
+*/
+
+#ifndef _PXA_GPU_MEM_H_
+#define _PXA_GPU_MEM_H_
+
+extern void __init pxa_reserve_gpu_memblock(void);
+extern void __init pxa_add_gpu(void);
+
+#endif
diff --git a/marvell/linux/include/soc/asr/hardware.h b/marvell/linux/include/soc/asr/hardware.h
new file mode 100644
index 0000000..99264a5
--- /dev/null
+++ b/marvell/linux/include/soc/asr/hardware.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_MACH_HARDWARE_H
+#define __ASM_MACH_HARDWARE_H
+
+#endif /* __ASM_MACH_HARDWARE_H */
diff --git a/marvell/linux/include/soc/asr/help_v7.h b/marvell/linux/include/soc/asr/help_v7.h
new file mode 100644
index 0000000..3b10432
--- /dev/null
+++ b/marvell/linux/include/soc/asr/help_v7.h
@@ -0,0 +1,103 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/help_v7.h
+ *
+ * Author: Fangsuo Wu <fswu@marvell.com>
+ * Copyright: (C) 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MMP_MACH_HELP_V7_H__
+#define __MMP_MACH_HELP_V7_H__
+
+#include <asm/cp15.h>
+#include <asm/cputype.h>
+#include <asm/smp_scu.h>
+
+#if defined(CONFIG_SMP) || defined(CONFIG_CPU_ASR18XX)
+#ifdef CONFIG_HAVE_ARM_SCU
+extern void __iomem *scu_get_base_addr(void);
+#endif
+
+static inline void core_exit_coherency(void)
+{
+ unsigned int v;
+ asm volatile(
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " bic %0, %0, #(1 << 6)\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ : "=&r" (v) : : "cc");
+ isb();
+}
+
+static inline void core_enter_coherency(void)
+{
+ unsigned int v;
+ asm volatile(
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " orr %0, %0, #(1 << 6)\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ : "=&r" (v) : : "cc");
+ isb();
+}
+#else
+static inline void core_exit_coherency(void);
+static inline void core_enter_coherency(void);
+#endif
+
+static inline void disable_l1_dcache(void)
+{
+ unsigned int v;
+ asm volatile(
+ " mrc p15, 0, %0, c1, c0, 0\n"
+ " bic %0, %0, %1\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+#ifdef CONFIG_ARM_ERRATA_794322
+ " ldr %0, =_stext\n"
+ " mcr p15, 0, %0, c8, c7, 1\n"
+ " dsb\n"
+#endif
+ : "=&r" (v) : "Ir" (CR_C) : "cc");
+ isb();
+}
+
+static inline void enable_l1_dcache(void)
+{
+ unsigned int v;
+ asm volatile(
+ " mrc p15, 0, %0, c1, c0, 0\n"
+ " orr %0, %0, %1\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ : "=&r" (v) : "Ir" (CR_C) : "cc");
+ isb();
+}
+
+static inline void ca9_power_down(void)
+{
+ flush_cache_louis();
+ disable_l1_dcache();
+ core_exit_coherency();
+#ifdef CONFIG_HAVE_ARM_SCU
+ scu_power_mode(scu_get_base_addr(), SCU_PM_POWEROFF);
+#endif
+}
+
+static inline void ca7_power_down(void)
+{
+ disable_l1_dcache();
+ flush_cache_louis();
+ asm volatile("clrex\n");
+ core_exit_coherency();
+}
+
+static inline void ca7_power_down_udr(void)
+{
+ disable_l1_dcache();
+ flush_cache_louis();
+ asm volatile("clrex\n");
+ flush_cache_all();
+ core_exit_coherency();
+}
+#endif
diff --git a/marvell/linux/include/soc/asr/irqs-pxa1928.h b/marvell/linux/include/soc/asr/irqs-pxa1928.h
new file mode 100644
index 0000000..efc6a5d
--- /dev/null
+++ b/marvell/linux/include/soc/asr/irqs-pxa1928.h
@@ -0,0 +1,323 @@
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+/*
+ * Interrupt numbers for PXA1928
+ */
+
+#if defined(CONFIG_GIC_BYPASS) /* Use ICU for Interrupt Handling */
+#if defined(CONFIG_SMP) /* Use GIC+ICU */
+#define IRQ_PXA1928_START 32
+#else /* ICU Only */
+#define IRQ_PXA1928_START 0
+#endif
+#else /* GIC Only Mode */
+#define IRQ_PXA1928_START 32
+#endif
+
+#define IRQ_PXA1928_NONE (-1)
+#define IRQ_PXA1928_SSP1 (IRQ_PXA1928_START + 0)
+#define IRQ_PXA1928_SSP2 (IRQ_PXA1928_START + 1)
+#define IRQ_PXA1928_SSPA1 (IRQ_PXA1928_START + 2)
+#define IRQ_PXA1928_SSPA2 (IRQ_PXA1928_START + 3)
+/* PMIC & USB Charger Intr. Mux */
+#define IRQ_PXA1928_INT4 (IRQ_PXA1928_START + 4)
+/* RTC Intr. Mux */
+#define IRQ_PXA1928_INT5 (IRQ_PXA1928_START + 5)
+#define IRQ_PXA1928_TWSI1 (IRQ_PXA1928_START + 7)
+/* GPU Intr. Mux */
+#define IRQ_PXA1928_INT8 (IRQ_PXA1928_START + 8)
+#define IRQ_PXA1928_KEYPAD (IRQ_PXA1928_START + 9)
+#define IRQ_PXA1928_ROTARY (IRQ_PXA1928_START + 10)
+#define IRQ_PXA1928_TRACKBALL (IRQ_PXA1928_START + 11)
+#define IRQ_PXA1928_ONEWIRE (IRQ_PXA1928_START + 12)
+#define IRQ_PXA1928_TIMER1 (IRQ_PXA1928_START + 13)
+#define IRQ_PXA1928_TIMER2 (IRQ_PXA1928_START + 14)
+#define IRQ_PXA1928_TIMER3 (IRQ_PXA1928_START + 15)
+#define IRQ_PXA1928_IPC1 (IRQ_PXA1928_START + 16)
+/* TWSI2 ~ TWSI6 Intr. Mux */
+#define IRQ_PXA1928_INT17 (IRQ_PXA1928_START + 17)
+/* Multicore cpu1 (IRQ & FIQ) Intr. */
+#define IRQ_PXA1928_INT18 (IRQ_PXA1928_START + 18)
+#define IRQ_PXA1928_HDMI (IRQ_PXA1928_START + 19)
+#define IRQ_PXA1928_SSP3 (IRQ_PXA1928_START + 20)
+#define IRQ_PXA1928_USB_HS (IRQ_PXA1928_START + 22)
+#define IRQ_PXA1928_UART3 (IRQ_PXA1928_START + 24)
+#define IRQ_PXA1928_VPU (IRQ_PXA1928_START + 26)
+#define IRQ_PXA1928_UART1 (IRQ_PXA1928_START + 27)
+#define IRQ_PXA1928_UART2 (IRQ_PXA1928_START + 28)
+#define IRQ_PXA1928_MIPI_DSI (IRQ_PXA1928_START + 29)
+/* ISP & Multicore cpu0 (IRQ & FIQ) Intr. Mux */
+#define IRQ_PXA1928_INT30 (IRQ_PXA1928_START + 30)
+#define IRQ_PXA1928_PMU_TIMER1 (IRQ_PXA1928_START + 31)
+#define IRQ_PXA1928_PMU_TIMER2 (IRQ_PXA1928_START + 32)
+#define IRQ_PXA1928_PMU_TIMER3 (IRQ_PXA1928_START + 33)
+/* Miscellaneous Intr. Mux */
+#define IRQ_PXA1928_INT35 (IRQ_PXA1928_START + 35)
+#define IRQ_PXA1928_WDT1 (IRQ_PXA1928_START + 36)
+#define IRQ_PXA1928_NAND_DMA (IRQ_PXA1928_START + 37)
+#define IRQ_PXA1928_USIM (IRQ_PXA1928_START + 38)
+#define IRQ_PXA1928_MMC (IRQ_PXA1928_START + 39)
+#define IRQ_PXA1928_WTM (IRQ_PXA1928_START + 40)
+#define IRQ_PXA1928_LCD (IRQ_PXA1928_START + 41)
+/* CCIC Intr. Mux */
+#define IRQ_PXA1928_INT42 (IRQ_PXA1928_START + 42)
+#define IRQ_PXA1928_PAD_EDGE (IRQ_PXA1928_START + 43)
+#define IRQ_PXA1928_USB_OTG (IRQ_PXA1928_START + 44)
+#define IRQ_PXA1928_NAND (IRQ_PXA1928_START + 45)
+#define IRQ_PXA1928_UART4 (IRQ_PXA1928_START + 46)
+#define IRQ_PXA1928_DMA_FIQ (IRQ_PXA1928_START + 47)
+#define IRQ_PXA1928_DMA_IRQ (IRQ_PXA1928_START + 48)
+#define IRQ_PXA1928_GPIO (IRQ_PXA1928_START + 49)
+#define IRQ_PXA1928_SECURITY (IRQ_PXA1928_START + 50)
+/* SSP Intr. Mux */
+#define IRQ_PXA1928_INT51 (IRQ_PXA1928_START + 51)
+#define IRQ_PXA1928_MMC2 (IRQ_PXA1928_START + 52)
+#define IRQ_PXA1928_MMC3 (IRQ_PXA1928_START + 53)
+#define IRQ_PXA1928_MMC4 (IRQ_PXA1928_START + 54)
+#define IRQ_PXA1928_IPC2 (IRQ_PXA1928_START + 56)
+/* DSP & Thermal Intr. Mux */
+#define IRQ_PXA1928_INT57 (IRQ_PXA1928_START + 57)
+#define IRQ_PXA1928_IPC_CP (IRQ_PXA1928_START + 59)
+#define IRQ_PXA1928_CA7_FREQ_CHG (IRQ_PXA1928_START + 60)
+#define IRQ_PXA1928_SMC (IRQ_PXA1928_START + 63)
+
+#if defined(CONFIG_GIC_BYPASS)
+
+#define IRQ_PXA1928_MUX_START (IRQ_PXA1928_START + 64)
+
+/* secondary interrupt of INT #4 */
+#define IRQ_PXA1928_INT4_BASE (IRQ_PXA1928_MUX_START)
+#define IRQ_PXA1928_CHARGER (IRQ_PXA1928_INT4_BASE + 0)
+#define IRQ_PXA1928_PMIC (IRQ_PXA1928_INT4_BASE + 1)
+#define IRQ_PXA1928_CHRG_DTC_OUT (IRQ_PXA1928_INT4_BASE + 3)
+
+/* secondary interrupt of INT #5 */
+#define IRQ_PXA1928_INT5_BASE (IRQ_PXA1928_INT4_BASE + 4)
+#define IRQ_PXA1928_RTC_ALARM (IRQ_PXA1928_INT5_BASE + 0)
+#define IRQ_PXA1928_RTC (IRQ_PXA1928_INT5_BASE + 1)
+
+/* secondary interrupt of INT #8 */
+#define IRQ_PXA1928_INT8_BASE (IRQ_PXA1928_INT5_BASE + 2)
+#define IRQ_PXA1928_GC2200 (IRQ_PXA1928_INT8_BASE + 0)
+#define IRQ_PXA1928_GC320 (IRQ_PXA1928_INT8_BASE + 2)
+#define IRQ_PXA1928_MULTICORE_INT_CPU3 (IRQ_PXA1928_INT8_BASE + 3)
+
+/* secondary interrupt of INT #17 */
+#define IRQ_PXA1928_INT17_BASE (IRQ_PXA1928_INT8_BASE + 4)
+#define IRQ_PXA1928_TWSI2 (IRQ_PXA1928_INT17_BASE + 0)
+#define IRQ_PXA1928_TWSI3 (IRQ_PXA1928_INT17_BASE + 1)
+#define IRQ_PXA1928_TWSI4 (IRQ_PXA1928_INT17_BASE + 2)
+#define IRQ_PXA1928_TWSI5 (IRQ_PXA1928_INT17_BASE + 3)
+#define IRQ_PXA1928_TWSI6 (IRQ_PXA1928_INT17_BASE + 4)
+#define IRQ_PXA1928_MULTICORE_INT_CPU2 (IRQ_PXA1928_INT17_BASE + 5)
+
+/* secondary interrupt of INT #18 */
+#define IRQ_PXA1928_INT18_BASE (IRQ_PXA1928_INT17_BASE + 6)
+#define IRQ_PXA1928_MULTICORE_INT_CPU1 (IRQ_PXA1928_INT18_BASE + 2)
+
+/* secondary interrupt of INT #30 */
+#define IRQ_PXA1928_INT30_BASE (IRQ_PXA1928_INT18_BASE + 3)
+#define IRQ_PXA1928_ISP_DMA (IRQ_PXA1928_INT30_BASE + 0)
+#define IRQ_PXA1928_DXO_ISP (IRQ_PXA1928_INT30_BASE + 1)
+#define IRQ_PXA1928_MULTICORE_INT_CPU0 (IRQ_PXA1928_INT30_BASE + 2)
+
+/* secondary interrupt of INT #35 */
+#define IRQ_PXA1928_INT35_BASE (IRQ_PXA1928_INT30_BASE + 3)
+#define IRQ_PXA1928_CA7_MP_TRIGGER0 (IRQ_PXA1928_INT35_BASE + 0)
+#define IRQ_PXA1928_CA7_MP_TRIGGER1 (IRQ_PXA1928_INT35_BASE + 1)
+#define IRQ_PXA1928_CA7_MP_TRIGGER2 (IRQ_PXA1928_INT35_BASE + 2)
+#define IRQ_PXA1928_CA7_MP_TRIGGER3 (IRQ_PXA1928_INT35_BASE + 3)
+#define IRQ_PXA1928_CA7_MP_COMMTX0 (IRQ_PXA1928_INT35_BASE + 4)
+#define IRQ_PXA1928_CA7_MP_COMMTX1 (IRQ_PXA1928_INT35_BASE + 5)
+#define IRQ_PXA1928_CA7_MP_COMMTX2 (IRQ_PXA1928_INT35_BASE + 6)
+#define IRQ_PXA1928_CA7_MP_COMMTX3 (IRQ_PXA1928_INT35_BASE + 7)
+#define IRQ_PXA1928_CA7_MP_COMMRX0 (IRQ_PXA1928_INT35_BASE + 8)
+#define IRQ_PXA1928_CA7_MP_COMMRX1 (IRQ_PXA1928_INT35_BASE + 9)
+#define IRQ_PXA1928_CA7_MP_COMMRX2 (IRQ_PXA1928_INT35_BASE + 10)
+#define IRQ_PXA1928_CA7_MP_COMMRX3 (IRQ_PXA1928_INT35_BASE + 11)
+#define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ0 (IRQ_PXA1928_INT35_BASE + 12)
+#define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ1 (IRQ_PXA1928_INT35_BASE + 13)
+#define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ2 (IRQ_PXA1928_INT35_BASE + 14)
+#define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ3 (IRQ_PXA1928_INT35_BASE + 15)
+#define IRQ_PXA1928_MULTICORE_NPMUIRQ0 (IRQ_PXA1928_INT35_BASE + 16)
+#define IRQ_PXA1928_MULTICORE_NPMUIRQ1 (IRQ_PXA1928_INT35_BASE + 17)
+#define IRQ_PXA1928_MULTICORE_NPMUIRQ2 (IRQ_PXA1928_INT35_BASE + 18)
+#define IRQ_PXA1928_MULTICORE_NPMUIRQ3 (IRQ_PXA1928_INT35_BASE + 19)
+#define IRQ_PXA1928_CORE_MP_NAXIERRIRQ (IRQ_PXA1928_INT35_BASE + 20)
+#define IRQ_PXA1928_WDT2_INT (IRQ_PXA1928_INT35_BASE + 21)
+#define IRQ_PXA1928_MULTICORE_NCNTPNSIRQ0 (IRQ_PXA1928_INT35_BASE + 23)
+#define IRQ_PXA1928_MULTICORE_NCNTPNSIRQ1 (IRQ_PXA1928_INT35_BASE + 24)
+#define IRQ_PXA1928_MULTICORE_NCNTPNSIRQ2 (IRQ_PXA1928_INT35_BASE + 25)
+#define IRQ_PXA1928_MULTICORE_NCNTPNSIRQ3 (IRQ_PXA1928_INT35_BASE + 26)
+#define IRQ_PXA1928_MULTICORE_NCNTPSIRQ0 (IRQ_PXA1928_INT35_BASE + 27)
+#define IRQ_PXA1928_MULTICORE_NCNTPSIRQ1 (IRQ_PXA1928_INT35_BASE + 28)
+#define IRQ_PXA1928_MULTICORE_NCNTPSIRQ2 (IRQ_PXA1928_INT35_BASE + 29)
+#define IRQ_PXA1928_MULTICORE_NCNTPSIRQ3 (IRQ_PXA1928_INT35_BASE + 30)
+#define IRQ_PXA1928_MCK_PML_OVERFLOW (IRQ_PXA1928_INT35_BASE + 31)
+
+/* secondary interrupt of INT #42 */
+#define IRQ_PXA1928_INT42_BASE (IRQ_PXA1928_INT35_BASE + 32)
+#define IRQ_PXA1928_CCIC2 (IRQ_PXA1928_INT42_BASE + 0)
+#define IRQ_PXA1928_CCIC1 (IRQ_PXA1928_INT42_BASE + 1)
+
+/* secondary interrupt of INT #48 (DMA_IRQ) */
+#define IRQ_PXA1928_INT48_BASE (IRQ_PXA1928_INT42_BASE + 2)
+#define IRQ_PXA1928_DMA_CHNL_INT0 (IRQ_PXA1928_INT48_BASE + 0)
+#define IRQ_PXA1928_DMA_CHNL_INT1 (IRQ_PXA1928_INT48_BASE + 1)
+#define IRQ_PXA1928_DMA_CHNL_INT2 (IRQ_PXA1928_INT48_BASE + 2)
+#define IRQ_PXA1928_DMA_CHNL_INT3 (IRQ_PXA1928_INT48_BASE + 3)
+#define IRQ_PXA1928_DMA_CHNL_INT4 (IRQ_PXA1928_INT48_BASE + 4)
+#define IRQ_PXA1928_DMA_CHNL_INT5 (IRQ_PXA1928_INT48_BASE + 5)
+#define IRQ_PXA1928_DMA_CHNL_INT6 (IRQ_PXA1928_INT48_BASE + 6)
+#define IRQ_PXA1928_DMA_CHNL_INT7 (IRQ_PXA1928_INT48_BASE + 7)
+#define IRQ_PXA1928_DMA_CHNL_INT8 (IRQ_PXA1928_INT48_BASE + 8)
+#define IRQ_PXA1928_DMA_CHNL_INT9 (IRQ_PXA1928_INT48_BASE + 9)
+#define IRQ_PXA1928_DMA_CHNL_INT10 (IRQ_PXA1928_INT48_BASE + 10)
+#define IRQ_PXA1928_DMA_CHNL_INT11 (IRQ_PXA1928_INT48_BASE + 11)
+#define IRQ_PXA1928_DMA_CHNL_INT12 (IRQ_PXA1928_INT48_BASE + 12)
+#define IRQ_PXA1928_DMA_CHNL_INT13 (IRQ_PXA1928_INT48_BASE + 13)
+#define IRQ_PXA1928_DMA_CHNL_INT14 (IRQ_PXA1928_INT48_BASE + 14)
+#define IRQ_PXA1928_DMA_CHNL_INT15 (IRQ_PXA1928_INT48_BASE + 15)
+#define IRQ_PXA1928_MDMA_CHNL_INT0 (IRQ_PXA1928_INT48_BASE + 16)
+#define IRQ_PXA1928_MDMA_CHNL_INT1 (IRQ_PXA1928_INT48_BASE + 17)
+#define IRQ_PXA1928_ADMA_CHNL_INT0 (IRQ_PXA1928_INT48_BASE + 18)
+#define IRQ_PXA1928_ADMA_CHNL_INT1 (IRQ_PXA1928_INT48_BASE + 19)
+#define IRQ_PXA1928_ADMA_CHNL_INT2 (IRQ_PXA1928_INT48_BASE + 20)
+#define IRQ_PXA1928_ADMA_CHNL_INT3 (IRQ_PXA1928_INT48_BASE + 21)
+#define IRQ_PXA1928_VDMA_INT (IRQ_PXA1928_INT48_BASE + 22)
+
+/* secondary interrupt of INT #51 */
+#define IRQ_PXA1928_INT51_BASE (IRQ_PXA1928_INT48_BASE + 23)
+#define IRQ_PXA1928_SSP1_SRDY (IRQ_PXA1928_INT51_BASE + 0)
+#define IRQ_PXA1928_SSP3_SRDY (IRQ_PXA1928_INT51_BASE + 1)
+
+/* secondary interrupt of INT #57 */
+#define IRQ_PXA1928_INT57_BASE (IRQ_PXA1928_INT51_BASE + 2)
+#define IRQ_PXA1928_DSP_INT_2 (IRQ_PXA1928_INT57_BASE + 2)
+#define IRQ_PXA1928_DSP_INT_3 (IRQ_PXA1928_INT57_BASE + 3)
+#define IRQ_PXA1928_DSP_INT_4 (IRQ_PXA1928_INT57_BASE + 4)
+#define IRQ_PXA1928_DSP_INT_5 (IRQ_PXA1928_INT57_BASE + 5)
+#define IRQ_PXA1928_DSP_INT_6 (IRQ_PXA1928_INT57_BASE + 6)
+#define IRQ_PXA1928_DSP_INT_7 (IRQ_PXA1928_INT57_BASE + 7)
+#define IRQ_PXA1928_DSP_INT_9 (IRQ_PXA1928_INT57_BASE + 9)
+#define IRQ_PXA1928_DSP_INT_10 (IRQ_PXA1928_INT57_BASE + 10)
+#define IRQ_PXA1928_DSP_INT_11 (IRQ_PXA1928_INT57_BASE + 11)
+#define IRQ_PXA1928_THERMAL_SENSOR (IRQ_PXA1928_INT57_BASE + 13)
+#define IRQ_PXA1928_MAIN_PMU_INT (IRQ_PXA1928_INT57_BASE + 14)
+#define IRQ_PXA1928_MULTICORE_NCNTVIRQ0 (IRQ_PXA1928_INT57_BASE + 15)
+#define IRQ_PXA1928_MULTICORE_NCNTVIRQ1 (IRQ_PXA1928_INT57_BASE + 16)
+#define IRQ_PXA1928_MULTICORE_NCNTVIRQ2 (IRQ_PXA1928_INT57_BASE + 17)
+#define IRQ_PXA1928_MULTICORE_NCNTVIRQ3 (IRQ_PXA1928_INT57_BASE + 18)
+#define IRQ_PXA1928_MULTICORE_NCNTHPIRQ0 (IRQ_PXA1928_INT57_BASE + 19)
+#define IRQ_PXA1928_MULTICORE_NCNTHPIRQ1 (IRQ_PXA1928_INT57_BASE + 20)
+#define IRQ_PXA1928_MULTICORE_NCNTHPIRQ2 (IRQ_PXA1928_INT57_BASE + 21)
+#define IRQ_PXA1928_MULTICORE_NCNTHPIRQ3 (IRQ_PXA1928_INT57_BASE + 22)
+#define IRQ_PXA1928_APMU_INT (IRQ_PXA1928_INT57_BASE + 23)
+
+#define IRQ_PXA1928_END (IRQ_PXA1928_INT57_BASE + 24)
+
+#else /* Use GIC Only Mode */
+
+#define IRQ_PXA1928_KEYPAD_WAKEUP (IRQ_PXA1928_START + 64)
+#define IRQ_PXA1928_USB_OTG_WAKEUP (IRQ_PXA1928_START + 66)
+#define IRQ_PXA1928_MMC1_WAKEUP (IRQ_PXA1928_START + 68)
+#define IRQ_PXA1928_MMC2_WAKEUP (IRQ_PXA1928_START + 70)
+#define IRQ_PXA1928_MMC3_WAKEUP (IRQ_PXA1928_START + 72)
+#define IRQ_PXA1928_MMC4_WAKEUP (IRQ_PXA1928_START + 74)
+#define IRQ_PXA1928_CHARGER (IRQ_PXA1928_START + 76)
+#define IRQ_PXA1928_PMIC (IRQ_PXA1928_START + 77)
+#define IRQ_PXA1928_CHRG_DTC_OUT (IRQ_PXA1928_START + 78)
+#define IRQ_PXA1928_RTC_ALARM (IRQ_PXA1928_START + 79)
+#define IRQ_PXA1928_RTC (IRQ_PXA1928_START + 80)
+#define IRQ_PXA1928_GC2200 (IRQ_PXA1928_START + 81)
+#define IRQ_PXA1928_GC320 (IRQ_PXA1928_START + 82)
+#define IRQ_PXA1928_MULTICORE_INT_CPU3 (IRQ_PXA1928_START + 83)
+#define IRQ_PXA1928_TWSI2 (IRQ_PXA1928_START + 84)
+#define IRQ_PXA1928_TWSI3 (IRQ_PXA1928_START + 85)
+#define IRQ_PXA1928_TWSI4 (IRQ_PXA1928_START + 86)
+#define IRQ_PXA1928_TWSI5 (IRQ_PXA1928_START + 87)
+#define IRQ_PXA1928_TWSI6 (IRQ_PXA1928_START + 88)
+#define IRQ_PXA1928_MULTICORE_INT_CPU2 (IRQ_PXA1928_START + 89)
+#define IRQ_PXA1928_MULTICORE_INT_CPU1 (IRQ_PXA1928_START + 90)
+#define IRQ_PXA1928_ISP_DMA (IRQ_PXA1928_START + 91)
+#define IRQ_PXA1928_DXO_ISP (IRQ_PXA1928_START + 92)
+#define IRQ_PXA1928_MULTICORE_INT_CPU0 (IRQ_PXA1928_START + 93)
+#define IRQ_PXA1928_CA7_MP_TRIGGER0 (IRQ_PXA1928_START + 94)
+#define IRQ_PXA1928_CA7_MP_TRIGGER1 (IRQ_PXA1928_START + 95)
+#define IRQ_PXA1928_CA7_MP_TRIGGER2 (IRQ_PXA1928_START + 96)
+#define IRQ_PXA1928_CA7_MP_TRIGGER3 (IRQ_PXA1928_START + 97)
+#define IRQ_PXA1928_CA7_MP_COMMTX0 (IRQ_PXA1928_START + 98)
+#define IRQ_PXA1928_CA7_MP_COMMTX1 (IRQ_PXA1928_START + 99)
+#define IRQ_PXA1928_CA7_MP_COMMTX2 (IRQ_PXA1928_START + 100)
+#define IRQ_PXA1928_CA7_MP_COMMTX3 (IRQ_PXA1928_START + 101)
+#define IRQ_PXA1928_CA7_MP_COMMRX0 (IRQ_PXA1928_START + 102)
+#define IRQ_PXA1928_CA7_MP_COMMRX1 (IRQ_PXA1928_START + 103)
+#define IRQ_PXA1928_CA7_MP_COMMRX2 (IRQ_PXA1928_START + 104)
+#define IRQ_PXA1928_CA7_MP_COMMRX3 (IRQ_PXA1928_START + 105)
+#define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ0 (IRQ_PXA1928_START + 106)
+#define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ1 (IRQ_PXA1928_START + 107)
+#define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ2 (IRQ_PXA1928_START + 108)
+#define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ3 (IRQ_PXA1928_START + 109)
+#define IRQ_PXA1928_MULTICORE_NPMUIRQ0 (IRQ_PXA1928_START + 110)
+#define IRQ_PXA1928_MULTICORE_NPMUIRQ1 (IRQ_PXA1928_START + 111)
+#define IRQ_PXA1928_MULTICORE_NPMUIRQ2 (IRQ_PXA1928_START + 112)
+#define IRQ_PXA1928_MULTICORE_NPMUIRQ3 (IRQ_PXA1928_START + 113)
+#define IRQ_PXA1928_CORE_MP_NAXIERRIRQ (IRQ_PXA1928_START + 114)
+#define IRQ_PXA1928_WDT2_INT (IRQ_PXA1928_START + 115)
+#define IRQ_PXA1928_MCK_PML_OVERFLOW (IRQ_PXA1928_START + 118)
+#define IRQ_PXA1928_CCIC2 (IRQ_PXA1928_START + 119)
+#define IRQ_PXA1928_CCIC1 (IRQ_PXA1928_START + 120)
+#define IRQ_PXA1928_SSP1_SRDY (IRQ_PXA1928_START + 121)
+#define IRQ_PXA1928_SSP3_SRDY (IRQ_PXA1928_START + 122)
+#define IRQ_PXA1928_DSP_INT_2 (IRQ_PXA1928_START + 123)
+#define IRQ_PXA1928_DSP_INT_3 (IRQ_PXA1928_START + 124)
+#define IRQ_PXA1928_DSP_INT_4 (IRQ_PXA1928_START + 125)
+#define IRQ_PXA1928_DSP_INT_5 (IRQ_PXA1928_START + 126)
+#define IRQ_PXA1928_DSP_INT_6 (IRQ_PXA1928_START + 127)
+#define IRQ_PXA1928_DSP_INT_7 (IRQ_PXA1928_START + 128)
+#define IRQ_PXA1928_DSP_INT_9 (IRQ_PXA1928_START + 129)
+#define IRQ_PXA1928_DSP_INT_10 (IRQ_PXA1928_START + 130)
+#define IRQ_PXA1928_DSP_INT_11 (IRQ_PXA1928_START + 131)
+#define IRQ_PXA1928_THERMAL_SENSOR (IRQ_PXA1928_START + 132)
+#define IRQ_PXA1928_MAIN_PMU_INT (IRQ_PXA1928_START + 133)
+#define IRQ_PXA1928_APMU_INT (IRQ_PXA1928_START + 134)
+#define IRQ_PXA1928_DMA_CHNL_INT0 (IRQ_PXA1928_START + 135)
+#define IRQ_PXA1928_DMA_CHNL_INT1 (IRQ_PXA1928_START + 136)
+#define IRQ_PXA1928_DMA_CHNL_INT2 (IRQ_PXA1928_START + 137)
+#define IRQ_PXA1928_DMA_CHNL_INT3 (IRQ_PXA1928_START + 138)
+#define IRQ_PXA1928_DMA_CHNL_INT4 (IRQ_PXA1928_START + 139)
+#define IRQ_PXA1928_DMA_CHNL_INT5 (IRQ_PXA1928_START + 140)
+#define IRQ_PXA1928_DMA_CHNL_INT6 (IRQ_PXA1928_START + 141)
+#define IRQ_PXA1928_DMA_CHNL_INT7 (IRQ_PXA1928_START + 142)
+#define IRQ_PXA1928_DMA_CHNL_INT8 (IRQ_PXA1928_START + 143)
+#define IRQ_PXA1928_DMA_CHNL_INT9 (IRQ_PXA1928_START + 144)
+#define IRQ_PXA1928_DMA_CHNL_INT10 (IRQ_PXA1928_START + 145)
+#define IRQ_PXA1928_DMA_CHNL_INT11 (IRQ_PXA1928_START + 146)
+#define IRQ_PXA1928_DMA_CHNL_INT12 (IRQ_PXA1928_START + 147)
+#define IRQ_PXA1928_DMA_CHNL_INT13 (IRQ_PXA1928_START + 148)
+#define IRQ_PXA1928_DMA_CHNL_INT14 (IRQ_PXA1928_START + 149)
+#define IRQ_PXA1928_DMA_CHNL_INT15 (IRQ_PXA1928_START + 150)
+#define IRQ_PXA1928_MDMA_CHNL_INT0 (IRQ_PXA1928_START + 151)
+#define IRQ_PXA1928_MDMA_CHNL_INT1 (IRQ_PXA1928_START + 152)
+#define IRQ_PXA1928_ADMA_CHNL_INT0 (IRQ_PXA1928_START + 153)
+#define IRQ_PXA1928_ADMA_CHNL_INT1 (IRQ_PXA1928_START + 154)
+#define IRQ_PXA1928_ADMA_CHNL_INT2 (IRQ_PXA1928_START + 155)
+#define IRQ_PXA1928_ADMA_CHNL_INT3 (IRQ_PXA1928_START + 156)
+#define IRQ_PXA1928_VDMA_INT (IRQ_PXA1928_START + 157)
+
+#define IRQ_PXA1928_END (IRQ_PXA1928_START + 160)
+#endif
+
+#if defined(CONFIG_CPU_PXA1928)
+#define IRQ_GPIO_START IRQ_PXA1928_END
+#else
+#define IRQ_GPIO_START 128
+#endif
+#define MMP_NR_BUILTIN_GPIO 192
+
+#define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO)
+#define MMP_NR_IRQS IRQ_BOARD_START
+#define MMP_GPIO_TO_IRQ(gpio) (IRQ_GPIO_START + (gpio))
+
+#endif /* __ASM_MACH_IRQS_H */
diff --git a/marvell/linux/include/soc/asr/irqs.h b/marvell/linux/include/soc/asr/irqs.h
new file mode 100755
index 0000000..2679be2
--- /dev/null
+++ b/marvell/linux/include/soc/asr/irqs.h
@@ -0,0 +1,266 @@
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+#include <linux/irqchip/mmp.h>
+
+/*
+ * Partial interrupt for PXA1826.
+ * The IRQ_PXA1822_START should not be 0 because irq domain is used
+ * which ignores the zero virq number, the virq= IRQ_PXA1822_START + hwirq
+ * dts file keep to use hwirq number in the mapping.
+ */
+
+/* FIXME: The following Macro will be refined by DT in future
+ * when Most of the Devices is configured in DT way.
+ */
+
+#define IRQ_PXA1822_PMIC (IRQ_PXA1822_START + 4)
+#define IRQ_PXA1822_RTC_ALARM (IRQ_PXA1822_START + 6)
+#define IRQ_PXA1822_KEYPAD (IRQ_PXA1822_START + 9)
+#define IRQ_PXA1822_AP_GMAC (IRQ_PXA1822_START + 11)
+#define IRQ_PXA1822_AP_TIMER1 (IRQ_PXA1822_START + 13)
+#define IRQ_PXA1822_AP_TIMER2_3 (IRQ_PXA1822_START + 14)
+#define IRQ_PXA1822_AP2_TIMER1 (IRQ_PXA1822_START + 29)
+#define IRQ_PXA1822_AP2_TIMER2_3 (IRQ_PXA1822_START + 30)
+#define IRQ_PXA1822_MMC (IRQ_PXA1822_START + 39)
+#define IRQ_PXA1822_USB1 (IRQ_PXA1822_START + 44)
+#define IRQ_PXA1822_HIFI_DMA (IRQ_PXA1822_START + 46)
+#define IRQ_PXA1822_DMA_INT0 (IRQ_PXA1822_START + 47)
+#define IRQ_PXA1822_GPIO_AP (IRQ_PXA1822_START + 49)
+#define IRQ_PXA1826S_USB_WAKEUP (IRQ_PXA1822_START + 53)
+
+/*
+ * Interrupt numbers for PXA168
+ */
+#define IRQ_PXA168_NONE (-1)
+#define IRQ_PXA168_SSP4 0
+#define IRQ_PXA168_SSP3 1
+#define IRQ_PXA168_SSP2 2
+#define IRQ_PXA168_SSP1 3
+#define IRQ_PXA168_PMIC_INT 4
+#define IRQ_PXA168_RTC_INT 5
+#define IRQ_PXA168_RTC_ALARM 6
+#define IRQ_PXA168_TWSI0 7
+#define IRQ_PXA168_GPU 8
+#define IRQ_PXA168_KEYPAD 9
+#define IRQ_PXA168_ONEWIRE 12
+#define IRQ_PXA168_TIMER1 13
+#define IRQ_PXA168_TIMER2 14
+#define IRQ_PXA168_TIMER3 15
+#define IRQ_PXA168_CMU 16
+#define IRQ_PXA168_SSP5 17
+#define IRQ_PXA168_MSP_WAKEUP 19
+#define IRQ_PXA168_CF_WAKEUP 20
+#define IRQ_PXA168_XD_WAKEUP 21
+#define IRQ_PXA168_MFU 22
+#define IRQ_PXA168_MSP 23
+#define IRQ_PXA168_CF 24
+#define IRQ_PXA168_XD 25
+#define IRQ_PXA168_DDR_INT 26
+#define IRQ_PXA168_UART1 27
+#define IRQ_PXA168_UART2 28
+#define IRQ_PXA168_UART3 29
+#define IRQ_PXA168_WDT 35
+#define IRQ_PXA168_MAIN_PMU 36
+#define IRQ_PXA168_FRQ_CHANGE 38
+#define IRQ_PXA168_SDH1 39
+#define IRQ_PXA168_SDH2 40
+#define IRQ_PXA168_LCD 41
+#define IRQ_PXA168_CI 42
+#define IRQ_PXA168_USB1 44
+#define IRQ_PXA168_NAND 45
+#define IRQ_PXA168_HIFI_DMA 46
+#define IRQ_PXA168_DMA_INT0 47
+#define IRQ_PXA168_DMA_INT1 48
+#define IRQ_PXA168_GPIOX 49
+#define IRQ_PXA168_USB2 51
+#define IRQ_PXA168_AC97 57
+#define IRQ_PXA168_TWSI1 58
+#define IRQ_PXA168_AP_PMU 60
+#define IRQ_PXA168_SM_INT 63
+
+/*
+ * Interrupt numbers for PXA910
+ */
+#define IRQ_PXA910_NONE (-1)
+#define IRQ_PXA910_AIRQ 0
+#define IRQ_PXA910_SSP3 1
+#define IRQ_PXA910_SSP2 2
+#define IRQ_PXA910_SSP1 3
+#define IRQ_PXA910_PMIC_INT 4
+#define IRQ_PXA910_RTC_INT 5
+#define IRQ_PXA910_RTC_ALARM 6
+#define IRQ_PXA910_TWSI0 7
+#define IRQ_PXA910_GPU 8
+#define IRQ_PXA910_KEYPAD 9
+#define IRQ_PXA910_ROTARY 10
+#define IRQ_PXA910_TRACKBALL 11
+#define IRQ_PXA910_ONEWIRE 12
+#define IRQ_PXA910_AP1_TIMER1 13
+#define IRQ_PXA910_AP1_TIMER2 14
+#define IRQ_PXA910_AP1_TIMER3 15
+#define IRQ_PXA910_IPC_AP0 16
+#define IRQ_PXA910_IPC_AP1 17
+#define IRQ_PXA910_IPC_AP2 18
+#define IRQ_PXA910_IPC_AP3 19
+#define IRQ_PXA910_IPC_AP4 20
+#define IRQ_PXA910_IPC_CP0 21
+#define IRQ_PXA910_IPC_CP1 22
+#define IRQ_PXA910_IPC_CP2 23
+#define IRQ_PXA910_IPC_CP3 24
+#define IRQ_PXA910_IPC_CP4 25
+#define IRQ_PXA910_L2_DDR 26
+#define IRQ_PXA910_UART2 27
+#define IRQ_PXA910_UART3 28
+#define IRQ_PXA910_AP2_TIMER1 29
+#define IRQ_PXA910_AP2_TIMER2 30
+#define IRQ_PXA910_CP2_TIMER1 31
+#define IRQ_PXA910_CP2_TIMER2 32
+#define IRQ_PXA910_CP2_TIMER3 33
+#define IRQ_PXA910_GSSP 34
+#define IRQ_PXA910_CP2_WDT 35
+#define IRQ_PXA910_MAIN_PMU 36
+#define IRQ_PXA910_CP_FREQ_CHG 37
+#define IRQ_PXA910_AP_FREQ_CHG 38
+#define IRQ_PXA910_MMC 39
+#define IRQ_PXA910_AEU 40
+#define IRQ_PXA910_LCD 41
+#define IRQ_PXA910_CCIC 42
+#define IRQ_PXA910_IRE 43
+#define IRQ_PXA910_USB1 44
+#define IRQ_PXA910_NAND 45
+#define IRQ_PXA910_HIFI_DMA 46
+#define IRQ_PXA910_DMA_INT0 47
+#define IRQ_PXA910_DMA_INT1 48
+#define IRQ_PXA910_AP_GPIO 49
+#define IRQ_PXA910_AP2_TIMER3 50
+#define IRQ_PXA910_USB2 51
+#define IRQ_PXA910_TWSI1 54
+#define IRQ_PXA910_CP_GPIO 55
+#define IRQ_PXA910_UART1 59 /* Slow UART */
+#define IRQ_PXA910_AP_PMU 60
+#define IRQ_PXA910_SM_INT 63 /* from PinMux */
+
+/*
+ * Interrupt numbers for MMP2
+ */
+#define IRQ_MMP2_NONE (-1)
+#define IRQ_MMP2_SSP1 0
+#define IRQ_MMP2_SSP2 1
+#define IRQ_MMP2_SSPA1 2
+#define IRQ_MMP2_SSPA2 3
+#define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */
+#define IRQ_MMP2_RTC_MUX 5
+#define IRQ_MMP2_TWSI1 7
+#define IRQ_MMP2_GPU 8
+#define IRQ_MMP2_KEYPAD_MUX 9
+#define IRQ_MMP2_ROTARY 10
+#define IRQ_MMP2_TRACKBALL 11
+#define IRQ_MMP2_ONEWIRE 12
+#define IRQ_MMP2_TIMER1 13
+#define IRQ_MMP2_TIMER2 14
+#define IRQ_MMP2_TIMER3 15
+#define IRQ_MMP2_RIPC 16
+#define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */
+#define IRQ_MMP2_HDMI 19
+#define IRQ_MMP2_SSP3 20
+#define IRQ_MMP2_SSP4 21
+#define IRQ_MMP2_USB_HS1 22
+#define IRQ_MMP2_USB_HS2 23
+#define IRQ_MMP2_UART3 24
+#define IRQ_MMP2_UART1 27
+#define IRQ_MMP2_UART2 28
+#define IRQ_MMP2_MIPI_DSI 29
+#define IRQ_MMP2_CI2 30
+#define IRQ_MMP2_PMU_TIMER1 31
+#define IRQ_MMP2_PMU_TIMER2 32
+#define IRQ_MMP2_PMU_TIMER3 33
+#define IRQ_MMP2_USB_FS 34
+#define IRQ_MMP2_MISC_MUX 35
+#define IRQ_MMP2_WDT1 36
+#define IRQ_MMP2_NAND_DMA 37
+#define IRQ_MMP2_USIM 38
+#define IRQ_MMP2_MMC 39
+#define IRQ_MMP2_WTM 40
+#define IRQ_MMP2_LCD 41
+#define IRQ_MMP2_CI 42
+#define IRQ_MMP2_IRE 43
+#define IRQ_MMP2_USB_OTG 44
+#define IRQ_MMP2_NAND 45
+#define IRQ_MMP2_UART4 46
+#define IRQ_MMP2_DMA_FIQ 47
+#define IRQ_MMP2_DMA_RIQ 48
+#define IRQ_MMP2_GPIO 49
+#define IRQ_MMP2_MIPI_HSI1_MUX 51
+#define IRQ_MMP2_MMC2 52
+#define IRQ_MMP2_MMC3 53
+#define IRQ_MMP2_MMC4 54
+#define IRQ_MMP2_MIPI_HSI0_MUX 55
+#define IRQ_MMP2_MSP 58
+#define IRQ_MMP2_MIPI_SLIM_DMA 59
+#define IRQ_MMP2_PJ4_FREQ_CHG 60
+#define IRQ_MMP2_MIPI_SLIM 62
+#define IRQ_MMP2_SM 63
+
+#define IRQ_MMP2_MUX_BASE 64
+
+/* secondary interrupt of INT #4 */
+#define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE)
+#define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0)
+#define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1)
+
+/* secondary interrupt of INT #5 */
+#define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2)
+#define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0)
+#define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1)
+
+/* secondary interrupt of INT #9 */
+#define IRQ_MMP2_KEYPAD_BASE (IRQ_MMP2_RTC_BASE + 2)
+#define IRQ_MMP2_KPC (IRQ_MMP2_KEYPAD_BASE + 0)
+#define IRQ_MMP2_ROTORY (IRQ_MMP2_KEYPAD_BASE + 1)
+#define IRQ_MMP2_TBALL (IRQ_MMP2_KEYPAD_BASE + 2)
+
+/* secondary interrupt of INT #17 */
+#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_KEYPAD_BASE + 3)
+#define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0)
+#define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1)
+#define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2)
+#define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3)
+#define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4)
+
+/* secondary interrupt of INT #35 */
+#define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5)
+#define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0)
+#define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1)
+#define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2)
+#define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3)
+#define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4)
+#define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5)
+#define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6)
+#define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7)
+#define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9)
+#define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10)
+#define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11)
+#define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12)
+#define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13)
+#define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14)
+
+/* secondary interrupt of INT #51 */
+#define IRQ_MMP2_MIPI_HSI1_BASE (IRQ_MMP2_MISC_BASE + 15)
+#define IRQ_MMP2_HSI1_CAWAKE (IRQ_MMP2_MIPI_HSI1_BASE + 0)
+#define IRQ_MMP2_MIPI_HSI_INT1 (IRQ_MMP2_MIPI_HSI1_BASE + 1)
+
+/* secondary interrupt of INT #55 */
+#define IRQ_MMP2_MIPI_HSI0_BASE (IRQ_MMP2_MIPI_HSI1_BASE + 2)
+#define IRQ_MMP2_HSI0_CAWAKE (IRQ_MMP2_MIPI_HSI0_BASE + 0)
+#define IRQ_MMP2_MIPI_HSI_INT0 (IRQ_MMP2_MIPI_HSI0_BASE + 1)
+
+#define IRQ_MMP2_MUX_END (IRQ_MMP2_MIPI_HSI0_BASE + 2)
+
+#define IRQ_GPIO_START 128
+#define MMP_NR_BUILTIN_GPIO 192
+
+#define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO)
+#define MMP_NR_IRQS IRQ_BOARD_START
+
+#endif /* __ASM_MACH_IRQS_H */
diff --git a/marvell/linux/include/soc/asr/memory.h b/marvell/linux/include/soc/asr/memory.h
new file mode 100644
index 0000000..f7c4e30
--- /dev/null
+++ b/marvell/linux/include/soc/asr/memory.h
@@ -0,0 +1,20 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/memory.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_MEMORY_H
+#define __ASM_MACH_MEMORY_H
+
+#if defined(CONFIG_CRASH_DUMP)
+#define PLAT_PHYS_OFFSET UL(0x06000000)
+#elif defined(CONFIG_TZ_HYPERVISOR)
+#define PLAT_PHYS_OFFSET UL(0x01000000)
+#else
+#define PLAT_PHYS_OFFSET UL(0x00000000)
+#endif
+
+#endif /* __ASM_MACH_MEMORY_H */
diff --git a/marvell/linux/include/soc/asr/mfp-mmp2.h b/marvell/linux/include/soc/asr/mfp-mmp2.h
new file mode 100644
index 0000000..c6b386d
--- /dev/null
+++ b/marvell/linux/include/soc/asr/mfp-mmp2.h
@@ -0,0 +1,395 @@
+#ifndef __ASM_MACH_MFP_MMP2_H
+#define __ASM_MACH_MFP_MMP2_H
+
+#include <soc/asr/mfp.h>
+
+#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
+#define MFP_DRIVE_SLOW (0x2 << 13)
+#define MFP_DRIVE_MEDIUM (0x4 << 13)
+#define MFP_DRIVE_FAST (0x6 << 13)
+
+/* GPIO */
+#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
+#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
+#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
+#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
+#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
+#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
+#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
+#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
+#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
+#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
+#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
+#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
+#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
+#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
+#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
+#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
+#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
+#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
+#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
+#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
+#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
+#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
+#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
+#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
+#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
+#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
+#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
+#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
+#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
+#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
+#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
+#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
+#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
+#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
+#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
+#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
+#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
+#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
+#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
+#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
+#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
+#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
+#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
+#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
+#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
+#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
+#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
+#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
+#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
+#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
+#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
+#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
+#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
+#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
+#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
+#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
+#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
+#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
+#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
+#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
+#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
+#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
+#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
+#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
+#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
+#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
+#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
+#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
+#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
+#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
+#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
+#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
+#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
+#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
+#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
+#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
+#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
+#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
+#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
+#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
+#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
+#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
+#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
+#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
+#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
+#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
+#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
+#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
+#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
+#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
+#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
+#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
+#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
+#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
+#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
+#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
+#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
+#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
+#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
+#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
+#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
+#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
+#define GPIO102_GPIO MFP_CFG(GPIO102, AF1)
+#define GPIO103_GPIO MFP_CFG(GPIO103, AF1)
+#define GPIO104_GPIO MFP_CFG(GPIO104, AF1)
+#define GPIO105_GPIO MFP_CFG(GPIO105, AF1)
+#define GPIO106_GPIO MFP_CFG(GPIO106, AF1)
+#define GPIO107_GPIO MFP_CFG(GPIO107, AF1)
+#define GPIO108_GPIO MFP_CFG(GPIO108, AF1)
+#define GPIO109_GPIO MFP_CFG(GPIO109, AF1)
+#define GPIO110_GPIO MFP_CFG(GPIO110, AF1)
+#define GPIO111_GPIO MFP_CFG(GPIO111, AF1)
+#define GPIO112_GPIO MFP_CFG(GPIO112, AF1)
+#define GPIO113_GPIO MFP_CFG(GPIO113, AF1)
+#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
+#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
+#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
+#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
+#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
+#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
+#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
+#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
+#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
+#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
+#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
+#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
+#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
+#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
+#define GPIO128_GPIO MFP_CFG(GPIO128, AF0)
+#define GPIO129_GPIO MFP_CFG(GPIO129, AF0)
+#define GPIO130_GPIO MFP_CFG(GPIO130, AF0)
+#define GPIO131_GPIO MFP_CFG(GPIO131, AF0)
+#define GPIO132_GPIO MFP_CFG(GPIO132, AF0)
+#define GPIO133_GPIO MFP_CFG(GPIO133, AF0)
+#define GPIO134_GPIO MFP_CFG(GPIO134, AF0)
+#define GPIO135_GPIO MFP_CFG(GPIO135, AF0)
+#define GPIO136_GPIO MFP_CFG(GPIO136, AF0)
+#define GPIO137_GPIO MFP_CFG(GPIO137, AF0)
+#define GPIO138_GPIO MFP_CFG(GPIO138, AF0)
+#define GPIO139_GPIO MFP_CFG(GPIO139, AF0)
+#define GPIO140_GPIO MFP_CFG(GPIO140, AF0)
+#define GPIO141_GPIO MFP_CFG(GPIO141, AF0)
+#define GPIO142_GPIO MFP_CFG(GPIO142, AF1)
+#define GPIO143_GPIO MFP_CFG(GPIO143, AF1)
+#define GPIO144_GPIO MFP_CFG(GPIO144, AF1)
+#define GPIO145_GPIO MFP_CFG(GPIO145, AF1)
+#define GPIO146_GPIO MFP_CFG(GPIO146, AF1)
+#define GPIO147_GPIO MFP_CFG(GPIO147, AF1)
+#define GPIO148_GPIO MFP_CFG(GPIO148, AF1)
+#define GPIO149_GPIO MFP_CFG(GPIO149, AF1)
+#define GPIO150_GPIO MFP_CFG(GPIO150, AF1)
+#define GPIO151_GPIO MFP_CFG(GPIO151, AF1)
+#define GPIO152_GPIO MFP_CFG(GPIO152, AF1)
+#define GPIO153_GPIO MFP_CFG(GPIO153, AF1)
+#define GPIO154_GPIO MFP_CFG(GPIO154, AF1)
+#define GPIO155_GPIO MFP_CFG(GPIO155, AF1)
+#define GPIO156_GPIO MFP_CFG(GPIO156, AF1)
+#define GPIO157_GPIO MFP_CFG(GPIO157, AF1)
+#define GPIO158_GPIO MFP_CFG(GPIO158, AF1)
+#define GPIO159_GPIO MFP_CFG(GPIO159, AF1)
+#define GPIO160_GPIO MFP_CFG(GPIO160, AF1)
+#define GPIO161_GPIO MFP_CFG(GPIO161, AF1)
+#define GPIO162_GPIO MFP_CFG(GPIO162, AF1)
+#define GPIO163_GPIO MFP_CFG(GPIO163, AF1)
+#define GPIO164_GPIO MFP_CFG(GPIO164, AF1)
+#define GPIO165_GPIO MFP_CFG(GPIO165, AF1)
+#define GPIO166_GPIO MFP_CFG(GPIO166, AF1)
+#define GPIO167_GPIO MFP_CFG(GPIO167, AF1)
+#define GPIO168_GPIO MFP_CFG(GPIO168, AF1)
+
+/* DFI */
+#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0)
+#define GPIO109_DFI_D14 MFP_CFG(GPIO109, AF0)
+#define GPIO110_DFI_D13 MFP_CFG(GPIO110, AF0)
+#define GPIO161_DFI_D12 MFP_CFG(GPIO161, AF0)
+#define GPIO162_DFI_D11 MFP_CFG(GPIO162, AF0)
+#define GPIO163_DFI_D10 MFP_CFG(GPIO163, AF0)
+#define GPIO164_DFI_D9 MFP_CFG(GPIO164, AF0)
+#define GPIO111_DFI_D8 MFP_CFG(GPIO111, AF0)
+#define GPIO104_DFI_D7 MFP_CFG(GPIO104, AF0)
+#define GPIO105_DFI_D6 MFP_CFG(GPIO105, AF0)
+#define GPIO106_DFI_D5 MFP_CFG(GPIO106, AF0)
+#define GPIO107_DFI_D4 MFP_CFG(GPIO107, AF0)
+#define GPIO165_DFI_D3 MFP_CFG(GPIO165, AF0)
+#define GPIO166_DFI_D2 MFP_CFG(GPIO166, AF0)
+#define GPIO167_DFI_D1 MFP_CFG(GPIO167, AF0)
+#define GPIO168_DFI_D0 MFP_CFG(GPIO168, AF0)
+#define GPIO143_ND_nCS0 MFP_CFG(GPIO143, AF0)
+#define GPIO144_ND_nCS1 MFP_CFG(GPIO144, AF0)
+#define GPIO147_ND_nWE MFP_CFG(GPIO147, AF0)
+#define GPIO148_ND_nRE MFP_CFG(GPIO148, AF0)
+#define GPIO150_ND_ALE MFP_CFG(GPIO150, AF0)
+#define GPIO149_ND_CLE MFP_CFG(GPIO149, AF0)
+#define GPIO112_ND_RDY0 MFP_CFG(GPIO112, AF0)
+#define GPIO160_ND_RDY1 MFP_CFG(GPIO160, AF0)
+
+/* Static Memory Controller */
+#define GPIO145_SMC_nCS0 MFP_CFG(GPIO145, AF0)
+#define GPIO146_SMC_nCS1 MFP_CFG(GPIO146, AF0)
+#define GPIO152_SMC_BE0 MFP_CFG(GPIO152, AF0)
+#define GPIO153_SMC_BE1 MFP_CFG(GPIO153, AF0)
+#define GPIO154_SMC_IRQ MFP_CFG(GPIO154, AF0)
+#define GPIO113_SMC_RDY MFP_CFG(GPIO113, AF0)
+#define GPIO151_SMC_SCLK MFP_CFG(GPIO151, AF0)
+
+/* Ethernet */
+#define GPIO155_SM_ADVMUX MFP_CFG(GPIO155, AF2)
+
+/* UART1 */
+#define GPIO45_UART1_RXD MFP_CFG(GPIO45, AF1)
+#define GPIO46_UART1_TXD MFP_CFG(GPIO46, AF1)
+#define GPIO29_UART1_RXD MFP_CFG(GPIO29, AF1)
+#define GPIO30_UART1_TXD MFP_CFG(GPIO30, AF1)
+#define GPIO31_UART1_CTS MFP_CFG(GPIO31, AF1)
+#define GPIO32_UART1_RTS MFP_CFG(GPIO32, AF1)
+
+/* UART2 */
+#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF1)
+#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF1)
+#define GPIO49_UART2_CTS MFP_CFG(GPIO49, AF1)
+#define GPIO50_UART2_RTS MFP_CFG(GPIO50, AF1)
+
+/* UART3 */
+#define GPIO51_UART3_RXD MFP_CFG(GPIO51, AF1)
+#define GPIO52_UART3_TXD MFP_CFG(GPIO52, AF1)
+#define GPIO53_UART3_CTS MFP_CFG(GPIO53, AF1)
+#define GPIO54_UART3_RTS MFP_CFG(GPIO54, AF1)
+
+/* MMC1 */
+#define GPIO124_MMC1_DAT7 MFP_CFG_DRV(GPIO124, AF1, FAST)
+#define GPIO125_MMC1_DAT6 MFP_CFG_DRV(GPIO125, AF1, FAST)
+#define GPIO129_MMC1_DAT5 MFP_CFG_DRV(GPIO129, AF1, FAST)
+#define GPIO130_MMC1_DAT4 MFP_CFG_DRV(GPIO130, AF1, FAST)
+#define GPIO131_MMC1_DAT3 MFP_CFG_DRV(GPIO131, AF1, FAST)
+#define GPIO132_MMC1_DAT2 MFP_CFG_DRV(GPIO132, AF1, FAST)
+#define GPIO133_MMC1_DAT1 MFP_CFG_DRV(GPIO133, AF1, FAST)
+#define GPIO134_MMC1_DAT0 MFP_CFG_DRV(GPIO134, AF1, FAST)
+#define GPIO136_MMC1_CMD MFP_CFG_DRV(GPIO136, AF1, FAST)
+#define GPIO139_MMC1_CLK MFP_CFG_DRV(GPIO139, AF1, FAST)
+#define GPIO140_MMC1_CD MFP_CFG_DRV(GPIO140, AF1, FAST)
+#define GPIO141_MMC1_WP MFP_CFG_DRV(GPIO141, AF1, FAST)
+
+/*MMC2*/
+#define GPIO37_MMC2_DAT3 MFP_CFG_DRV(GPIO37, AF1, FAST)
+#define GPIO38_MMC2_DAT2 MFP_CFG_DRV(GPIO38, AF1, FAST)
+#define GPIO39_MMC2_DAT1 MFP_CFG_DRV(GPIO39, AF1, FAST)
+#define GPIO40_MMC2_DAT0 MFP_CFG_DRV(GPIO40, AF1, FAST)
+#define GPIO41_MMC2_CMD MFP_CFG_DRV(GPIO41, AF1, FAST)
+#define GPIO42_MMC2_CLK MFP_CFG_DRV(GPIO42, AF1, FAST)
+
+/*MMC3*/
+#define GPIO165_MMC3_DAT7 MFP_CFG_DRV(GPIO165, AF2, FAST)
+#define GPIO162_MMC3_DAT6 MFP_CFG_DRV(GPIO162, AF2, FAST)
+#define GPIO166_MMC3_DAT5 MFP_CFG_DRV(GPIO166, AF2, FAST)
+#define GPIO163_MMC3_DAT4 MFP_CFG_DRV(GPIO163, AF2, FAST)
+#define GPIO167_MMC3_DAT3 MFP_CFG_DRV(GPIO167, AF2, FAST)
+#define GPIO164_MMC3_DAT2 MFP_CFG_DRV(GPIO164, AF2, FAST)
+#define GPIO168_MMC3_DAT1 MFP_CFG_DRV(GPIO168, AF2, FAST)
+#define GPIO111_MMC3_DAT0 MFP_CFG_DRV(GPIO111, AF2, FAST)
+#define GPIO112_MMC3_CMD MFP_CFG_DRV(GPIO112, AF2, FAST)
+#define GPIO151_MMC3_CLK MFP_CFG_DRV(GPIO151, AF2, FAST)
+
+/* LCD */
+#define GPIO74_LCD_FCLK MFP_CFG_DRV(GPIO74, AF1, FAST)
+#define GPIO75_LCD_LCLK MFP_CFG_DRV(GPIO75, AF1, FAST)
+#define GPIO76_LCD_PCLK MFP_CFG_DRV(GPIO76, AF1, FAST)
+#define GPIO77_LCD_DENA MFP_CFG_DRV(GPIO77, AF1, FAST)
+#define GPIO78_LCD_DD0 MFP_CFG_DRV(GPIO78, AF1, FAST)
+#define GPIO79_LCD_DD1 MFP_CFG_DRV(GPIO79, AF1, FAST)
+#define GPIO80_LCD_DD2 MFP_CFG_DRV(GPIO80, AF1, FAST)
+#define GPIO81_LCD_DD3 MFP_CFG_DRV(GPIO81, AF1, FAST)
+#define GPIO82_LCD_DD4 MFP_CFG_DRV(GPIO82, AF1, FAST)
+#define GPIO83_LCD_DD5 MFP_CFG_DRV(GPIO83, AF1, FAST)
+#define GPIO84_LCD_DD6 MFP_CFG_DRV(GPIO84, AF1, FAST)
+#define GPIO85_LCD_DD7 MFP_CFG_DRV(GPIO85, AF1, FAST)
+#define GPIO86_LCD_DD8 MFP_CFG_DRV(GPIO86, AF1, FAST)
+#define GPIO87_LCD_DD9 MFP_CFG_DRV(GPIO87, AF1, FAST)
+#define GPIO88_LCD_DD10 MFP_CFG_DRV(GPIO88, AF1, FAST)
+#define GPIO89_LCD_DD11 MFP_CFG_DRV(GPIO89, AF1, FAST)
+#define GPIO90_LCD_DD12 MFP_CFG_DRV(GPIO90, AF1, FAST)
+#define GPIO91_LCD_DD13 MFP_CFG_DRV(GPIO91, AF1, FAST)
+#define GPIO92_LCD_DD14 MFP_CFG_DRV(GPIO92, AF1, FAST)
+#define GPIO93_LCD_DD15 MFP_CFG_DRV(GPIO93, AF1, FAST)
+#define GPIO94_LCD_DD16 MFP_CFG_DRV(GPIO94, AF1, FAST)
+#define GPIO95_LCD_DD17 MFP_CFG_DRV(GPIO95, AF1, FAST)
+#define GPIO96_LCD_DD18 MFP_CFG_DRV(GPIO96, AF1, FAST)
+#define GPIO97_LCD_DD19 MFP_CFG_DRV(GPIO97, AF1, FAST)
+#define GPIO98_LCD_DD20 MFP_CFG_DRV(GPIO98, AF1, FAST)
+#define GPIO99_LCD_DD21 MFP_CFG_DRV(GPIO99, AF1, FAST)
+#define GPIO100_LCD_DD22 MFP_CFG_DRV(GPIO100, AF1, FAST)
+#define GPIO101_LCD_DD23 MFP_CFG_DRV(GPIO101, AF1, FAST)
+#define GPIO94_SPI_DCLK MFP_CFG_DRV(GPIO94, AF3, FAST)
+#define GPIO95_SPI_CS0 MFP_CFG_DRV(GPIO95, AF3, FAST)
+#define GPIO96_SPI_DIN MFP_CFG_DRV(GPIO96, AF3, FAST)
+#define GPIO97_SPI_DOUT MFP_CFG_DRV(GPIO97, AF3, FAST)
+#define GPIO98_LCD_RST MFP_CFG_DRV(GPIO98, AF0, FAST)
+
+#define GPIO114_MN_CLK_OUT MFP_CFG_DRV(GPIO114, AF1, FAST)
+
+/*LCD TV path*/
+#define GPIO124_LCD_DD24 MFP_CFG_DRV(GPIO124, AF2, FAST)
+#define GPIO125_LCD_DD25 MFP_CFG_DRV(GPIO125, AF2, FAST)
+#define GPIO126_LCD_DD33 MFP_CFG_DRV(GPIO126, AF2, FAST)
+#define GPIO127_LCD_DD26 MFP_CFG_DRV(GPIO127, AF2, FAST)
+#define GPIO128_LCD_DD27 MFP_CFG_DRV(GPIO128, AF2, FAST)
+#define GPIO129_LCD_DD28 MFP_CFG_DRV(GPIO129, AF2, FAST)
+#define GPIO130_LCD_DD29 MFP_CFG_DRV(GPIO130, AF2, FAST)
+#define GPIO135_LCD_DD30 MFP_CFG_DRV(GPIO135, AF2, FAST)
+#define GPIO137_LCD_DD31 MFP_CFG_DRV(GPIO137, AF2, FAST)
+#define GPIO138_LCD_DD32 MFP_CFG_DRV(GPIO138, AF2, FAST)
+#define GPIO140_LCD_DD34 MFP_CFG_DRV(GPIO140, AF2, FAST)
+#define GPIO141_LCD_DD35 MFP_CFG_DRV(GPIO141, AF2, FAST)
+
+/* I2C */
+#define GPIO43_TWSI2_SCL MFP_CFG_DRV(GPIO43, AF1, SLOW)
+#define GPIO44_TWSI2_SDA MFP_CFG_DRV(GPIO44, AF1, SLOW)
+#define GPIO71_TWSI3_SCL MFP_CFG_DRV(GPIO71, AF1, SLOW)
+#define GPIO72_TWSI3_SDA MFP_CFG_DRV(GPIO72, AF1, SLOW)
+#define TWSI4_SCL MFP_CFG_DRV(TWSI4_SCL, AF0, SLOW)
+#define TWSI4_SDA MFP_CFG_DRV(TWSI4_SDA, AF0, SLOW)
+#define GPIO99_TWSI5_SCL MFP_CFG_DRV(GPIO99, AF4, SLOW)
+#define GPIO100_TWSI5_SDA MFP_CFG_DRV(GPIO100, AF4, SLOW)
+#define GPIO97_TWSI6_SCL MFP_CFG_DRV(GPIO97, AF2, SLOW)
+#define GPIO98_TWSI6_SDA MFP_CFG_DRV(GPIO98, AF2, SLOW)
+
+/* SSPA1 */
+#define GPIO24_I2S_SYSCLK MFP_CFG(GPIO24, AF1)
+#define GPIO25_I2S_BITCLK MFP_CFG(GPIO25, AF1)
+#define GPIO26_I2S_SYNC MFP_CFG(GPIO26, AF1)
+#define GPIO27_I2S_DATA_OUT MFP_CFG(GPIO27, AF1)
+#define GPIO28_I2S_SDATA_IN MFP_CFG(GPIO28, AF1)
+#define GPIO114_I2S_MCLK MFP_CFG(GPIO114, AF1)
+
+/* SSPA2 */
+#define GPIO33_SSPA2_CLK MFP_CFG(GPIO33, AF1)
+#define GPIO34_SSPA2_FRM MFP_CFG(GPIO34, AF1)
+#define GPIO35_SSPA2_TXD MFP_CFG(GPIO35, AF1)
+#define GPIO36_SSPA2_RXD MFP_CFG(GPIO36, AF1)
+
+/* Keypad */
+#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1)
+#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1)
+#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1)
+#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1)
+#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1)
+#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1)
+#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1)
+#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1)
+#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1)
+#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1)
+#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1)
+#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1)
+#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1)
+#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1)
+#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1)
+#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1)
+#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1)
+#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1)
+#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1)
+#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1)
+#define GPIO20_KP_DKIN4 MFP_CFG(GPIO20, AF1)
+#define GPIO21_KP_DKIN5 MFP_CFG(GPIO21, AF1)
+#define GPIO22_KP_DKIN6 MFP_CFG(GPIO22, AF1)
+#define GPIO23_KP_DKIN7 MFP_CFG(GPIO23, AF1)
+
+/* CAMERA */
+#define GPIO59_CCIC_IN7 MFP_CFG_DRV(GPIO59, AF1, FAST)
+#define GPIO60_CCIC_IN6 MFP_CFG_DRV(GPIO60, AF1, FAST)
+#define GPIO61_CCIC_IN5 MFP_CFG_DRV(GPIO61, AF1, FAST)
+#define GPIO62_CCIC_IN4 MFP_CFG_DRV(GPIO62, AF1, FAST)
+#define GPIO63_CCIC_IN3 MFP_CFG_DRV(GPIO63, AF1, FAST)
+#define GPIO64_CCIC_IN2 MFP_CFG_DRV(GPIO64, AF1, FAST)
+#define GPIO65_CCIC_IN1 MFP_CFG_DRV(GPIO65, AF1, FAST)
+#define GPIO66_CCIC_IN0 MFP_CFG_DRV(GPIO66, AF1, FAST)
+#define GPIO67_CAM_HSYNC MFP_CFG_DRV(GPIO67, AF1, FAST)
+#define GPIO68_CAM_VSYNC MFP_CFG_DRV(GPIO68, AF1, FAST)
+#define GPIO69_CAM_MCLK MFP_CFG_DRV(GPIO69, AF1, FAST)
+#define GPIO70_CAM_PCLK MFP_CFG_DRV(GPIO70, AF1, FAST)
+
+/* PMIC */
+#define PMIC_PMIC_INT MFP_CFG(PMIC_INT, AF0)
+
+#endif /* __ASM_MACH_MFP_MMP2_H */
+
diff --git a/marvell/linux/include/soc/asr/mfp-pxa168.h b/marvell/linux/include/soc/asr/mfp-pxa168.h
new file mode 100644
index 0000000..9b591a3
--- /dev/null
+++ b/marvell/linux/include/soc/asr/mfp-pxa168.h
@@ -0,0 +1,354 @@
+#ifndef __ASM_MACH_MFP_PXA168_H
+#define __ASM_MACH_MFP_PXA168_H
+
+#include <soc/asr/mfp.h>
+
+#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
+#define MFP_DRIVE_SLOW (0x1 << 13)
+#define MFP_DRIVE_MEDIUM (0x2 << 13)
+#define MFP_DRIVE_FAST (0x3 << 13)
+
+#undef MFP_CFG
+#undef MFP_CFG_DRV
+
+#define MFP_CFG(pin, af) \
+ (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
+
+#define MFP_CFG_DRV(pin, af, drv) \
+ (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
+
+/* GPIO */
+#define GPIO0_GPIO MFP_CFG(GPIO0, AF5)
+#define GPIO1_GPIO MFP_CFG(GPIO1, AF5)
+#define GPIO2_GPIO MFP_CFG(GPIO2, AF5)
+#define GPIO3_GPIO MFP_CFG(GPIO3, AF5)
+#define GPIO4_GPIO MFP_CFG(GPIO4, AF5)
+#define GPIO5_GPIO MFP_CFG(GPIO5, AF5)
+#define GPIO6_GPIO MFP_CFG(GPIO6, AF5)
+#define GPIO7_GPIO MFP_CFG(GPIO7, AF5)
+#define GPIO8_GPIO MFP_CFG(GPIO8, AF5)
+#define GPIO9_GPIO MFP_CFG(GPIO9, AF5)
+#define GPIO10_GPIO MFP_CFG(GPIO10, AF5)
+#define GPIO11_GPIO MFP_CFG(GPIO11, AF5)
+#define GPIO12_GPIO MFP_CFG(GPIO12, AF5)
+#define GPIO13_GPIO MFP_CFG(GPIO13, AF5)
+#define GPIO14_GPIO MFP_CFG(GPIO14, AF5)
+#define GPIO15_GPIO MFP_CFG(GPIO15, AF5)
+#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
+#define GPIO17_GPIO MFP_CFG(GPIO17, AF5)
+#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
+#define GPIO19_GPIO MFP_CFG(GPIO19, AF5)
+#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
+#define GPIO21_GPIO MFP_CFG(GPIO21, AF5)
+#define GPIO22_GPIO MFP_CFG(GPIO22, AF5)
+#define GPIO23_GPIO MFP_CFG(GPIO23, AF5)
+#define GPIO24_GPIO MFP_CFG(GPIO24, AF5)
+#define GPIO25_GPIO MFP_CFG(GPIO25, AF5)
+#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
+#define GPIO27_GPIO MFP_CFG(GPIO27, AF5)
+#define GPIO28_GPIO MFP_CFG(GPIO28, AF5)
+#define GPIO29_GPIO MFP_CFG(GPIO29, AF5)
+#define GPIO30_GPIO MFP_CFG(GPIO30, AF5)
+#define GPIO31_GPIO MFP_CFG(GPIO31, AF5)
+#define GPIO32_GPIO MFP_CFG(GPIO32, AF5)
+#define GPIO33_GPIO MFP_CFG(GPIO33, AF5)
+#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
+#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
+#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
+#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
+#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
+#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
+#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
+#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
+#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
+#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
+#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
+#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
+#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
+#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
+#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
+#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
+#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
+#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
+#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
+#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
+#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
+#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
+#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
+#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
+#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
+#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
+#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
+#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
+#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
+#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
+#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
+#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
+#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
+#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
+#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
+#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
+#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
+#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
+#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
+#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
+#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
+#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
+#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
+#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
+#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
+#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
+#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
+#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
+#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
+#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
+#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
+#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
+#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
+#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
+#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
+#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
+#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
+#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
+#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
+#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
+#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
+#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
+#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
+#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
+#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
+#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
+#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
+#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
+#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
+#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
+#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
+#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
+#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
+#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
+#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
+#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
+#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
+#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
+#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
+#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
+#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
+#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
+#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
+#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
+#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
+#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
+#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
+#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
+#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
+
+/* DFI */
+#define GPIO0_DFI_D15 MFP_CFG(GPIO0, AF0)
+#define GPIO1_DFI_D14 MFP_CFG(GPIO1, AF0)
+#define GPIO2_DFI_D13 MFP_CFG(GPIO2, AF0)
+#define GPIO3_DFI_D12 MFP_CFG(GPIO3, AF0)
+#define GPIO4_DFI_D11 MFP_CFG(GPIO4, AF0)
+#define GPIO5_DFI_D10 MFP_CFG(GPIO5, AF0)
+#define GPIO6_DFI_D9 MFP_CFG(GPIO6, AF0)
+#define GPIO7_DFI_D8 MFP_CFG(GPIO7, AF0)
+#define GPIO8_DFI_D7 MFP_CFG(GPIO8, AF0)
+#define GPIO9_DFI_D6 MFP_CFG(GPIO9, AF0)
+#define GPIO10_DFI_D5 MFP_CFG(GPIO10, AF0)
+#define GPIO11_DFI_D4 MFP_CFG(GPIO11, AF0)
+#define GPIO12_DFI_D3 MFP_CFG(GPIO12, AF0)
+#define GPIO13_DFI_D2 MFP_CFG(GPIO13, AF0)
+#define GPIO14_DFI_D1 MFP_CFG(GPIO14, AF0)
+#define GPIO15_DFI_D0 MFP_CFG(GPIO15, AF0)
+
+#define GPIO30_DFI_ADDR0 MFP_CFG(GPIO30, AF0)
+#define GPIO31_DFI_ADDR1 MFP_CFG(GPIO31, AF0)
+#define GPIO32_DFI_ADDR2 MFP_CFG(GPIO32, AF0)
+#define GPIO33_DFI_ADDR3 MFP_CFG(GPIO33, AF0)
+
+/* NAND */
+#define GPIO16_ND_nCS0 MFP_CFG(GPIO16, AF1)
+#define GPIO17_ND_nWE MFP_CFG(GPIO17, AF0)
+#define GPIO21_ND_ALE MFP_CFG(GPIO21, AF0)
+#define GPIO22_ND_CLE MFP_CFG(GPIO22, AF0)
+#define GPIO24_ND_nRE MFP_CFG(GPIO24, AF0)
+#define GPIO26_ND_RnB1 MFP_CFG(GPIO26, AF1)
+#define GPIO27_ND_RnB2 MFP_CFG(GPIO27, AF1)
+
+/* Static Memory Controller */
+#define GPIO18_SMC_nCS0 MFP_CFG(GPIO18, AF3)
+#define GPIO18_SMC_nCS1 MFP_CFG(GPIO18, AF2)
+#define GPIO16_SMC_nCS0 MFP_CFG(GPIO16, AF2)
+#define GPIO16_SMC_nCS1 MFP_CFG(GPIO16, AF3)
+#define GPIO19_SMC_nCS0 MFP_CFG(GPIO19, AF0)
+#define GPIO20_SMC_nCS1 MFP_CFG(GPIO20, AF2)
+#define GPIO23_SMC_nLUA MFP_CFG(GPIO23, AF0)
+#define GPIO25_SMC_nLLA MFP_CFG(GPIO25, AF0)
+#define GPIO27_SMC_IRQ MFP_CFG(GPIO27, AF0)
+#define GPIO28_SMC_RDY MFP_CFG(GPIO28, AF0)
+#define GPIO29_SMC_SCLK MFP_CFG(GPIO29, AF0)
+#define GPIO34_SMC_nCS1 MFP_CFG(GPIO34, AF2)
+#define GPIO35_SMC_BE1 MFP_CFG(GPIO35, AF2)
+#define GPIO36_SMC_BE2 MFP_CFG(GPIO36, AF2)
+
+/* Compact Flash */
+#define GPIO19_CF_nCE1 MFP_CFG(GPIO19, AF3)
+#define GPIO20_CF_nCE2 MFP_CFG(GPIO20, AF3)
+#define GPIO23_CF_nALE MFP_CFG(GPIO23, AF3)
+#define GPIO25_CF_nRESET MFP_CFG(GPIO25, AF3)
+#define GPIO28_CF_RDY MFP_CFG(GPIO28, AF3)
+#define GPIO29_CF_STSCH MFP_CFG(GPIO29, AF3)
+#define GPIO30_CF_nREG MFP_CFG(GPIO30, AF3)
+#define GPIO31_CF_nIOIS16 MFP_CFG(GPIO31, AF3)
+#define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3)
+#define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3)
+
+/* UART */
+#define GPIO8_UART3_TXD MFP_CFG(GPIO8, AF2)
+#define GPIO9_UART3_RXD MFP_CFG(GPIO9, AF2)
+#define GPIO1O_UART3_CTS MFP_CFG(GPIO10, AF2)
+#define GPIO11_UART3_RTS MFP_CFG(GPIO11, AF2)
+#define GPIO88_UART2_TXD MFP_CFG(GPIO88, AF2)
+#define GPIO89_UART2_RXD MFP_CFG(GPIO89, AF2)
+#define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST)
+#define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST)
+#define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST)
+#define GPIO108_UART1_TXD MFP_CFG_DRV(GPIO108, AF2, FAST)
+#define GPIO109_UART1_CTS MFP_CFG(GPIO109, AF1)
+#define GPIO109_UART1_RTS MFP_CFG(GPIO109, AF2)
+#define GPIO110_UART1_RTS MFP_CFG(GPIO110, AF1)
+#define GPIO110_UART1_CTS MFP_CFG(GPIO110, AF2)
+#define GPIO111_UART1_RI MFP_CFG(GPIO111, AF1)
+#define GPIO111_UART1_DSR MFP_CFG(GPIO111, AF2)
+#define GPIO112_UART1_DTR MFP_CFG(GPIO111, AF1)
+#define GPIO112_UART1_DCD MFP_CFG(GPIO112, AF2)
+
+/* MMC1 */
+#define GPIO37_MMC1_DAT7 MFP_CFG(GPIO37, AF1)
+#define GPIO38_MMC1_DAT6 MFP_CFG(GPIO38, AF1)
+#define GPIO54_MMC1_DAT5 MFP_CFG(GPIO54, AF1)
+#define GPIO48_MMC1_DAT4 MFP_CFG(GPIO48, AF1)
+#define GPIO51_MMC1_DAT3 MFP_CFG(GPIO51, AF1)
+#define GPIO52_MMC1_DAT2 MFP_CFG(GPIO52, AF1)
+#define GPIO40_MMC1_DAT1 MFP_CFG(GPIO40, AF1)
+#define GPIO41_MMC1_DAT0 MFP_CFG(GPIO41, AF1)
+#define GPIO49_MMC1_CMD MFP_CFG(GPIO49, AF1)
+#define GPIO43_MMC1_CLK MFP_CFG(GPIO43, AF1)
+#define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1)
+#define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1)
+
+/* MMC2 */
+#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST)
+#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST)
+#define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST)
+#define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST)
+#define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST)
+#define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST)
+
+/* MMC4 */
+#define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST)
+#define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST)
+#define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST)
+#define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST)
+#define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST)
+#define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST)
+
+/* LCD */
+#define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1)
+#define GPIO60_LCD_DD0 MFP_CFG(GPIO60, AF1)
+#define GPIO61_LCD_DD1 MFP_CFG(GPIO61, AF1)
+#define GPIO70_LCD_DD10 MFP_CFG(GPIO70, AF1)
+#define GPIO71_LCD_DD11 MFP_CFG(GPIO71, AF1)
+#define GPIO72_LCD_DD12 MFP_CFG(GPIO72, AF1)
+#define GPIO73_LCD_DD13 MFP_CFG(GPIO73, AF1)
+#define GPIO74_LCD_DD14 MFP_CFG(GPIO74, AF1)
+#define GPIO75_LCD_DD15 MFP_CFG(GPIO75, AF1)
+#define GPIO76_LCD_DD16 MFP_CFG(GPIO76, AF1)
+#define GPIO77_LCD_DD17 MFP_CFG(GPIO77, AF1)
+#define GPIO78_LCD_DD18 MFP_CFG(GPIO78, AF1)
+#define GPIO79_LCD_DD19 MFP_CFG(GPIO79, AF1)
+#define GPIO62_LCD_DD2 MFP_CFG(GPIO62, AF1)
+#define GPIO80_LCD_DD20 MFP_CFG(GPIO80, AF1)
+#define GPIO81_LCD_DD21 MFP_CFG(GPIO81, AF1)
+#define GPIO82_LCD_DD22 MFP_CFG(GPIO82, AF1)
+#define GPIO83_LCD_DD23 MFP_CFG(GPIO83, AF1)
+#define GPIO63_LCD_DD3 MFP_CFG(GPIO63, AF1)
+#define GPIO64_LCD_DD4 MFP_CFG(GPIO64, AF1)
+#define GPIO65_LCD_DD5 MFP_CFG(GPIO65, AF1)
+#define GPIO66_LCD_DD6 MFP_CFG(GPIO66, AF1)
+#define GPIO67_LCD_DD7 MFP_CFG(GPIO67, AF1)
+#define GPIO68_LCD_DD8 MFP_CFG(GPIO68, AF1)
+#define GPIO69_LCD_DD9 MFP_CFG(GPIO69, AF1)
+#define GPIO59_LCD_DENA_BIAS MFP_CFG(GPIO59, AF1)
+#define GPIO56_LCD_FCLK_RD MFP_CFG(GPIO56, AF1)
+#define GPIO57_LCD_LCLK_A0 MFP_CFG(GPIO57, AF1)
+#define GPIO58_LCD_PCLK_WR MFP_CFG(GPIO58, AF1)
+#define GPIO85_LCD_VSYNC MFP_CFG(GPIO85, AF1)
+
+/* I2C */
+#define GPIO105_CI2C_SDA MFP_CFG(GPIO105, AF1)
+#define GPIO106_CI2C_SCL MFP_CFG(GPIO106, AF1)
+
+/* I2S */
+#define GPIO113_I2S_MCLK MFP_CFG(GPIO113, AF6)
+#define GPIO114_I2S_FRM MFP_CFG(GPIO114, AF1)
+#define GPIO115_I2S_BCLK MFP_CFG(GPIO115, AF1)
+#define GPIO116_I2S_RXD MFP_CFG(GPIO116, AF2)
+#define GPIO116_I2S_TXD MFP_CFG(GPIO116, AF1)
+#define GPIO117_I2S_TXD MFP_CFG(GPIO117, AF2)
+
+/* PWM */
+#define GPIO96_PWM3_OUT MFP_CFG(GPIO96, AF1)
+#define GPIO97_PWM2_OUT MFP_CFG(GPIO97, AF1)
+#define GPIO98_PWM1_OUT MFP_CFG(GPIO98, AF1)
+#define GPIO104_PWM4_OUT MFP_CFG(GPIO104, AF1)
+#define GPIO106_PWM2_OUT MFP_CFG(GPIO106, AF2)
+#define GPIO74_PWM4_OUT MFP_CFG(GPIO74, AF2)
+#define GPIO75_PWM3_OUT MFP_CFG(GPIO75, AF2)
+#define GPIO76_PWM2_OUT MFP_CFG(GPIO76, AF2)
+#define GPIO77_PWM1_OUT MFP_CFG(GPIO77, AF2)
+#define GPIO82_PWM4_OUT MFP_CFG(GPIO82, AF2)
+#define GPIO83_PWM3_OUT MFP_CFG(GPIO83, AF2)
+#define GPIO84_PWM2_OUT MFP_CFG(GPIO84, AF2)
+#define GPIO85_PWM1_OUT MFP_CFG(GPIO85, AF2)
+#define GPIO84_PWM1_OUT MFP_CFG(GPIO84, AF4)
+#define GPIO122_PWM3_OUT MFP_CFG(GPIO122, AF3)
+#define GPIO123_PWM1_OUT MFP_CFG(GPIO123, AF1)
+#define GPIO124_PWM2_OUT MFP_CFG(GPIO124, AF1)
+#define GPIO125_PWM3_OUT MFP_CFG(GPIO125, AF1)
+#define GPIO126_PWM4_OUT MFP_CFG(GPIO126, AF1)
+#define GPIO86_PWM1_OUT MFP_CFG(GPIO86, AF2)
+#define GPIO86_PWM2_OUT MFP_CFG(GPIO86, AF3)
+
+/* Keypad */
+#define GPIO109_KP_MKIN1 MFP_CFG(GPIO109, AF7)
+#define GPIO110_KP_MKIN0 MFP_CFG(GPIO110, AF7)
+#define GPIO111_KP_MKOUT7 MFP_CFG(GPIO111, AF7)
+#define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7)
+#define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7)
+
+/* Fast Ethernet */
+#define GPIO86_TX_CLK MFP_CFG(GPIO86, AF5)
+#define GPIO87_TX_EN MFP_CFG(GPIO87, AF5)
+#define GPIO88_TX_DQ3 MFP_CFG(GPIO88, AF5)
+#define GPIO89_TX_DQ2 MFP_CFG(GPIO89, AF5)
+#define GPIO90_TX_DQ1 MFP_CFG(GPIO90, AF5)
+#define GPIO91_TX_DQ0 MFP_CFG(GPIO91, AF5)
+#define GPIO92_MII_CRS MFP_CFG(GPIO92, AF5)
+#define GPIO93_MII_COL MFP_CFG(GPIO93, AF5)
+#define GPIO94_RX_CLK MFP_CFG(GPIO94, AF5)
+#define GPIO95_RX_ER MFP_CFG(GPIO95, AF5)
+#define GPIO96_RX_DQ3 MFP_CFG(GPIO96, AF5)
+#define GPIO97_RX_DQ2 MFP_CFG(GPIO97, AF5)
+#define GPIO98_RX_DQ1 MFP_CFG(GPIO98, AF5)
+#define GPIO99_RX_DQ0 MFP_CFG(GPIO99, AF5)
+#define GPIO100_MII_MDC MFP_CFG(GPIO100, AF5)
+#define GPIO101_MII_MDIO MFP_CFG(GPIO101, AF5)
+#define GPIO103_RX_DV MFP_CFG(GPIO103, AF5)
+
+/* SSP2 */
+#define GPIO107_SSP2_RXD MFP_CFG(GPIO107, AF4)
+#define GPIO108_SSP2_TXD MFP_CFG(GPIO108, AF4)
+#define GPIO111_SSP2_CLK MFP_CFG(GPIO111, AF4)
+#define GPIO112_SSP2_FRM MFP_CFG(GPIO112, AF4)
+
+#endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/marvell/linux/include/soc/asr/mfp-pxa910.h b/marvell/linux/include/soc/asr/mfp-pxa910.h
new file mode 100644
index 0000000..018a843
--- /dev/null
+++ b/marvell/linux/include/soc/asr/mfp-pxa910.h
@@ -0,0 +1,170 @@
+#ifndef __ASM_MACH_MFP_PXA910_H
+#define __ASM_MACH_MFP_PXA910_H
+
+#include <soc/asr/mfp.h>
+
+#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
+#define MFP_DRIVE_SLOW (0x2 << 13)
+#define MFP_DRIVE_MEDIUM (0x4 << 13)
+#define MFP_DRIVE_FAST (0x6 << 13)
+
+/* UART2 */
+#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6)
+#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6)
+
+/* UART3 */
+#define GPIO31_UART3_RXD MFP_CFG(GPIO31, AF4)
+#define GPIO32_UART3_TXD MFP_CFG(GPIO32, AF4)
+
+/*IRDA*/
+#define GPIO51_IRDA_SHDN MFP_CFG(GPIO51, AF0)
+
+/* SMC */
+#define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0)
+#define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0)
+#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0)
+#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0)
+#define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1)
+#define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1)
+
+/* I2C */
+#define GPIO53_CI2C_SCL MFP_CFG(GPIO53, AF2)
+#define GPIO54_CI2C_SDA MFP_CFG(GPIO54, AF2)
+
+/* SSP1 (I2S) */
+#define GPIO24_SSP1_SDATA_IN MFP_CFG_DRV(GPIO24, AF1, MEDIUM)
+#define GPIO21_SSP1_BITCLK MFP_CFG_DRV(GPIO21, AF1, MEDIUM)
+#define GPIO20_SSP1_SYSCLK MFP_CFG_DRV(GPIO20, AF1, MEDIUM)
+#define GPIO22_SSP1_SYNC MFP_CFG_DRV(GPIO22, AF1, MEDIUM)
+#define GPIO23_SSP1_DATA_OUT MFP_CFG_DRV(GPIO23, AF1, MEDIUM)
+#define GPIO124_MN_CLK_OUT MFP_CFG_DRV(GPIO124, AF1, MEDIUM)
+#define GPIO123_CLK_REQ MFP_CFG_DRV(GPIO123, AF0, MEDIUM)
+
+/* DFI */
+#define DF_IO0_ND_IO0 MFP_CFG(DF_IO0, AF0)
+#define DF_IO1_ND_IO1 MFP_CFG(DF_IO1, AF0)
+#define DF_IO2_ND_IO2 MFP_CFG(DF_IO2, AF0)
+#define DF_IO3_ND_IO3 MFP_CFG(DF_IO3, AF0)
+#define DF_IO4_ND_IO4 MFP_CFG(DF_IO4, AF0)
+#define DF_IO5_ND_IO5 MFP_CFG(DF_IO5, AF0)
+#define DF_IO6_ND_IO6 MFP_CFG(DF_IO6, AF0)
+#define DF_IO7_ND_IO7 MFP_CFG(DF_IO7, AF0)
+#define DF_IO8_ND_IO8 MFP_CFG(DF_IO8, AF0)
+#define DF_IO9_ND_IO9 MFP_CFG(DF_IO9, AF0)
+#define DF_IO10_ND_IO10 MFP_CFG(DF_IO10, AF0)
+#define DF_IO11_ND_IO11 MFP_CFG(DF_IO11, AF0)
+#define DF_IO12_ND_IO12 MFP_CFG(DF_IO12, AF0)
+#define DF_IO13_ND_IO13 MFP_CFG(DF_IO13, AF0)
+#define DF_IO14_ND_IO14 MFP_CFG(DF_IO14, AF0)
+#define DF_IO15_ND_IO15 MFP_CFG(DF_IO15, AF0)
+#define DF_nCS0_SM_nCS2_nCS0 MFP_CFG(DF_nCS0_SM_nCS2, AF0)
+#define DF_ALE_SM_WEn_ND_ALE MFP_CFG(DF_ALE_SM_WEn, AF1)
+#define DF_CLE_SM_OEn_ND_CLE MFP_CFG(DF_CLE_SM_OEn, AF0)
+#define DF_WEn_DF_WEn MFP_CFG(DF_WEn, AF1)
+#define DF_REn_DF_REn MFP_CFG(DF_REn, AF1)
+#define DF_RDY0_DF_RDY0 MFP_CFG(DF_RDY0, AF0)
+
+/*keypad*/
+#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1)
+#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1)
+#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1)
+#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1)
+#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1)
+#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1)
+#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1)
+#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1)
+#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1)
+#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1)
+#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1)
+#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1)
+#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1)
+#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1)
+#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1)
+#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1)
+#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1)
+#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1)
+#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1)
+#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1)
+
+/* LCD */
+#define GPIO81_LCD_FCLK MFP_CFG(GPIO81, AF1)
+#define GPIO82_LCD_LCLK MFP_CFG(GPIO82, AF1)
+#define GPIO83_LCD_PCLK MFP_CFG(GPIO83, AF1)
+#define GPIO84_LCD_DENA MFP_CFG(GPIO84, AF1)
+#define GPIO85_LCD_DD0 MFP_CFG(GPIO85, AF1)
+#define GPIO86_LCD_DD1 MFP_CFG(GPIO86, AF1)
+#define GPIO87_LCD_DD2 MFP_CFG(GPIO87, AF1)
+#define GPIO88_LCD_DD3 MFP_CFG(GPIO88, AF1)
+#define GPIO89_LCD_DD4 MFP_CFG(GPIO89, AF1)
+#define GPIO90_LCD_DD5 MFP_CFG(GPIO90, AF1)
+#define GPIO91_LCD_DD6 MFP_CFG(GPIO91, AF1)
+#define GPIO92_LCD_DD7 MFP_CFG(GPIO92, AF1)
+#define GPIO93_LCD_DD8 MFP_CFG(GPIO93, AF1)
+#define GPIO94_LCD_DD9 MFP_CFG(GPIO94, AF1)
+#define GPIO95_LCD_DD10 MFP_CFG(GPIO95, AF1)
+#define GPIO96_LCD_DD11 MFP_CFG(GPIO96, AF1)
+#define GPIO97_LCD_DD12 MFP_CFG(GPIO97, AF1)
+#define GPIO98_LCD_DD13 MFP_CFG(GPIO98, AF1)
+#define GPIO100_LCD_DD14 MFP_CFG(GPIO100, AF1)
+#define GPIO101_LCD_DD15 MFP_CFG(GPIO101, AF1)
+#define GPIO102_LCD_DD16 MFP_CFG(GPIO102, AF1)
+#define GPIO103_LCD_DD17 MFP_CFG(GPIO103, AF1)
+#define GPIO104_LCD_DD18 MFP_CFG(GPIO104, AF1)
+#define GPIO105_LCD_DD19 MFP_CFG(GPIO105, AF1)
+#define GPIO106_LCD_DD20 MFP_CFG(GPIO106, AF1)
+#define GPIO107_LCD_DD21 MFP_CFG(GPIO107, AF1)
+#define GPIO108_LCD_DD22 MFP_CFG(GPIO108, AF1)
+#define GPIO109_LCD_DD23 MFP_CFG(GPIO109, AF1)
+
+#define GPIO104_LCD_SPIDOUT MFP_CFG(GPIO104, AF3)
+#define GPIO105_LCD_SPIDIN MFP_CFG(GPIO105, AF3)
+#define GPIO107_LCD_CS1 MFP_CFG(GPIO107, AF3)
+#define GPIO108_LCD_DCLK MFP_CFG(GPIO108, AF3)
+
+#define GPIO106_LCD_RESET MFP_CFG(GPIO106, AF0)
+
+/*smart panel*/
+#define GPIO82_LCD_A0 MFP_CFG(GPIO82, AF0)
+#define GPIO83_LCD_WR MFP_CFG(GPIO83, AF0)
+#define GPIO103_LCD_CS MFP_CFG(GPIO103, AF0)
+
+/*1wire*/
+#define GPIO106_1WIRE MFP_CFG(GPIO106, AF3)
+
+/*CCIC*/
+#define GPIO67_CCIC_IN7 MFP_CFG_DRV(GPIO67, AF1, MEDIUM)
+#define GPIO68_CCIC_IN6 MFP_CFG_DRV(GPIO68, AF1, MEDIUM)
+#define GPIO69_CCIC_IN5 MFP_CFG_DRV(GPIO69, AF1, MEDIUM)
+#define GPIO70_CCIC_IN4 MFP_CFG_DRV(GPIO70, AF1, MEDIUM)
+#define GPIO71_CCIC_IN3 MFP_CFG_DRV(GPIO71, AF1, MEDIUM)
+#define GPIO72_CCIC_IN2 MFP_CFG_DRV(GPIO72, AF1, MEDIUM)
+#define GPIO73_CCIC_IN1 MFP_CFG_DRV(GPIO73, AF1, MEDIUM)
+#define GPIO74_CCIC_IN0 MFP_CFG_DRV(GPIO74, AF1, MEDIUM)
+#define GPIO75_CAM_HSYNC MFP_CFG_DRV(GPIO75, AF1, MEDIUM)
+#define GPIO76_CAM_VSYNC MFP_CFG_DRV(GPIO76, AF1, MEDIUM)
+#define GPIO77_CAM_MCLK MFP_CFG_DRV(GPIO77, AF1, MEDIUM)
+#define GPIO78_CAM_PCLK MFP_CFG_DRV(GPIO78, AF1, MEDIUM)
+
+/* MMC1 */
+#define MMC1_DAT7_MMC1_DAT7 MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM)
+#define MMC1_DAT6_MMC1_DAT6 MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM)
+#define MMC1_DAT5_MMC1_DAT5 MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM)
+#define MMC1_DAT4_MMC1_DAT4 MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM)
+#define MMC1_DAT3_MMC1_DAT3 MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM)
+#define MMC1_DAT2_MMC1_DAT2 MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM)
+#define MMC1_DAT1_MMC1_DAT1 MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM)
+#define MMC1_DAT0_MMC1_DAT0 MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM)
+#define MMC1_CMD_MMC1_CMD MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM)
+#define MMC1_CLK_MMC1_CLK MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM)
+#define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM)
+#define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM)
+
+/* PWM */
+#define GPIO27_PWM3_AF2 MFP_CFG(GPIO27, AF2)
+#define GPIO51_PWM2_OUT MFP_CFG(GPIO51, AF2)
+#define GPIO117_PWM1_OUT MFP_CFG(GPIO117, AF2)
+#define GPIO118_PWM2_OUT MFP_CFG(GPIO118, AF2)
+#define GPIO119_PWM3_OUT MFP_CFG(GPIO119, AF2)
+#define GPIO120_PWM4_OUT MFP_CFG(GPIO120, AF2)
+
+#endif /* __ASM_MACH MFP_PXA910_H */
diff --git a/marvell/linux/include/soc/asr/mfp.h b/marvell/linux/include/soc/asr/mfp.h
new file mode 100644
index 0000000..62e510e
--- /dev/null
+++ b/marvell/linux/include/soc/asr/mfp.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_MACH_MFP_H
+#define __ASM_MACH_MFP_H
+
+#include <plat/mfp.h>
+
+/*
+ * NOTE: the MFPR register bit definitions on PXA168 processor lines are a
+ * bit different from those on PXA3xx. Bit [7:10] are now reserved, which
+ * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
+ *
+ * To cope with this difference and re-use the pxa3xx mfp code as much as
+ * possible, we make the following compromise:
+ *
+ * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
+ * 2. DRIVE strength definitions redefined to include the reserved bit
+ * - the reserved bit differs between pxa168 and pxa910, and the
+ * MFP_DRIVE_* macros are individually defined in mfp-pxa{168,910}.h
+ * 3. Override MFP_CFG() and MFP_CFG_DRV()
+ * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
+ */
+
+#undef MFP_CFG
+#undef MFP_CFG_DRV
+#undef MFP_CFG_LPM
+#undef MFP_CFG_X
+#undef MFP_CFG_DEFAULT
+
+#define MFP_CFG(pin, af) \
+ (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
+
+#define MFP_CFG_DRV(pin, af, drv) \
+ (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
+
+#endif /* __ASM_MACH_MFP_H */
diff --git a/marvell/linux/include/soc/asr/mipsram_pm_event.h b/marvell/linux/include/soc/asr/mipsram_pm_event.h
new file mode 100755
index 0000000..7293a44
--- /dev/null
+++ b/marvell/linux/include/soc/asr/mipsram_pm_event.h
@@ -0,0 +1,64 @@
+/*
+ * This software program is licensed subject to the GNU General Public License
+ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
+
+ * (C) Copyright 2015 Marvell International Ltd.
+ * All Rights Reserved
+ */
+
+#ifndef PXA_MIPSRAM_PM_EVNT_H
+#define PXA_MIPSRAM_PM_EVNT_H
+
+#include <linux/mipsram.h>
+
+/* definitions for MIPSRAM events
+ * enum Names are used only in code, but Numbers are used by
+ * offline-mipsram tool and therefore reserved
+ */
+/*0x00020000+enum=131072+enum*/
+enum {
+ /* clk op index */
+ PM_OP0_MIPSRAM = 0,
+ PM_OP1_MIPSRAM,
+ PM_OP2_MIPSRAM,
+ PM_OP3_MIPSRAM,
+ PM_OP4_MIPSRAM,
+ PM_OP5_MIPSRAM,
+ PM_OP6_MIPSRAM,
+ PM_OP7_MIPSRAM,
+/* Existing EXCELL's trace/numbers, could be re-used
+ PM_DDR_REQ_RECEIVED_MIPSRAM, @*08=131080*@
+ PM_DVFM_CONSTRAITNS_SET,
+ PM_DDR_REL_RECEIVED_MIPSRAM, @*0A=131082*@
+ PM_DVFM_CONSTRAITNS_RELEASED,
+ PM_EARLY_DDR_PREVENTING_LPM,
+ PP_HF_DDR_REQ_RECEIVED_MIPSRAM,
+ PP_HF_DDR_REQ_HANDHELD_MIPSRAM,
+ PP_HF_DDR_REL_RECEIVED_MIPSRAM, @*0F=131087*@
+ PP_HF_DDR_REL_HANDHELD_MIPSRAM,
+*/
+ MAX_NUMBER_OF_PP_MIPSRAM,
+ INVALID_PP_NUMBER_MIPSRAM = 0xFF
+};
+
+enum {
+/*
+* ::Basic PM traces already defined in mipsram.h
+* 0x00020100+enum=131328+enum
+* ENTER_IDLE_MIPS_RAM = OFFSET_LPM_MIPS_RAM,
+* EXIT_IDLE_MIPS_RAM,
+* ENTER_D2_MIPS_RAM,
+* EXIT_D2_MIPS_RAM,
+* INVALID_LPM_NUMBER_MIPS_RAM = 0x1FF,
+*
+* ::Extention:
+**/
+ ENTER_CGM_MIPS_RAM = WKSRC_PMIC_MIPS_RAM + 1,
+ EXIT_CGM_MIPS_RAM,
+ ENTER_D1_MIPS_RAM,
+ EXIT_D1_MIPS_RAM,
+ LPM_TRACE_MAX_NUMBER_MIPSRAM,
+ INVALID_LPM_NUMBER_MIPSRAM = 0x1FF,
+};
+
+#endif
diff --git a/marvell/linux/include/soc/asr/mmp2.h b/marvell/linux/include/soc/asr/mmp2.h
new file mode 100644
index 0000000..515a886
--- /dev/null
+++ b/marvell/linux/include/soc/asr/mmp2.h
@@ -0,0 +1,106 @@
+#ifndef __ASM_MACH_MMP2_H
+#define __ASM_MACH_MMP2_H
+
+#include <linux/platform_data/pxa_sdhci.h>
+
+extern void mmp2_timer_init(void);
+extern void __init mmp2_init_icu(void);
+extern void __init mmp2_init_irq(void);
+extern void mmp2_clear_pmic_int(void);
+
+#include <linux/i2c.h>
+#include <linux/i2c/pxa-i2c.h>
+#include <soc/asr/devices.h>
+#include <linux/platform_data/dma-mmp_tdma.h>
+
+extern struct pxa_device_desc mmp2_device_uart1;
+extern struct pxa_device_desc mmp2_device_uart2;
+extern struct pxa_device_desc mmp2_device_uart3;
+extern struct pxa_device_desc mmp2_device_uart4;
+extern struct pxa_device_desc mmp2_device_twsi1;
+extern struct pxa_device_desc mmp2_device_twsi2;
+extern struct pxa_device_desc mmp2_device_twsi3;
+extern struct pxa_device_desc mmp2_device_twsi4;
+extern struct pxa_device_desc mmp2_device_twsi5;
+extern struct pxa_device_desc mmp2_device_twsi6;
+extern struct pxa_device_desc mmp2_device_sdh0;
+extern struct pxa_device_desc mmp2_device_sdh1;
+extern struct pxa_device_desc mmp2_device_sdh2;
+extern struct pxa_device_desc mmp2_device_sdh3;
+extern struct pxa_device_desc mmp2_device_asram;
+extern struct pxa_device_desc mmp2_device_isram;
+extern struct pxa_device_desc mmp2_device_u2o;
+extern struct pxa_device_desc mmp2_device_u2ootg;
+extern struct pxa_device_desc mmp2_device_u2oehci;
+extern struct pxa_device_desc mmp2_device_u2ophy;
+
+extern struct platform_device mmp2_device_gpio;
+
+static inline int mmp2_add_uart(int id)
+{
+ struct pxa_device_desc *d = NULL;
+
+ switch (id) {
+ case 1: d = &mmp2_device_uart1; break;
+ case 2: d = &mmp2_device_uart2; break;
+ case 3: d = &mmp2_device_uart3; break;
+ case 4: d = &mmp2_device_uart4; break;
+ default:
+ return -EINVAL;
+ }
+
+ return pxa_register_device(d, NULL, 0);
+}
+
+static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data,
+ struct i2c_board_info *info, unsigned size)
+{
+ struct pxa_device_desc *d = NULL;
+ int ret;
+
+ switch (id) {
+ case 1: d = &mmp2_device_twsi1; break;
+ case 2: d = &mmp2_device_twsi2; break;
+ case 3: d = &mmp2_device_twsi3; break;
+ case 4: d = &mmp2_device_twsi4; break;
+ case 5: d = &mmp2_device_twsi5; break;
+ case 6: d = &mmp2_device_twsi6; break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = i2c_register_board_info(id - 1, info, size);
+ if (ret)
+ return ret;
+
+ return pxa_register_device(d, data, sizeof(*data));
+}
+
+static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data)
+{
+ struct pxa_device_desc *d = NULL;
+
+ switch (id) {
+ case 0: d = &mmp2_device_sdh0; break;
+ case 1: d = &mmp2_device_sdh1; break;
+ case 2: d = &mmp2_device_sdh2; break;
+ case 3: d = &mmp2_device_sdh3; break;
+ default:
+ return -EINVAL;
+ }
+
+ return pxa_register_device(d, data, sizeof(*data));
+}
+
+static inline int mmp2_add_asram(struct sram_platdata *data)
+{
+ return pxa_register_device(&mmp2_device_asram, data, sizeof(*data));
+}
+
+static inline int mmp2_add_isram(struct sram_platdata *data)
+{
+ return pxa_register_device(&mmp2_device_isram, data, sizeof(*data));
+}
+
+#endif /* __ASM_MACH_MMP2_H */
+
diff --git a/marvell/linux/include/soc/asr/mmp_cpuidle.h b/marvell/linux/include/soc/asr/mmp_cpuidle.h
new file mode 100644
index 0000000..d829605
--- /dev/null
+++ b/marvell/linux/include/soc/asr/mmp_cpuidle.h
@@ -0,0 +1,46 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/mmp_cpuidle.h
+ *
+ * Author: Fangsuo Wu <fswu@marvell.com>
+ * Copyright: (C) 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MMP_MACH_MMP_CPUIDLE_H__
+#define __MMP_MACH_MMP_CPUIDLE_H__
+
+struct platform_power_ops {
+ void (*set_pmu)(u32 cpu, u32 power_state);
+ void (*clr_pmu)(u32 cpu);
+ void (*save_wakeup)(void);
+ void (*restore_wakeup)(void);
+ void (*power_up_setup)(unsigned int);
+ int (*cpu_power_status)(u32);
+};
+
+struct platform_idle {
+ u32 cpudown_state; /* hardware state when cpu be shutdown */
+ u32 wakeup_state; /* hardware state when wakeup be set */
+ u32 hotplug_state; /* hardware state when cpu hotplug out */
+ u32 l2_flush_state; /* hardware state when l2 flush is need */
+ u32 state_count; /* number of hardware states */
+ struct platform_power_ops *ops;
+ struct cpuidle_state *states;
+};
+
+int __init mmp_platform_power_register(struct platform_idle *idle);
+void asr_set_target_lpm_state(unsigned int cpu, unsigned int cluster,
+ int target_state, int *entered_state_ptr);
+
+extern int __init mcpm_platform_state_register \
+ (struct cpuidle_state *states, int count);
+#ifdef CONFIG_CPU_ASR18XX
+void asr18xx_pm_suspend(unsigned long addr);
+void asr18xx_pm_powered_up(void);
+extern int __init asr18xx_platform_state_register(
+ struct cpuidle_state *states, int count);
+#endif
+#endif
diff --git a/marvell/linux/include/soc/asr/pm-mmp2.h b/marvell/linux/include/soc/asr/pm-mmp2.h
new file mode 100644
index 0000000..a387008
--- /dev/null
+++ b/marvell/linux/include/soc/asr/pm-mmp2.h
@@ -0,0 +1,61 @@
+/*
+ * MMP2 Power Management Routines
+ *
+ * This software program is licensed subject to the GNU General Public License
+ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
+ *
+ * (C) Copyright 2010 Marvell International Ltd.
+ * All Rights Reserved
+ */
+
+#ifndef __MMP2_PM_H__
+#define __MMP2_PM_H__
+
+#include <soc/asr/addr-map.h>
+
+#define APMU_PJ_IDLE_CFG APMU_REG(0x018)
+#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1)
+#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5)
+#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16)
+#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19)
+#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28)
+
+#define APMU_SRAM_PWR_DWN APMU_REG(0x08c)
+
+#define MPMU_SCCR MPMU_REG(0x038)
+#define MPMU_PCR_PJ MPMU_REG(0x1000)
+#define MPMU_PCR_PJ_AXISD (1 << 31)
+#define MPMU_PCR_PJ_SLPEN (1 << 29)
+#define MPMU_PCR_PJ_SPSD (1 << 28)
+#define MPMU_PCR_PJ_DDRCORSD (1 << 27)
+#define MPMU_PCR_PJ_APBSD (1 << 26)
+#define MPMU_PCR_PJ_INTCLR (1 << 24)
+#define MPMU_PCR_PJ_SLPWP0 (1 << 23)
+#define MPMU_PCR_PJ_SLPWP1 (1 << 22)
+#define MPMU_PCR_PJ_SLPWP2 (1 << 21)
+#define MPMU_PCR_PJ_SLPWP3 (1 << 20)
+#define MPMU_PCR_PJ_VCTCXOSD (1 << 19)
+#define MPMU_PCR_PJ_SLPWP4 (1 << 18)
+#define MPMU_PCR_PJ_SLPWP5 (1 << 17)
+#define MPMU_PCR_PJ_SLPWP6 (1 << 16)
+#define MPMU_PCR_PJ_SLPWP7 (1 << 15)
+
+#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414)
+#define MPMU_CGR_PJ MPMU_REG(0x1024)
+#define MPMU_WUCRM_PJ MPMU_REG(0x104c)
+#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x))
+#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17)
+
+enum {
+ POWER_MODE_ACTIVE = 0,
+ POWER_MODE_CORE_INTIDLE,
+ POWER_MODE_CORE_EXTIDLE,
+ POWER_MODE_APPS_IDLE,
+ POWER_MODE_APPS_SLEEP,
+ POWER_MODE_CHIP_SLEEP,
+ POWER_MODE_SYS_SLEEP,
+};
+
+extern void mmp2_pm_enter_lowpower_mode(int state);
+extern int mmp2_set_wake(struct irq_data *d, unsigned int on);
+#endif
diff --git a/marvell/linux/include/soc/asr/pm-pxa910.h b/marvell/linux/include/soc/asr/pm-pxa910.h
new file mode 100644
index 0000000..8cac8ab
--- /dev/null
+++ b/marvell/linux/include/soc/asr/pm-pxa910.h
@@ -0,0 +1,77 @@
+/*
+ * PXA910 Power Management Routines
+ *
+ * This software program is licensed subject to the GNU General Public License
+ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
+ *
+ * (C) Copyright 2009 Marvell International Ltd.
+ * All Rights Reserved
+ */
+
+#ifndef __PXA910_PM_H__
+#define __PXA910_PM_H__
+
+#define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
+#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
+#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
+#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
+#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
+#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
+#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
+#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
+
+#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
+#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
+
+#define MPMU_FCCR MPMU_REG(0x0008)
+#define MPMU_APCR MPMU_REG(0x1000)
+#define MPMU_APCR_AXISD (1 << 31)
+#define MPMU_APCR_DSPSD (1 << 30)
+#define MPMU_APCR_SLPEN (1 << 29)
+#define MPMU_APCR_DTCMSD (1 << 28)
+#define MPMU_APCR_DDRCORSD (1 << 27)
+#define MPMU_APCR_APBSD (1 << 26)
+#define MPMU_APCR_BBSD (1 << 25)
+#define MPMU_APCR_SLPWP0 (1 << 23)
+#define MPMU_APCR_SLPWP1 (1 << 22)
+#define MPMU_APCR_SLPWP2 (1 << 21)
+#define MPMU_APCR_SLPWP3 (1 << 20)
+#define MPMU_APCR_VCTCXOSD (1 << 19)
+#define MPMU_APCR_SLPWP4 (1 << 18)
+#define MPMU_APCR_SLPWP5 (1 << 17)
+#define MPMU_APCR_SLPWP6 (1 << 16)
+#define MPMU_APCR_SLPWP7 (1 << 15)
+#define MPMU_APCR_MSASLPEN (1 << 14)
+#define MPMU_APCR_STBYEN (1 << 13)
+
+#define MPMU_AWUCRM MPMU_REG(0x104c)
+#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
+#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
+#define MPMU_AWUCRM_SDH1 (1 << 23)
+#define MPMU_AWUCRM_SDH2 (1 << 22)
+#define MPMU_AWUCRM_KEYPRESS (1 << 21)
+#define MPMU_AWUCRM_TRACKBALL (1 << 20)
+#define MPMU_AWUCRM_NEWROTARY (1 << 19)
+#define MPMU_AWUCRM_RTC_ALARM (1 << 17)
+#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
+#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
+#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
+#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
+#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
+#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
+#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
+
+enum {
+ POWER_MODE_ACTIVE = 0,
+ POWER_MODE_CORE_INTIDLE,
+ POWER_MODE_CORE_EXTIDLE,
+ POWER_MODE_APPS_IDLE,
+ POWER_MODE_APPS_SLEEP,
+ POWER_MODE_SYS_SLEEP,
+ POWER_MODE_HIBERNATE,
+ POWER_MODE_UDR,
+};
+
+extern int pxa910_set_wake(struct irq_data *data, unsigned int on);
+
+#endif
diff --git a/marvell/linux/include/soc/asr/pm.h b/marvell/linux/include/soc/asr/pm.h
new file mode 100644
index 0000000..cadc461
--- /dev/null
+++ b/marvell/linux/include/soc/asr/pm.h
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-mmp/include/mach/pm.h
+ *
+ * Author: Fan Wu <fwu@marvell.com>
+ * Copyright: (C) 2013 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MACH_PM_H__
+#define __MACH_PM_H__
+
+/* MMP suspend API Function Notes:
+ * 1) set_wake:
+ * offer interrupt clients to enable itself as wakeup source
+ * 2) pre_suspend_check:
+ * Anything need to do before entering suspend.
+ * return 0 if there is nothing wrong or unexpected.
+ * 3) post_chk_wakeup:
+ * Wakeup source check after suspend, often for debug usage.
+ * return the wakeup source bit map to the caller.
+ * 4) post_clr_wakeup:
+ * Clear the possible wakeup source after suspend.
+ * 5) plt_suspend_init:
+ * Platform specified suspend init operation can be included in
+ * this function.
+ */
+struct suspend_ops {
+ void (*set_wake)(int irq, unsigned int on);
+ int (*pre_suspend_check)(void);
+ u32 (*post_chk_wakeup)(void);
+ void (*post_clr_wakeup)(u32 wakeup_src_stat);
+ void (*plt_suspend_init)(void);
+};
+
+struct platform_suspend {
+ int suspend_state;
+ struct suspend_ops *ops;
+};
+
+extern int mmp_platform_suspend_register(struct platform_suspend *plt_suspend);
+#endif
diff --git a/marvell/linux/include/soc/asr/power_domain_isp.h b/marvell/linux/include/soc/asr/power_domain_isp.h
new file mode 100644
index 0000000..d52b89e
--- /dev/null
+++ b/marvell/linux/include/soc/asr/power_domain_isp.h
@@ -0,0 +1,11 @@
+#ifndef _POWER_DOMAIN_ISP_H
+#define _POWER_DOMAIN_ISP_H
+/*
+ * gc, vpu, isp will access the same regsiter to pwr on/off,
+ * add spinlock to protect the sequence
+ */
+extern spinlock_t gc_vpu_isp_pwr_lock;
+
+int isp_pwr_ctrl(void *dev, int on);
+
+#endif
diff --git a/marvell/linux/include/soc/asr/pxa168.h b/marvell/linux/include/soc/asr/pxa168.h
new file mode 100644
index 0000000..6dfe36a
--- /dev/null
+++ b/marvell/linux/include/soc/asr/pxa168.h
@@ -0,0 +1,135 @@
+#ifndef __ASM_MACH_PXA168_H
+#define __ASM_MACH_PXA168_H
+
+extern void pxa168_timer_init(void);
+extern void __init icu_init_irq(void);
+extern void __init pxa168_init_irq(void);
+extern void pxa168_restart(char, const char *);
+extern void pxa168_clear_keypad_wakeup(void);
+
+#include <linux/i2c.h>
+#include <linux/i2c/pxa-i2c.h>
+#include <soc/asr/devices.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
+#include <video/pxa168fb.h>
+#include <linux/platform_data/keypad-pxa27x.h>
+#include <linux/cputype.h>
+#include <linux/pxa168_eth.h>
+#include <linux/platform_data/mv_usb.h>
+
+extern struct pxa_device_desc pxa168_device_uart1;
+extern struct pxa_device_desc pxa168_device_uart2;
+extern struct pxa_device_desc pxa168_device_uart3;
+extern struct pxa_device_desc pxa168_device_twsi0;
+extern struct pxa_device_desc pxa168_device_twsi1;
+extern struct pxa_device_desc pxa168_device_pwm1;
+extern struct pxa_device_desc pxa168_device_pwm2;
+extern struct pxa_device_desc pxa168_device_pwm3;
+extern struct pxa_device_desc pxa168_device_pwm4;
+extern struct pxa_device_desc pxa168_device_ssp1;
+extern struct pxa_device_desc pxa168_device_ssp2;
+extern struct pxa_device_desc pxa168_device_ssp3;
+extern struct pxa_device_desc pxa168_device_ssp4;
+extern struct pxa_device_desc pxa168_device_ssp5;
+extern struct pxa_device_desc pxa168_device_nand;
+extern struct pxa_device_desc pxa168_device_fb;
+extern struct pxa_device_desc pxa168_device_keypad;
+extern struct pxa_device_desc pxa168_device_eth;
+
+/* pdata can be NULL */
+extern int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata);
+
+
+extern struct platform_device pxa168_device_gpio;
+
+static inline int pxa168_add_uart(int id)
+{
+ struct pxa_device_desc *d = NULL;
+
+ switch (id) {
+ case 1: d = &pxa168_device_uart1; break;
+ case 2: d = &pxa168_device_uart2; break;
+ case 3: d = &pxa168_device_uart3; break;
+ }
+
+ if (d == NULL)
+ return -EINVAL;
+
+ return pxa_register_device(d, NULL, 0);
+}
+
+static inline int pxa168_add_twsi(int id, struct i2c_pxa_platform_data *data,
+ struct i2c_board_info *info, unsigned size)
+{
+ struct pxa_device_desc *d = NULL;
+ int ret;
+
+ switch (id) {
+ case 0: d = &pxa168_device_twsi0; break;
+ case 1: d = &pxa168_device_twsi1; break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = i2c_register_board_info(id, info, size);
+ if (ret)
+ return ret;
+
+ return pxa_register_device(d, data, sizeof(*data));
+}
+
+static inline int pxa168_add_pwm(int id)
+{
+ struct pxa_device_desc *d = NULL;
+
+ switch (id) {
+ case 1: d = &pxa168_device_pwm1; break;
+ case 2: d = &pxa168_device_pwm2; break;
+ case 3: d = &pxa168_device_pwm3; break;
+ case 4: d = &pxa168_device_pwm4; break;
+ default:
+ return -EINVAL;
+ }
+
+ return pxa_register_device(d, NULL, 0);
+}
+
+static inline int pxa168_add_ssp(int id)
+{
+ struct pxa_device_desc *d = NULL;
+
+ switch (id) {
+ case 1: d = &pxa168_device_ssp1; break;
+ case 2: d = &pxa168_device_ssp2; break;
+ case 3: d = &pxa168_device_ssp3; break;
+ case 4: d = &pxa168_device_ssp4; break;
+ case 5: d = &pxa168_device_ssp5; break;
+ default:
+ return -EINVAL;
+ }
+ return pxa_register_device(d, NULL, 0);
+}
+
+static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
+{
+ return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
+}
+
+static inline int pxa168_add_fb(struct pxa168fb_mach_info *mi)
+{
+ return pxa_register_device(&pxa168_device_fb, mi, sizeof(*mi));
+}
+
+static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
+{
+ if (cpu_is_pxa168())
+ data->clear_wakeup_event = pxa168_clear_keypad_wakeup;
+
+ return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
+}
+
+static inline int pxa168_add_eth(struct pxa168_eth_platform_data *data)
+{
+ return pxa_register_device(&pxa168_device_eth, data, sizeof(*data));
+}
+#endif /* __ASM_MACH_PXA168_H */
diff --git a/marvell/linux/include/soc/asr/pxa1928_ddrtable.h b/marvell/linux/include/soc/asr/pxa1928_ddrtable.h
new file mode 100644
index 0000000..02fc7a2
--- /dev/null
+++ b/marvell/linux/include/soc/asr/pxa1928_ddrtable.h
@@ -0,0 +1,49 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/pxa1928_ddrtable.h
+ *
+ * Copyright: (C) 2013 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+
+#ifndef __PXA1928_DDRTABLE_H__
+#define __PXA1928_DDRTABLE_H__
+
+struct ddr_regtbl {
+ u32 reg;
+ u32 b2c;
+ u32 b2s;
+};
+
+struct ddr_regtbl_info {
+ u32 array_size;
+ u32 timing_cnt;
+};
+
+enum ddr_regtbl_type {
+ DDR_TYPE_MT42L256M = 0,
+ DDR_TYPE_LPDDR3 = 1,
+ DDR_TYPE_INVALID = 255,
+};
+
+extern struct ddr_regtbl *mt42l256m32d2lg18_array[];
+extern struct ddr_regtbl *lpddr3_array[];
+
+extern void pxa1928_ddrhwt_select_array(u32 ind);
+extern int pxa1928_ddrhwt_get_freqnr(void);
+extern int pxa1928_ddrhwt_get_timingcnt(void);
+extern void pxa1928_ddrhwt_lpddr2_h2l(u32 *dmcu, struct ddr_regtbl *newtiming,
+ u32 timing_cnt, u32 table_index);
+extern void pxa1928_ddrhwt_lpddr2_l2h(u32 *dmcu, struct ddr_regtbl *newtiming,
+ u32 timing_cnt, u32 table_index);
+extern void pxa1928_register_table_lpddr2_dll_calibration(u32 *dmcu);
+extern void pxa1928_enable_lpm_ddrdll_recalibration(void);
+extern void pxa1928_ddrhwt_lpddr2_h2l_lowfreq(u32 *dmcu,
+ struct ddr_regtbl *newtiming, u32 timing_cnt, u32 table_index);
+extern void pxa1928_ddrhwt_lpddr2_l2h_lowfreq(u32 *dmcu,
+ struct ddr_regtbl *newtiming, u32 timing_cnt, u32 table_index);
+#endif
diff --git a/marvell/linux/include/soc/asr/pxa1928_lowpower.h b/marvell/linux/include/soc/asr/pxa1928_lowpower.h
new file mode 100644
index 0000000..45b7a46
--- /dev/null
+++ b/marvell/linux/include/soc/asr/pxa1928_lowpower.h
@@ -0,0 +1,116 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/pxa1928_lowpower.h
+ *
+ * Copyright: (C) 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MMP_MACH_PXA1928_LOWPOWER_H__
+#define __MMP_MACH_PXA1928_LOWPOWER_H__
+
+/* APMU regs offset */
+/* Core power mode configuration */
+#define CORE0_PWRMODE 0x280
+#define CORE1_PWRMODE 0x284
+#define CORE2_PWRMODE 0x288
+#define CORE3_PWRMODE 0x28c
+
+/* CORE RSTCTRL */
+#define CORE0_RSTCTRL 0x2a0
+#define CORE1_RSTCTRL 0x2a4
+#define CORE2_RSTCTRL 0x2a8
+#define CORE3_RSTCTRL 0x2ac
+
+/* APSS power mode configuration */
+#define APPS_PWRMODE 0x2c0
+
+/* wake up mask */
+#define WKUP_MASK 0x2c8
+
+/* MPMU regs offset */
+#define APCR 0x1000
+
+/* ICU regs offset */
+#define CORE0_CA7_GLB_IRQ_MASK 0x114
+#define CORE1_CA7_GLB_IRQ_MASK 0x1d8
+#define CORE2_CA7_GLB_IRQ_MASK 0x208
+#define CORE3_CA7_GLB_IRQ_MASK 0x238
+
+#define CORE0_CA7_GLB_FIQ_MASK 0x110
+#define CORE1_CA7_GLB_FIQ_MASK 0x190
+#define CORE2_CA7_GLB_FIQ_MASK 0x1f0
+#define CORE3_CA7_GLB_FIQ_MASK 0x220
+
+/* bits definition */
+#define ICU_MASK (1 << 0)
+
+#define PMUA_SW_WAKEUP (0x1 << 16)
+#define PMUA_APCORESS_MP1 (0x2 << 8)
+#define PMUA_APCORESS_MP2 (0x3 << 8)
+#define PMUA_L2SR_PWROFF_VT (0x1 << 4)
+#define PMUA_CPU_PWRMODE_C1 (0x1 << 0)
+#define PMUA_CPU_PWRMODE_C2 (0x3 << 0)
+
+#define PMUA_CORE_PWRMODE (3 << 0)
+#define PMUA_CORESS_PWRMODE (3 << 8)
+#define PMUA_GIC_IRQ_GLOBAL_MASK (1 << 12)
+#define PMUA_GIC_FIQ_GLOBAL_MASK (1 << 13)
+
+#define PMUA_LCD_REFRESH_EN (1 << 4)
+#define PMUA_APPS_D0CG (0x1 << 0)
+#define PMUA_APPS_D1D2 (0x2 << 0)
+#define PMUA_APPS_PWRMODE_MSK (0x3 << 0)
+#define PMUM_APCR_BASE 0xBE000000
+#define PMUM_APCR_MASK 0x1E000
+#define PMUM_INTCLR (1 << 24)
+#define PMUM_VCTCXOSD (1 << 19)
+
+#define PMUA_CP_IPC (1 << 31)
+#define PMUA_PMIC (1 << 29)
+#define PMUA_USB (1 << 28)
+#define PMUA_AUDIO (1 << 26)
+#define PMUA_GPIO (1 << 25)
+#define PMUA_SSP2 (1 << 21)
+#define PMUA_SSP1 (1 << 20)
+#define PMUA_SDH2 (1 << 17)
+#define PMUA_SDH1 (1 << 16)
+#define PMUA_KEYPAD (1 << 14)
+#define PMUA_TRACKBALL (1 << 13)
+#define PMUA_ROTARYKEY (1 << 12)
+#define PMUA_RTC_ALARM (1 << 11)
+#define PMUA_WTD_TIMER_2 (1 << 10)
+#define PMUA_WTD_TIMER_1 (1 << 9)
+#define PMUA_TIMER_2_3 (1 << 5)
+#define PMUA_TIMER_2_2 (1 << 4)
+#define PMUA_TIMER_2_1 (1 << 3)
+#define PMUA_TIMER_1_3 (1 << 2)
+#define PMUA_TIMER_1_2 (1 << 1)
+#define PMUA_TIMER_1_1 (1 << 0)
+
+#if defined(CONFIG_PXA1928_SOC_TIMER1)
+#define PMUA_TIMER_WK_MSK PMUA_TIMER_1_1
+#elif defined(CONFIG_PXA1928_SOC_TIMER2)
+#define PMUA_TIMER_WK_MSK PMUA_TIMER_2_1
+#else
+#define PMUA_TIMER_WK_MSK PMUA_TIMER_1_1
+#endif
+
+#ifndef __ASSEMBLER__
+
+enum pxa1928_lowpower_state {
+ POWER_MODE_CORE_INTIDLE, /* used for C1 */
+ POWER_MODE_CORE_POWERDOWN, /* used for C2 */
+ POWER_MODE_APPS_IDLE, /* used for D1P */
+ POWER_MODE_APPS_SLEEP, /* used for non-udr apps sleep, D1 */
+ POWER_MODE_UDR_VCTCXO, /* used for udr with vctcxo, D2 */
+ POWER_MODE_UDR, /* used for udr D2, suspend */
+ POWER_MODE_MAX = 15, /* maximum lowpower states */
+};
+
+extern void __iomem *pxa1928_icu_get_base_addr(void);
+extern void ca7_power_up_setup(unsigned int);
+#endif
+#endif
diff --git a/marvell/linux/include/soc/asr/pxa910.h b/marvell/linux/include/soc/asr/pxa910.h
new file mode 100644
index 0000000..2495a1c
--- /dev/null
+++ b/marvell/linux/include/soc/asr/pxa910.h
@@ -0,0 +1,88 @@
+#ifndef __ASM_MACH_PXA910_H
+#define __ASM_MACH_PXA910_H
+
+extern void pxa910_timer_init(void);
+extern void __init icu_init_irq(void);
+extern void __init pxa910_init_irq(void);
+
+#include <linux/i2c.h>
+#include <linux/i2c/pxa-i2c.h>
+#include <soc/asr/devices.h>
+#include <linux/platform_data/mtd-nand-pxa3xx.h>
+#include <video/mmp_disp.h>
+
+extern struct pxa_device_desc pxa910_device_uart1;
+extern struct pxa_device_desc pxa910_device_uart2;
+extern struct pxa_device_desc pxa910_device_twsi0;
+extern struct pxa_device_desc pxa910_device_twsi1;
+extern struct pxa_device_desc pxa910_device_pwm1;
+extern struct pxa_device_desc pxa910_device_pwm2;
+extern struct pxa_device_desc pxa910_device_pwm3;
+extern struct pxa_device_desc pxa910_device_pwm4;
+extern struct pxa_device_desc pxa910_device_nand;
+extern struct pxa_device_desc pxa910_device_u2o;
+extern struct pxa_device_desc pxa910_device_u2ootg;
+extern struct pxa_device_desc pxa910_device_u2oehci;
+extern struct pxa_device_desc pxa910_device_u2ophy;
+extern struct pxa_device_desc pxa910_device_disp;
+extern struct pxa_device_desc pxa910_device_fb;
+extern struct pxa_device_desc pxa910_device_panel;
+extern struct platform_device pxa910_device_gpio;
+extern struct platform_device pxa910_device_rtc;
+
+static inline int pxa910_add_uart(int id)
+{
+ struct pxa_device_desc *d = NULL;
+
+ switch (id) {
+ case 1: d = &pxa910_device_uart1; break;
+ case 2: d = &pxa910_device_uart2; break;
+ }
+
+ if (d == NULL)
+ return -EINVAL;
+
+ return pxa_register_device(d, NULL, 0);
+}
+
+static inline int pxa910_add_twsi(int id, struct i2c_pxa_platform_data *data,
+ struct i2c_board_info *info, unsigned size)
+{
+ struct pxa_device_desc *d = NULL;
+ int ret;
+
+ switch (id) {
+ case 0: d = &pxa910_device_twsi0; break;
+ case 1: d = &pxa910_device_twsi1; break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = i2c_register_board_info(id, info, size);
+ if (ret)
+ return ret;
+
+ return pxa_register_device(d, data, sizeof(*data));
+}
+
+static inline int pxa910_add_pwm(int id)
+{
+ struct pxa_device_desc *d = NULL;
+
+ switch (id) {
+ case 1: d = &pxa910_device_pwm1; break;
+ case 2: d = &pxa910_device_pwm2; break;
+ case 3: d = &pxa910_device_pwm3; break;
+ case 4: d = &pxa910_device_pwm4; break;
+ default:
+ return -EINVAL;
+ }
+
+ return pxa_register_device(d, NULL, 0);
+}
+
+static inline int pxa910_add_nand(struct pxa3xx_nand_platform_data *info)
+{
+ return pxa_register_device(&pxa910_device_nand, info, sizeof(*info));
+}
+#endif /* __ASM_MACH_PXA910_H */
diff --git a/marvell/linux/include/soc/asr/ramdump.h b/marvell/linux/include/soc/asr/ramdump.h
new file mode 100644
index 0000000..d48c557
--- /dev/null
+++ b/marvell/linux/include/soc/asr/ramdump.h
@@ -0,0 +1,120 @@
+/*
+ * linux/arch/arm/mach-mmp/ramdump.h
+ *
+ * Support for the Marvell PXA RAMDUMP error handling capability.
+ *
+ * Author: Anton Eidelman (anton.eidelman@marvell.com)
+ * Created: May 20, 2010
+ * Copyright: (C) Copyright 2006 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+#ifndef _RAMDUMP_H
+#define _RAMDUMP_H
+
+#include <linux/ptrace.h> /*pt_regs*/
+
+/*
+ * Error_id values:
+ * [0xffff..0] is used for ARM die() err codes, see fault.c/trapc.c
+ */
+#define RAMDUMP_ERR_EEH_CP 0x80000000
+#define RAMDUMP_ERR_EEH_AP 0x80000100
+#define RAMDUMP_ERR_NONE 0x8FFFFFFF
+
+void ramdump_save_dynamic_context(const char *str, int err,
+ struct thread_info *thread, struct pt_regs *regs);
+void ramdump_save_panic_text(const char *str);
+void ramdump_prepare_in_advance(void);
+void ramdump_rdc_reset(void);
+void ramdump_panic(void);
+#define RAMDUMP_ERR_STR_LEN 100
+
+/* RAMFILE related definitions and functions */
+
+/* RAMFILE object descriptor */
+#define RAMFILE_PHYCONT 1 /* physical memory is continuous (kmalloc) */
+struct ramfile_desc {
+ unsigned next; /* next object (pa) or NULL */
+ unsigned payload_size; /* bytes, excluding this header */
+ unsigned flags;
+ unsigned vaddr; /* virtual start address for discontinous case */
+ unsigned vaddr_hi; /* upper 32 bit of the above, which is misaligned */
+ unsigned reserved[3];
+};
+
+int ramdump_attach_ramfile(struct ramfile_desc *desc);
+
+
+/* RDI related definitions and functions */
+enum rdi_type {
+ RDI_NONE, /* End of list */
+ RDI_CBUF, /* virtual addr, size, opt current idx/ptr; refs supported */
+ RDI_PBUF, /* physical addr, size in bytes; no refs */
+ RDI_CUST, /* Custom: no 1st level parser for this */
+};
+
+/* Attrbits: OR these: for each data word tells if it's an address or a value */
+#define RDI_ATTR_VAL(wordnum) (0<<(wordnum))
+#define RDI_ATTR_ADDR(wordnum) (1<<(wordnum))
+
+/*
+ * RDI (data item) generic object attachment:
+ * type: for unknown types rdp will just print the data words suplied;
+ * name: string used by rdp as filename, at most MAX_RDI_NAME chars;
+ * attrbits: 1 bit per data word, 0=value, 1=address of a value;
+ * Callers can assume "value" is the default (0).
+ * nwords: number of data words, max 16;
+ * unsigned long data elements follow (32-bit or 64-bit)
+ */
+int ramdump_attach_item(enum rdi_type type,
+ const char *name,
+ unsigned attrbits,
+ unsigned nwords, ...);
+
+/*
+ * Buffer (RDI_CBUF) type RDI object attachment:
+ * name: string used by rdp as filename, at most MAX_RDI_NAME chars;
+ * buf: address of the pointer to the buffer;
+ * buf_size: address of an unsigned containing buffer size;
+ * OR an address of a pointer to the buffer end;
+ * rdp will automatically figure out which;
+ * cur_ptr: address of a pointer to the current byte inside the buffer;
+ * OR an address of an unsigned containing the current byte index;
+ * OR an address of an unsigned containing the total byte count
+ * (with no wrap-around);
+ * rdp will automatically figure out which;
+ * unit: unit buf_size (and cur_ptr if is an index) are expressed in.
+ */
+static inline
+int ramdump_attach_cbuffer(const char *name,
+ void **buf,
+ unsigned *buf_size,
+ unsigned *cur_ptr,
+ unsigned unit)
+{
+ return ramdump_attach_item(RDI_CBUF, name,
+ RDI_ATTR_ADDR(0) | RDI_ATTR_ADDR(1)
+ | RDI_ATTR_ADDR(2), 4,
+ (unsigned long)buf, (unsigned long)buf_size,
+ (unsigned long)cur_ptr, (unsigned long)unit);
+}
+
+static inline
+int ramdump_attach_pbuffer(const char *name,
+ unsigned buf_physical,
+ unsigned buf_size)
+{
+ return ramdump_attach_item(RDI_PBUF, name,
+ RDI_ATTR_VAL(0) | RDI_ATTR_VAL(1), 2,
+ (unsigned)buf_physical, (unsigned)buf_size);
+}
+
+/* Configuration */
+#define RAMDUMP_PHASE_1_1 /* allow KO's to work with older kernel */
+#define RAMDUMP_RDI /* allow detecting RDI interface is present */
+
+#endif
diff --git a/marvell/linux/include/soc/asr/ramdump_defs.h b/marvell/linux/include/soc/asr/ramdump_defs.h
new file mode 100644
index 0000000..bd63790
--- /dev/null
+++ b/marvell/linux/include/soc/asr/ramdump_defs.h
@@ -0,0 +1,167 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/ramdump_defs.h
+ *
+ * Support for the Marvell PXA RAMDUMP error handling capability.
+ *
+ * Author: Anton Eidelman (anton.eidelman@marvell.com)
+ * Created: May 20, 2010
+ * Copyright: (C) Copyright 2006 Marvell International Ltd.
+ *
+ */
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef ARCH_ARM_MACH_PXA_RAMDUMP_DEFS_H
+#define ARCH_ARM_MACH_PXA_RAMDUMP_DEFS_H
+
+/*
+ * Types for 32/64-bit architectures support.
+ * T_PTR: used below for objects that are pointers, for which
+ * we do not want to allocate 64-bit on all architectures.
+ * In native arm code these can be (unsigned long),
+ * however when compiled inside parser tools on host, this
+ * may result in a mismatch. Host build can redefine T_PTR to avoid this.
+ *
+ * u64: used below for objects that are always allocated 64-bit.
+ * For example, pointers inside RDC structure, because we do not want
+ * to compile two instances of RDC for 32- and 64-bit in the parser tools.
+ * u64 may need to be defined in the host builds.
+ */
+#define T_PTR unsigned long
+
+/************************************************************************/
+/* RAMDUMP definitions */
+/************************************************************************/
+/* RDC header is at fixed address adjacent to the top of DDR space */
+#define RDC_SIGNATURE 0x41434452 /* ascii(RDCA), little endian */
+#define RDC_OFFSET 0x002FFC00 /* from CP area start */
+#define ISRAM_PA 0x5c000000
+
+#define DDR0_BASE 0x00000000
+#define DDR1_BASE 0x40000000
+#define CP_AREA_SIZE 0x01000000 /* fixed top 16MB of bank 0 */
+#define CP_ADDRESS(ddr0_size) (DDR0_BASE+(ddr0_size)-CP_AREA_SIZE)
+#define RDC_ADDRESS(ddr0_size) (CP_ADDRESS(ddr0_size)+RDC_OFFSET)
+
+/* ISRAM dump is located before RDC header. More objects can be added here.
+ Not included into the struct rdc_area as the size of isram and
+ other objects might not be known at compile time.
+ Macro's below may use function calls or variable references.*/
+#define RDC_ISRAM_START(header, isram_size) \
+ ((void *)(((unsigned long)header)-isram_size))
+
+/* Data Item objects in RDC */
+#define MAX_RDI_NAME 8
+struct rdc_dataitem {
+ unsigned char size; /* total bytes to the next item */
+ unsigned char type; /* one of enum rdc_di_type */
+ unsigned short attrbits;/* bit per body element, lsb first */
+ char name[MAX_RDI_NAME];/* 8-char ascii item name */
+ union {
+ unsigned w[1]; /* contents: not aligned to 64-bit */
+ } body;
+};
+
+struct kallsyms_record {
+ T_PTR kallsyms_addresses;
+ T_PTR kallsyms_names;
+ unsigned kallsyms_num_syms;
+ T_PTR kallsyms_token_table;
+ T_PTR kallsyms_token_index;
+ T_PTR kallsyms_markers;
+};
+
+/* RDC: the location is fixed at RDC_ADDRESS. Size is 1KB. */
+struct rdc_area {
+ struct rdc_header {
+ unsigned signature;
+ unsigned kernel_build_id;
+ unsigned error_id;
+ unsigned reserved[5];
+ unsigned ramdump_data_addr; /* physical addr of ramdump_data */
+ unsigned isram_pa; /* physical addr of ISRAM dump */
+ unsigned isram_size; /* size of ISRAM dump */
+ unsigned isram_crc32; /* verify contents survived flush/reset */
+ unsigned ramfile_addr; /* physical addr of the first or NULL */
+ /* mipsram is here so it can be extracted w/o symbol table */
+ unsigned mipsram_pa; /* physical addr of mipsram buffer */
+ unsigned mipsram_size; /* size of mipsram buffer */
+ unsigned ddr_bank0_size; /* for future use in RDP */
+ unsigned pgd; /* init_mm.pgd pa: translate vmalloc addresses */
+ unsigned kallsyms; /* VA of struct kallsyms_record */
+ unsigned kallsyms_hi; /* upper 32 bit of the above */
+ unsigned kernel_build_id_hi; /* upper 32 bit of the above */
+ unsigned reserved1[12]; /* Up to offset 0x80 */
+ } header;
+ union { /*upto 1KB*/
+ unsigned char space[0x400-sizeof(struct rdc_header)];
+ struct rdc_dataitem rdi[1];
+ } body;
+};
+
+/* use this for debug and memory consistency checking.
+ Note: CRC32 no 2-s complement option is used */
+#define RAMDUMP_ISRAM_CRC_CHECK
+
+#endif
diff --git a/marvell/linux/include/soc/asr/ramdump_miscdevice.h b/marvell/linux/include/soc/asr/ramdump_miscdevice.h
new file mode 100755
index 0000000..8e32a33
--- /dev/null
+++ b/marvell/linux/include/soc/asr/ramdump_miscdevice.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright: (C) Copyright 2015 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ * Author: Yan Markman (ymarkman@marvell.com)
+ *
+ * RAMDUMP Devices are for System Debug ErrorHandling and Health Management
+ * Working MISC-Devices may be stack whilst working but RAMDUMP-devices
+ * must be always ok to guaranty system recovery and logging.
+ *
+ * Do not use MISC-Device for RAMDUMPs but use own
+ * Major-Node-Number for them. The devices are still "char"
+ *
+ * An alternation depends upon ALTERNATE_MISC_TO_SYSDBG
+ */
+
+#ifndef _RAMDUMP_MISCDEVICE_H
+#define _RAMDUMP_MISCDEVICE_H
+
+#include <linux/miscdevice.h>
+
+#define ALTERNATE_MISC_TO_SYSDBG
+
+#if !defined(_RAMDUMP_UTIL_C)
+#ifdef ALTERNATE_MISC_TO_SYSDBG
+#define misc_register sysdbg_misc_register
+#define misc_deregister sysdbg_misc_deregister
+#endif
+#endif
+
+extern int sysdbg_misc_register(struct miscdevice * misc);
+extern int sysdbg_misc_deregister(struct miscdevice * misc);
+
+#endif/*_RAMDUMP_MISCDEVICE_H*/
diff --git a/marvell/linux/include/soc/asr/ramdump_util.h b/marvell/linux/include/soc/asr/ramdump_util.h
new file mode 100755
index 0000000..b106f4d
--- /dev/null
+++ b/marvell/linux/include/soc/asr/ramdump_util.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright: (C) Copyright 2015 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ * Author: Yan Markman (ymarkman@marvell.com)
+ *
+ * Utilities for ramdump.c debug capability extension:
+ * - Kernel-RO CRC16 check and reporting on panic
+ */
+
+#ifndef _RAMDUMP_UTIL_H
+#define _RAMDUMP_UTIL_H
+
+
+/* Configuration */
+#define RAMDUMP_PHASE_1_1 /* allow KO's to work with older kernel */
+#define RAMDUMP_RDI /* allow detecting RDI interface is present */
+
+/* EXPORT from ramdump.c; "internal" between ramdump and ramdump_util */
+extern unsigned ramdump_level;
+/* 0: do not request ramdump at all
+ * 1: for panic only, ignore User-Space fatal signals and modems
+ * (used on "reboot" Graceful Shutdown)
+ * 2: always ramdump
+ * >2: same as 2, just for better debug
+ */
+#define RAMDUMP_LEVEL_PANIC_ONLY 1
+#define RAMDUMP_LEVEL_FULL 2
+#define RAMDUMP_LEVEL_FULL_IN_ADVANCE 3
+
+int get_kernel_text_crc16_valid(void); /* returns:
+*** 0 if OK, -1 if bad-crc, -2 if not accounted */
+int get_kernel_text_crc16_threaded_req(void); /* runs on thread */
+u16 get_kernel_text_crc16_on_panic(void); /* has huge blocking latency */
+void ramdump_ignore_fatal_signals(int on_shutdown);
+
+#endif/*_RAMDUMP_UTIL_H*/
diff --git a/marvell/linux/include/soc/asr/regs-accu.h b/marvell/linux/include/soc/asr/regs-accu.h
new file mode 100644
index 0000000..61260d4
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-accu.h
@@ -0,0 +1,107 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-accu.h
+ *
+ * Application Clock Control Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_ACCU_H
+#define __ASM_MACH_REGS_ACCU_H
+
+/*
+ * ACCU register offsets for PXA1986
+ */
+#define ACCU_FABRIC_N1_CLK_CNTRL_REG (0x004)
+#define ACCU_APPS_MDMA_CLK_CNTRL_REG (0x00C)
+#define ACCU_APPS_STM_CLK_CNTRL_REG (0x010)
+#define ACCU_APPS_IC_CLK_CNTRL_REG (0x014)
+#define ACCU_WTM_MAIN_CLK_CNTRL_REG (0x018)
+#define ACCU_WTM_CORE_CLK_CNTRL_REG (0x01C)
+#define ACCU_WTM_CORE_BUS_CLK_CNTRL_REG (0x020)
+#define ACCU_FABRIC_N2_CLK_CNTRL_REG (0x030)
+#define ACCU_VID_DEC_CLK_CNTRL_REG (0x034)
+#define ACCU_VID_ENC_CLK_CNTRL_REG (0x038)
+#define ACCU_FABRIC_N3_CLK_CNTRL_REG (0x040)
+#define ACCU_USB_CLK_CNTRL_REG (0x044)
+#define ACCU_HSIC_CLK_CNTRL_REG (0x048)
+#define ACCU_NAND_CLK_CNTRL_REG (0x04C)
+#define ACCU_FABRIC_N4_CLK_CNTRL_REG (0x058)
+#define ACCU_APPS_INT_SRAM_CLK_CNTRL_REG (0x05C)
+#define ACCU_VDMA_CLK_CNTRL_REG (0x060)
+#define ACCU_CI1_CCIC_CLK_CNTRL_REG (0x064)
+#define ACCU_CI2_CCIC_CLK_CNTRL_REG (0x068)
+#define ACCU_ISP_CLK_CNTRL_REG (0x06C)
+#define ACCU_DISPLAY1_CLK_CNTRL_REG (0x074)
+#define ACCU_DISPLAY2_CLK_CNTRL_REG (0x078)
+#define ACCU_DISPLAY_UNIT_CLK_CNTRL_REG (0x07C)
+#define ACCU_FABRIC_N5_CLK_CNTRL_REG (0x080)
+#define ACCU_GC1_3D_CLK_CNTRL_REG (0x084)
+#define ACCU_GC2_3D_CLK_CNTRL_REG (0x088)
+#define ACCU_GC_2D_CLK_CNTRL_REG (0x08C)
+#define ACCU_FABRIC_N6_CLK_CNTRL_REG (0x090)
+#define ACCU_APPS_LSP_APB_CLK_CNTRL_REG (0x0A0)
+#define ACCU_APPS_OW_CLK_CNTRL_REG (0x0A4)
+#define ACCU_APPS_PWM01_CLK_CNTRL_REG (0x0A8)
+#define ACCU_APPS_PWM23_CLK_CNTRL_REG (0x0AC)
+#define ACCU_APPS_TIMERS1_CLK_CNTRL_REG (0x0B0)
+#define ACCU_APPS_TIMERS2_CLK_CNTRL_REG (0x0B4)
+#define ACCU_APPS_TIMERS3_CLK_CNTRL_REG (0x0B8)
+#define ACCU_APPS_KP_CLK_CNTRL_REG (0x0C4)
+#define ACCU_APPS_RTC_CLK_CNTRL_REG (0x0C8)
+#define ACCU_APPS_SSP1_CLK_CNTRL_REG (0x0D0)
+#define ACCU_APPS_SSP2_CLK_CNTRL_REG (0x0D4)
+#define ACCU_APPS_I2C1_CLK_CNTRL_REG (0x0DC)
+#define ACCU_APPS_I2C2_CLK_CNTRL_REG (0x0E0)
+#define ACCU_APPS_I2C3_CLK_CNTRL_REG (0x0E4)
+#define ACCU_APPS_I2C4_CLK_CNTRL_REG (0x0E8)
+#define ACCU_APPS_I2C5_CLK_CNTRL_REG (0x0EC)
+#define ACCU_APPS_UART1_CLK_CNTRL_REG (0x0F0)
+#define ACCU_APPS_UART2_CLK_CNTRL_REG (0x0F4)
+#define ACCU_APPS_UART3_CLK_CNTRL_REG (0x0F8)
+#define ACCU_APPS_TEMP_S1_CLK_CNTRL_REG (0x100)
+#define ACCU_APPS_TEMP_S2_CLK_CNTRL_REG (0x104)
+#define ACCU_APPS_TEMP_S3_CLK_CNTRL_REG (0x108)
+#define ACCU_APPS_CORE_B_CLK_CNTRL_REG (0x120)
+#define ACCU_APPS_CORE_B_CLK_CNTRL2_REG (0x124)
+#define ACCU_APPS_CORE_L_CLK_CNTRL_REG (0x12C)
+#define ACCU_APPS_CORE_L_CLK_CNTRL2_REG (0x130)
+#define ACCU_APPS_CORE_TOP_CLK_CNTRL_REG (0x138)
+#define ACCU_APPS_CORE_CS_CLK_CNTRL_REG (0x13C)
+#define ACCU_SDH_BUS_CLK_CNTRL_REG (0x170)
+#define ACCU_SDH_CLK_CNTRL_REG (0x174)
+#define ACCU_HSI_CLK_CNTRL_REG (0x17C)
+
+/* Common ACCU clock register bit definitions */
+#define ACCU_ST_BIT BIT(29)
+#define ACCU_GO_BIT BIT(28)
+
+#define ACCU_AHBCLK BIT(10)
+#define ACCU_APBCLK BIT(9) /* Bus Clock Enable */
+#define ACCU_FNCLK BIT(8) /* Functional Clock Enable */
+
+#define ACCU_AHBRST BIT(2)
+#define ACCU_APBRST BIT(1)
+#define ACCU_RST BIT(0) /* Reset Generation */
+
+/* Functional Clock Selection Mask */
+#define ACCU_RATIO_MASK (0xf << 20)
+#define ACCU_SOURCE_MASK (0x7 << 16)
+
+/* Functional Clock Set */
+#define SET_ACCU_RATIO(x) (((x) & 0xf) << 20)
+#define SET_ACCU_SOURCE(x) (((x) & 0x7) << 16)
+
+/* Functional Clock Get */
+#define GET_ACCU_RATIO(x) ((x & ACCU_RATIO_MASK) >> 20)
+#define GET_ACCU_SOURCE(x) ((x & ACCU_SOURCE_MASK) >> 16)
+
+#define ACCU_GC3D_INTLCLK (1 << 12)
+#define ACCU_GC3D_AHBCLK (1 << 11)
+#define ACCU_GC3D_APBCLK (1 << 10) /* Bus Clock Enable */
+#define ACCU_GC3D_SHADERCLK (1 << 9)
+#define ACCU_GC3D_FNCLK (1 << 8) /* Functional Clock Enable */
+
+#endif /* __ASM_MACH_REGS_ACCU_H */
diff --git a/marvell/linux/include/soc/asr/regs-addr.h b/marvell/linux/include/soc/asr/regs-addr.h
new file mode 100644
index 0000000..1aa1913
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-addr.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 ASR Micro Limited
+ */
+
+#ifndef __REGS_ADDR_H
+#define __REGS_ADDR_H
+
+#include <linux/types.h>
+
+enum {
+ REGS_ADDR_MPMU,
+ REGS_ADDR_APMU,
+ REGS_ADDR_APBC,
+ REGS_ADDR_APBS,
+ REGS_ADDR_CIU,
+ REGS_ADDR_SQU,
+ REGS_ADDR_MCU,
+ REGS_ADDR_ICU,
+ REGS_ADDR_MAX,
+};
+
+void regs_addr_iomap(void);
+phys_addr_t regs_addr_get_pa(unsigned int id);
+void __iomem *regs_addr_get_va(unsigned int id);
+
+#endif
diff --git a/marvell/linux/include/soc/asr/regs-apbc.h b/marvell/linux/include/soc/asr/regs-apbc.h
new file mode 100644
index 0000000..9f17037
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-apbc.h
@@ -0,0 +1,50 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-apbc.h
+ *
+ * Application Peripheral Bus Clock Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_APBC_H
+#define __ASM_MACH_REGS_APBC_H
+
+#include <soc/asr/addr-map.h>
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
+#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
+#define APBC_RST (1 << 2) /* Reset Generation */
+
+#define APBC_POWER_EN (1 << 7) /* Power Enable */
+
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
+
+#define APBC_MMPX_TIMER0 APBC_REG(0x034)
+#define APBC_MMPX_TIMER1 APBC_REG(0x044)
+#define APBC_MMPX_TIMER2 APBC_REG(0x068)
+
+#define APBCP_TICER APBCP_REG(0x030)
+
+#define APBC_MMPX_RTC APBC_REG(0x028)
+
+
+/* Clock Control Register for Generic Counter */
+#define APBC_COUNTER_CLK_SEL APBC_REG(0x64)
+#define FREQ_HW_CTRL 0x1
+#define FREQ_SW_SEL 0x2
+
+/* memory maped registers for generic timers */
+#define CNTCR 0x00 /* Counter Control Register */
+#define CNTCR_EN (1 << 0) /* The counter is enabled */
+#define CNTCR_HDBG (1 << 1) /* Halt on debug */
+
+#define CNTSR 0x04 /* Counter Status Register */
+#define CNTCVLW 0x08 /* Current value of counter[31:0] */
+#define CNTCVUP 0x0C /* Current value of counter[63:32] */
+#define CNTFID0 0x20 /* Base frequency ID */
+
+#endif /* __ASM_MACH_REGS_APBC_H */
diff --git a/marvell/linux/include/soc/asr/regs-apmu.h b/marvell/linux/include/soc/asr/regs-apmu.h
new file mode 100644
index 0000000..6ed021e
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-apmu.h
@@ -0,0 +1,166 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-apmu.h
+ *
+ * Application Subsystem Power Management Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_APMU_H
+#define __ASM_MACH_REGS_APMU_H
+
+#include <soc/asr/addr-map.h>
+
+#if defined(CONFIG_CPU_PXA1986)
+/*
+ * APMU register offsets for PXA1986
+ */
+#define APMU_PCR_0 (0x0000)
+#define APMU_PCR_1 (0x0004)
+#define APMU_PCR_2 (0x0008)
+#define APMU_PCR_3 (0x000C)
+#define APMU_PCR_4 (0x0010)
+#define APMU_PSR (0x0014)
+#define APMU_CORE_RESET_0 (0x0018)
+#define APMU_CORE_RESET_1 (0x001C)
+#define APMU_CORE_RESET_2 (0x0020)
+#define APMU_CORE_RESET_3 (0x0024)
+#define APMU_CORE_RESET_4 (0x0028)
+#define APMU_CORE_STATUS (0x002C)
+#define APMU_SP_IDLE_CFG (0x0030)
+#define APMU_CORE_IDLE_CFG_0 (0x0034)
+#define APMU_CORE_IDLE_CFG_1 (0x0038)
+#define APMU_CORE_IDLE_CFG_2 (0x003C)
+#define APMU_CORE_IDLE_CFG_3 (0x0040)
+#define APMU_RES_FRM_SLP_0 (0x0044)
+#define APMU_RES_FRM_SLP_1 (0x0048)
+#define APMU_RES_FRM_SLP_2 (0x004C)
+#define APMU_RES_FRM_SLP_3 (0x0050)
+#define APMU_AP_CLK_REQ (0x0054)
+#define APMU_AP_CLK_ST (0x0058)
+#define APMU_GPU_PWR_CTRL (0x005C)
+#define APMU_IMG_PWR_CTRL (0x0060)
+#define APMU_USB_PWR_CTRL (0x0064)
+#define APMU_VIDEO_PWR_CTRL (0x0068)
+#define APMU_GPU_PWR_STATUS (0x006C)
+#define APMU_IMG_PWR_STATUS (0x0070)
+#define APMU_USB_PWR_STATUS (0x0074)
+#define APMU_VIDEO_PWR_STATUS (0x0078)
+#define APMU_PWR_ISL_TIMER (0x007C)
+#define APMU_PLL3_CTL_0 (0x0080)
+#define APMU_PLL3_CTL_1 (0x0084)
+#define APMU_PLL3_CTL_2 (0x0088)
+#define APMU_PLL3_CTL_3 (0x008C)
+#define APMU_PLL3_CTL_4 (0x0090)
+#define APMU_CORE_PLL1_CTL_0 (0x0094)
+#define APMU_CORE_PLL1_CTL_1 (0x0098)
+#define APMU_CORE_PLL1_CTL_2 (0x009C)
+#define APMU_CORE_PLL1_CTL_3 (0x00A0)
+#define APMU_CORE_PLL1_CTL_4 (0x00A4)
+#define APMU_PWR_STBL_TIMER (0x00A8)
+#define APMU_POCR (0x00AC)
+#define APMU_SRAM_PWR_DWN (0x00B0)
+#define APMU_GP_LPM_TIMER (0x00B4)
+#define APMU_GP_CORE_TIMER (0x00B8)
+#define APMU_GP_LPI_TIMER (0x00BC)
+#define APMU_VCC_SEL (0x00C8)
+#define APMU_PLL4_CTL_0 (0x00CC)
+#define APMU_PLL4_CTL_1 (0x00D0)
+#define APMU_PLL4_CTL_2 (0x00D4)
+#define APMU_PLL4_CTL_3 (0x00D8)
+#define APMU_PLL4_CTL_4 (0x00DC)
+#define APMU_USB3_PMNG (0x00E0)
+#define APMU_USB3_PSTAT (0x00E4)
+#define AP_WAKEUP_ENABLE_SET (0x00E8)
+#define AP_WAKEUP_ENABLE_CLR (0x00EC)
+#define APMU_TEST_REG (0x00F0)
+#define APMU_CORE_PLL2_CTL_0 (0x00F4)
+#define APMU_CORE_PLL2_CTL_1 (0x00F8)
+#define APMU_CORE_PLL2_CTL_2 (0x00FC)
+#define APMU_CORE_PLL2_CTL_3 (0x0100)
+#define APMU_CORE_PLL2_CTL_4 (0x0104)
+#define APMU_FORCE_CPU_IDLE (0x0108)
+#define APMU_HDMI_PLL_GATE (0x010C)
+#define APMU_SLP_IND_CLR (0x0110)
+#define APMU_CORE_IDLE_ST (0x0114)
+#define APMU_RST_EXIT_1 (0x0118)
+#define APMU_RST_EXIT_2 (0x011C)
+#define APMU_RST_EXIT_3 (0x0120)
+#define APMU_RST_EXIT_4 (0x0124)
+#define APMU_INT_MASK_0 (0x0128)
+#define APMU_INT_MASK_1 (0x012C)
+#define APMU_INT_MASK_2 (0x0130)
+#define APMU_INT_MASK_3 (0x0134)
+#define APMU_WKP_STKY_SEL (0x0138)
+#define APMU_WKP_ST (0x013C)
+
+/* APMU_GPU_PWR_CTRL */
+#define GPU1_3D_PWR_ON BIT(0)
+#define GPU2_3D_PWR_ON BIT(4)
+#define GPU_SS_PWR_ON BIT(8)
+/* APMU_VIDEO_PWR_CTRL */
+#define VIDEO_SS_PWR_ON BIT(0)
+#define ISP_DMA_PWR_ON_OFF BIT(4)
+#define DISPLAY_VDMA_PWR_ON_OFF BIT(8)
+
+/* APMU_IMG_PWR_STATUS */
+#define ISP_DMA_POWER_STATUS BIT(4)
+#define DISPLAY_VDMA_POWER_STATUS BIT(8)
+
+/* APMU_USB_PWR_CTRL */
+#define USB_SS_PWR_ON BIT(0)
+
+#else /* CONFIG_CPU_PXA1986 */
+
+#define APMU_FNCLK_EN (1 << 4)
+#define APMU_AXICLK_EN (1 << 3)
+#define APMU_FNRST_DIS (1 << 1)
+#define APMU_AXIRST_DIS (1 << 0)
+
+/* Wake Clear Register */
+#define APMU_WAKE_CLR APMU_REG(0x07c)
+
+#define APMU_PXA168_KP_WAKE_CLR (1 << 7)
+#define APMU_PXA168_CFI_WAKE_CLR (1 << 6)
+#define APMU_PXA168_XD_WAKE_CLR (1 << 5)
+#define APMU_PXA168_MSP_WAKE_CLR (1 << 4)
+#define APMU_PXA168_SD4_WAKE_CLR (1 << 3)
+#define APMU_PXA168_SD3_WAKE_CLR (1 << 2)
+#define APMU_PXA168_SD2_WAKE_CLR (1 << 1)
+#define APMU_PXA168_SD1_WAKE_CLR (1 << 0)
+
+#define APMU_PXA182X_SD2_WAKE_CLR (1 << 6)
+#define APMU_PXA182X_SD1_WAKE_CLR (1 << 1)
+#define APMU_PXA182X_SD0_WAKE_CLR (1 << 0)
+
+#ifdef CONFIG_CPU_PXA1928
+#define PMUA_APCORESS_MP2 (0x3 << 8)
+#define PMUA_L2SR_PWROFF_VT (0x1 << 4)
+#define PMUA_CPU_PWRMODE_C2 (0x3 << 0)
+
+
+#define APMU_SW_WAKEUP (0x1 << 16)
+
+#define APMU_CORE0_PWRMODE APMU_REG(0x0280)
+#define APMU_CORE1_PWRMODE APMU_REG(0x0284)
+#define APMU_CORE2_PWRMODE APMU_REG(0x0288)
+#define APMU_CORE3_PWRMODE APMU_REG(0x028C)
+#define APMU_CORE0_RSTCTRL APMU_REG(0x02a0)
+#define APMU_CORE1_RSTCTRL APMU_REG(0x02a4)
+#define APMU_CORE2_RSTCTRL APMU_REG(0x02a8)
+#define APMU_CORE3_RSTCTRL APMU_REG(0x02aC)
+
+#define APMU_MC_CLK_RES_CTRL APMU_REG(0x0258)
+#endif /* CONFIG_CPU_PXA1928 */
+
+/* Debug register */
+#define APMU_DEBUG APMU_REG(0x0088)
+#define APMU_CORE_STATUS APMU_REG(0x090)
+
+#define APMU_WAKEUP_CORE(n) (1 << (n & 0x3))
+#define APMU_COREn_WAKEUP_CTL(n) (APMU_REG(0x012c) + 4 * (n & 0x3))
+#endif /* !CONFIG_CPU_PXA1986 */
+
+#endif /* __ASM_MACH_REGS_APMU_H */
diff --git a/marvell/linux/include/soc/asr/regs-ciu.h b/marvell/linux/include/soc/asr/regs-ciu.h
new file mode 100644
index 0000000..e5d9160
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-ciu.h
@@ -0,0 +1,60 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-ciu.h
+ *
+ * CPU Interface Unit Registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_CIU_H
+#define __ASM_MACH_REGS_CIU_H
+
+#include <soc/asr/addr-map.h>
+
+#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00)
+#define CIU_REG(x) (CIU_VIRT_BASE + (x))
+
+#if defined(CONFIG_CPU_ASR18XX) || defined(CONFIG_CPU_ASR1901)
+#define CIU_CHIP_ID CIU_REG(0x0000)
+#define CIU_SEAGULL_CPU_CONF CIU_REG(0x0004)
+#define CIU_SEAGULL_CPU_SRAM_SPD CIU_REG(0x000c)
+#define CIU_SEAGULL_CPU_L2C_SRAM_SPD CIU_REG(0x0014)
+#define CIU_SYS_BOOT_CNTRL CIU_REG(0x0020)
+#define CIU_SW_BRANCH_ADDR CIU_REG(0x0024)
+#define CIU_PERF_COUNT2 CIU_REG(0x003c)
+#define CIU_MC_CONF CIU_REG(0x0040)
+#define CIU_CS_CONF CIU_REG(0x004c)
+#define CIU_CS_DEBUG_CONF CIU_REG(0x0050)
+#define CIU_MCB_CONFIG2_REG CIU_REG(0x008c)
+#define CIU_DDR_PHY_TST_CONFIG_REG CIU_REG(0x0090)
+#define CIU_DDR_PHY_TST_SEED_REG CIU_REG(0x0094)
+#define CIU_DDR_PHY_TST_SIGNATURE_REG CIU_REG(0x0098)
+#define CIU_DDR_PHY_TST_STATUS_REG CIU_REG(0x009c)
+#define CIU_GPU2D_XTC_REG CIU_REG(0x00a0)
+#define CIU_GPU_XTC_REG CIU_REG(0x00a4)
+#define CIU_VPU_XTC_REG CIU_REG(0x00a8)
+#define CIU_CPU_CONF_ADDR_FILTER CIU_REG(0x00b0)
+#define CIU_CPU_CONF_L2C CIU_REG(0x00b4)
+#define CIU_CPU_CONF_SCU CIU_REG(0x00b8)
+#define CIU_CPU_CONF_MISC CIU_REG(0x00bc)
+#define CIU_CPU_CONF_CORESIGHT_ROM_ADDR CIU_REG(0x00c0)
+#define CIU_CPU_CONF_CORESIGHT_SELF_ADDR CIU_REG(0x00c4)
+#define CIU_CPU_CONF_SRAM_0 CIU_REG(0x00c8)
+#define CIU_CPU_CONF_SRAM_1 CIU_REG(0x00cc)
+#define CIU_CPU_CORE0_CONF CIU_REG(0x00d0)
+#define CIU_CPU_CORE0_STATUS CIU_REG(0x00d4)
+#define CIU_WARM_RESET_VECTOR CIU_REG(0x00d8)
+#define CIU_CPU_CORE1_CONF CIU_REG(0x00e0)
+#define CIU_CPU_CORE1_STATUS CIU_REG(0x00e4)
+#define CIU_SW_SCRATCH_REG CIU_REG(0x00e8)
+#define CIU_CPU_CORE2_CONF CIU_REG(0x00f0)
+#define CIU_CPU_CORE2_STATUS CIU_REG(0x00f4)
+#define CIU_CPU_CORE3_CONF CIU_REG(0x00f8)
+#define CIU_CPU_CORE3_STATUS CIU_REG(0x00fc)
+//For PXA1822 which has only one core and the offset of CORE CONF is different
+#define CIU_CPU_CA7_CONF CIU_REG(0x00e0)
+#endif
+
+#endif /* __ASM_MACH_REGS_CIU_H */
diff --git a/marvell/linux/include/soc/asr/regs-coresight.h b/marvell/linux/include/soc/asr/regs-coresight.h
new file mode 100644
index 0000000..ef04faa
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-coresight.h
@@ -0,0 +1,108 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-coresight.h
+ *
+ * Author: Neil Zhang <zhangwm@marvell.com>
+ * Copyright: (C) 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_MACH_CORSIGHT_H
+#define __ASM_MACH_CORSIGHT_H
+
+#include <soc/asr/addr-map.h>
+
+#define CORESIGHT_VIRT_BASE (APB_VIRT_BASE + 0x100000)
+
+#if defined(CONFIG_CPU_ASR18XX) || defined(CONFIG_CPU_ASR1901)
+#define ETB_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x5000)
+#define TPIU_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x8000)
+#define CSTF_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x9000)
+#elif defined(CONFIG_CPU_PXA1928)
+#define ETB_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x20000)
+#define CSS_CTI1_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x21000)
+#define TPIU_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x22000)
+/* core funnel */
+#define CORE_FUN_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x23000)
+/* coresight subsystem funnel */
+#define CSTF_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x24000)
+#define CSS_ITM_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x25000)
+#define TS_READ_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x27000)
+#define TS_CTRL_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x28000)
+#define CSS_CTI2_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x29000)
+#define CSS_CTI3_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x2A000)
+#define DEBUGCCU_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x2B000)
+#define HUBF_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x2C000)
+#define HUBF_FUN_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x2D000)
+#define PML_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x2E000)
+#endif
+
+#define DBG_CORE0_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x10000)
+#define CTI_CORE0_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x18000)
+#define CTI_CORE1_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x19000)
+#define CTI_CORE2_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x1A000)
+#define CTI_CORE3_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x1B000)
+#define PTM_CORE0_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x1C000)
+#define PTM_CORE1_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x1D000)
+#define PTM_CORE2_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x1E000)
+#define PTM_CORE3_VIRT_BASE (CORESIGHT_VIRT_BASE + 0x1F000)
+
+#define ETB_REG(x) (ETB_VIRT_BASE + (x))
+#define TPIU_REG(x) (TPIU_VIRT_BASE + (x))
+#define CSTF_REG(x) (CSTF_VIRT_BASE + (x))
+
+#define ETB_CORE0_VIRT_BASE (CORESIGHT_VIRT_BASE + 0xa000)
+#define LOCAL_ETB_REG(x) ((ETB_CORE0_VIRT_BASE \
+ + 0x1000 * raw_smp_processor_id()) \
+ + (x))
+
+#define PTM_REG(x) ((PTM_CORE0_VIRT_BASE \
+ + 0x1000 * raw_smp_processor_id()) \
+ + (x))
+
+#define CTI_REG(x) ((CTI_CORE0_VIRT_BASE \
+ + 0x1000 * raw_smp_processor_id()) \
+ + (x))
+
+#define ETB_LOCK ETB_REG(0xFB0)
+#define TPIU_LOCK TPIU_REG(0xFB0)
+#define CSTF_LOCK CSTF_REG(0xFB0)
+#define PTM_LOCK PTM_REG(0xFB0)
+#define CTI_LOCK CTI_REG(0xFB0)
+
+#define DBG_REG(cpu, addr) (DBG_CORE0_VIRT_BASE + cpu * 0x2000 + addr)
+
+#define DBG_ID(cpu) DBG_REG(cpu, 0x0)
+#define DBG_DTRRX(cpu) DBG_REG(cpu, 0x80)
+#define DBG_ITR(cpu) DBG_REG(cpu, 0x84) /* Write only */
+#define DBG_PCSR(cpu) DBG_REG(cpu, 0x84) /* Read only */
+#define DBG_DSCR(cpu) DBG_REG(cpu, 0x88)
+#define DBG_DTRTX(cpu) DBG_REG(cpu, 0x8C)
+#define DBG_DRCR(cpu) DBG_REG(cpu, 0x90)
+#define DBG_LAR(cpu) DBG_REG(cpu, 0xFB0)
+
+#define CTI_EN_MASK 0x0F
+#define CTI_CTRL_OFFSET 0x0
+#define CTI_INTACK_OFFSET 0x10
+#define CTI_EN_IN0_OFFSET 0x20
+#define CTI_EN_IN1_OFFSET 0x24
+#define CTI_EN_IN2_OFFSET 0x28
+#define CTI_EN_IN3_OFFSET 0x2C
+#define CTI_EN_IN4_OFFSET 0x30
+#define CTI_EN_IN5_OFFSET 0x34
+#define CTI_EN_IN6_OFFSET 0x38
+#define CTI_EN_IN7_OFFSET 0x3C
+#define CTI_EN_OUT0_OFFSET 0xA0
+#define CTI_EN_OUT1_OFFSET 0xA4
+#define CTI_EN_OUT2_OFFSET 0xA8
+#define CTI_EN_OUT3_OFFSET 0xAC
+#define CTI_EN_OUT4_OFFSET 0xB0
+#define CTI_EN_OUT5_OFFSET 0xB4
+#define CTI_EN_OUT6_OFFSET 0xB8
+#define CTI_EN_OUT7_OFFSET 0xBC
+#define CTI_LOCK_OFFSET 0xFB0
+
+#endif /* __ASM_MACH_CORSIGHT_H */
diff --git a/marvell/linux/include/soc/asr/regs-icu.h b/marvell/linux/include/soc/asr/regs-icu.h
new file mode 100644
index 0000000..2e3774e
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-icu.h
@@ -0,0 +1,196 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-icu.h
+ *
+ * Interrupt Control Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ICU_H
+#define __ASM_MACH_ICU_H
+
+#include <soc/asr/addr-map.h>
+
+#if defined(CONFIG_CPU_PXA1928)
+#define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x84000)
+#else
+#define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
+#endif
+#define ICU_REG(x) (ICU_VIRT_BASE + (x))
+
+#define ICU_INT_CONF(n) ICU_REG((n) << 2)
+#define ICU_INT_CONF_MASK (0xf)
+
+/************ PXA168/PXA910 (MMP) *********************/
+#define ICU_INT_CONF_AP_INT (1 << 6)
+#define ICU_INT_CONF_CP_INT (1 << 5)
+#define ICU_INT_CONF_IRQ (1 << 4)
+
+#define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
+#define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
+#define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
+#define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
+#define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
+
+/************************** MMP2 ***********************/
+
+/*
+ * IRQ0/FIQ0 is routed to SP IRQ/FIQ.
+ * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ.
+ */
+#define ICU_INT_ROUTE_SP_IRQ (1 << 4)
+#define ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
+#define ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
+
+#define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138)
+#define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c)
+#define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140)
+#define MMP2_ICU_PJ4_FIQ_STATUS1 ICU_REG(0x144)
+
+#define MMP2_ICU_INT4_STATUS ICU_REG(0x150)
+#define MMP2_ICU_INT5_STATUS ICU_REG(0x154)
+#define MMP2_ICU_INT17_STATUS ICU_REG(0x158)
+#define MMP2_ICU_INT35_STATUS ICU_REG(0x15c)
+#define MMP2_ICU_INT51_STATUS ICU_REG(0x160)
+
+#define MMP2_ICU_INT4_MASK ICU_REG(0x168)
+#define MMP2_ICU_INT5_MASK ICU_REG(0x16C)
+#define MMP2_ICU_INT17_MASK ICU_REG(0x170)
+#define MMP2_ICU_INT35_MASK ICU_REG(0x174)
+#define MMP2_ICU_INT51_MASK ICU_REG(0x178)
+
+#define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100)
+#define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104)
+#define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108)
+
+#define MMP2_ICU_INVERT ICU_REG(0x164)
+
+#define MMP2_ICU_INV_PMIC (1 << 0)
+#define MMP2_ICU_INV_PERF (1 << 1)
+#define MMP2_ICU_INV_COMMTX (1 << 2)
+#define MMP2_ICU_INV_COMMRX (1 << 3)
+
+#if defined(CONFIG_CPU_PXA1928)
+#define PXA1928_ICU_INT_CONF_AP(n) (1 << (6 + ((n & 0x3) << 1)))
+#define PXA1928_ICU_INT_CONF_AP_MASK (0x55 << 6)
+#define PXA1928_ICU_INT_CONF_PRIO(n) (n & 0xF)
+
+/*
+ * ICU Configuration Register Bit Definitions:
+ * IRQ SP routes to SP IRQ
+ * FIRQ1 routes to CA7-1 FIQ
+ * IRQ1 routes to CA7-1 IRQ
+ * FIRQ2 routes to CA7-2 FIQ
+ * IRQ2 routes to CA7-2 IRQ
+*/
+
+#define ICU_INT_ROUTE_SP_IRQ (1 << 4)
+#define ICU_INT_ROUTE_CA7_1_FIQ (1 << 5)
+#define ICU_INT_ROUTE_CA7_1_IRQ (1 << 6)
+#define ICU_INT_ROUTE_CA7_2_FIQ (1 << 7)
+#define ICU_INT_ROUTE_CA7_2_IRQ (1 << 8)
+#define ICU_INT_ROUTE_CA7_3_FIQ (1 << 9)
+#define ICU_INT_ROUTE_CA7_3_IRQ (1 << 10)
+#define ICU_INT_ROUTE_CA7_4_FIQ (1 << 11)
+#define ICU_INT_ROUTE_CA7_4_IRQ (1 << 12)
+
+#define PXA1928_ICU_IRQ_SP_SEL_INT_NUM ICU_REG(0x100)
+#define PXA1928_ICU_FIQ1_SEL_INT_NUM ICU_REG(0x104)
+#define PXA1928_ICU_IRQ1_SEL_INT_NUM ICU_REG(0x108)
+#define PXA1928_ICU_FIQ2_SEL_INT_NUM ICU_REG(0x18C)
+#define PXA1928_ICU_IRQ2_SEL_INT_NUM ICU_REG(0x1d4)
+
+#define PXA1928_ICU_GBL_IRQ_SP_MSK ICU_REG(0x10C)
+#define PXA1928_ICU_GBL_FIQ1_MSK ICU_REG(0x110)
+#define PXA1928_ICU_GBL_IRQ1_MSK ICU_REG(0x114)
+#define PXA1928_ICU_GBL_FIQ2_MSK ICU_REG(0x190)
+#define PXA1928_ICU_GBL_IRQ2_MSK ICU_REG(0x1d8)
+#define PXA1928_ICU_GBL_FIQ3_MSK ICU_REG(0x1f0)
+#define PXA1928_ICU_GBL_IRQ3_MSK ICU_REG(0x208)
+#define PXA1928_ICU_GBL_FIQ4_MSK ICU_REG(0x220)
+#define PXA1928_ICU_GBL_IRQ4_MSK ICU_REG(0x238)
+
+#define PXA1928_ICU_CORE0_GBL_IRQ_MSK PXA1928_ICU_GBL_IRQ1_MSK
+#define PXA1928_ICU_CORE1_GBL_IRQ_MSK PXA1928_ICU_GBL_IRQ2_MSK
+#define PXA1928_ICU_CORE2_GBL_IRQ_MSK PXA1928_ICU_GBL_IRQ3_MSK
+#define PXA1928_ICU_CORE3_GBL_IRQ_MSK PXA1928_ICU_GBL_IRQ4_MSK
+#define PXA1928_ICU_CORE0_GBL_FIQ_MSK PXA1928_ICU_GBL_FIQ1_MSK
+#define PXA1928_ICU_CORE1_GBL_FIQ_MSK PXA1928_ICU_GBL_FIQ2_MSK
+#define PXA1928_ICU_CORE2_GBL_FIQ_MSK PXA1928_ICU_GBL_FIQ3_MSK
+#define PXA1928_ICU_CORE3_GBL_FIQ_MSK PXA1928_ICU_GBL_FIQ4_MSK
+
+#define PXA1928_ICU_DMA_IRQ_SP_MASK ICU_REG(0x118)
+#define PXA1928_ICU_DMA_FIQ1_MASK ICU_REG(0x11C)
+#define PXA1928_ICU_DMA_IRQ1_MASK ICU_REG(0x120)
+#define PXA1928_ICU_DMA_FIQ2_MASK ICU_REG(0x194)
+#define PXA1928_ICU_DMA_IRQ2_MASK ICU_REG(0x1dc)
+#define PXA1928_ICU_DMA_FIQ3_MASK ICU_REG(0x1f4)
+#define PXA1928_ICU_DMA_IRQ3_MASK ICU_REG(0x20c)
+#define PXA1928_ICU_DMA_FIQ4_MASK ICU_REG(0x224)
+#define PXA1928_ICU_DMA_IRQ4_MASK ICU_REG(0x23c)
+#define CORE0_CA7_GLB_IRQ_MASK 0x114
+#define CORE1_CA7_GLB_IRQ_MASK 0x1d8
+#define CORE2_CA7_GLB_IRQ_MASK 0x208
+#define CORE3_CA7_GLB_IRQ_MASK 0x238
+
+#define CORE0_CA7_GLB_FIQ_MASK 0x110
+#define CORE1_CA7_GLB_FIQ_MASK 0x190
+#define CORE2_CA7_GLB_FIQ_MASK 0x1f0
+#define CORE3_CA7_GLB_FIQ_MASK 0x220
+
+
+#define PXA1928_ICU_DMA_IRQ_SP_STATUS ICU_REG(0x124)
+#define PXA1928_ICU_DMA_FIQ1_STATUS ICU_REG(0x128)
+#define PXA1928_ICU_DMA_IRQ1_STATUS ICU_REG(0x12C)
+#define PXA1928_ICU_DMA_FIQ2_STATUS ICU_REG(0x198)
+#define PXA1928_ICU_DMA_IRQ2_STATUS ICU_REG(0x1E0)
+#define PXA1928_ICU_DMA_FIQ3_STATUS ICU_REG(0x1f8)
+#define PXA1928_ICU_DMA_IRQ3_STATUS ICU_REG(0x210)
+#define PXA1928_ICU_DMA_FIQ4_STATUS ICU_REG(0x228)
+#define PXA1928_ICU_DMA_IRQ4_STATUS ICU_REG(0x240)
+
+#define PXA1928_ICU_IRQ_SP_STATUS_0 ICU_REG(0x130)
+#define PXA1928_ICU_IRQ_SP_STATUS_1 ICU_REG(0x134)
+#define PXA1928_ICU_FIQ1_STATUS_0 ICU_REG(0x138)
+#define PXA1928_ICU_FIQ1_STATUS_1 ICU_REG(0x13C)
+#define PXA1928_ICU_IRQ1_STATUS_0 ICU_REG(0x140)
+#define PXA1928_ICU_IRQ1_STATUS_1 ICU_REG(0x144)
+#define PXA1928_ICU_FIQ2_STATUS_0 ICU_REG(0x19C)
+#define PXA1928_ICU_FIQ2_STATUS_1 ICU_REG(0x1A0)
+#define PXA1928_ICU_IRQ2_STATUS_0 ICU_REG(0x1E4)
+#define PXA1928_ICU_IRQ2_STATUS_1 ICU_REG(0x1E8)
+
+#define PXA1928_ICU_INT_4_STATUS ICU_REG(0x150)
+#define PXA1928_ICU_INT_5_STATUS ICU_REG(0x154)
+#define PXA1928_ICU_INT_6_STATUS ICU_REG(0x1BC)
+#define PXA1928_ICU_INT_8_STATUS ICU_REG(0x1C0)
+#define PXA1928_ICU_INT_17_STATUS ICU_REG(0x158)
+#define PXA1928_ICU_INT_18_STATUS ICU_REG(0x1C4)
+#define PXA1928_ICU_INT_30_STATUS ICU_REG(0x1C8)
+#define PXA1928_ICU_INT_35_STATUS ICU_REG(0x15C)
+#define PXA1928_ICU_INT_42_STATUS ICU_REG(0x1CC)
+#define PXA1928_ICU_INT_51_STATUS ICU_REG(0x160)
+#define PXA1928_ICU_INT_INVERT ICU_REG(0x164)
+#define PXA1928_ICU_INT_55_STATUS ICU_REG(0x184)
+#define PXA1928_ICU_INT_57_STATUS ICU_REG(0x188)
+#define PXA1928_ICU_INT_58_STATUS ICU_REG(0x1D0)
+
+#define PXA1928_ICU_INT_4_MASK ICU_REG(0x168)
+#define PXA1928_ICU_INT_5_MASK ICU_REG(0x16C)
+#define PXA1928_ICU_INT_6_MASK ICU_REG(0x1A4)
+#define PXA1928_ICU_INT_8_MASK ICU_REG(0x1A8)
+#define PXA1928_ICU_INT_17_MASK ICU_REG(0x170)
+#define PXA1928_ICU_INT_18_MASK ICU_REG(0x1AC)
+#define PXA1928_ICU_INT_30_MASK ICU_REG(0x1B0)
+#define PXA1928_ICU_INT_35_MASK ICU_REG(0x174)
+#define PXA1928_ICU_INT_42_MASK ICU_REG(0x1B4)
+#define PXA1928_ICU_INT_51_MASK ICU_REG(0x178)
+#define PXA1928_ICU_INT_55_MASK ICU_REG(0x17C)
+#define PXA1928_ICU_INT_57_MASK ICU_REG(0x180)
+#define PXA1928_ICU_INT_58_MASK ICU_REG(0x1B8)
+
+#endif /* CONFIG_CPU_PXA1928 */
+
+#endif /* __ASM_MACH_ICU_H */
diff --git a/marvell/linux/include/soc/asr/regs-map.h b/marvell/linux/include/soc/asr/regs-map.h
new file mode 100644
index 0000000..7078671
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-map.h
@@ -0,0 +1,188 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-map.h
+ *
+ * Common soc registers map
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_MACH_REGS_MAP_H
+#define __ASM_MACH_REGS_MAP_H
+#include <plat/dump_regs.h>
+
+struct reg_map pxa_reg_map[] = {
+/* register map of pxa1088 */
+/*
+ * important registers like CIU, Main_PMU, AP_PMU, MCK4, APB_clock, ICU are
+ * put ahead, they will be dumped as early as possible.
+ */
+ {0xD4282C00, 0xD4282CFC, 0, "CIU"},
+ {0xD4050000, 0xD405004C, 0, "Main_PMU_0"},
+ {0xD4050100, 0xD4050100, 0, "Main_PMU_1"},
+ {0xD4050200, 0xD4050200, 0, "Main_PMU_2"},
+ {0xD4050400, 0xD4050410, 0, "Main_PMU_3"},
+ {0xD4051000, 0xD4051004, 0, "Main_PMU_4"},
+ {0xD4051020, 0xD4051028, 0, "Main_PMU_5"},
+ {0xD4051048, 0xD405104C, 0, "Main_PMU_6"},
+ {0xD4052000, 0xD4052058, 0, "Main_PMU_DVC"},
+ {0xD4282800, 0xD4282970, 0, "AP_PMU"},
+ {0xC0100000, 0xC010003C, 0, "MCK4_00"},
+ {0xC0100050, 0xC0100078, 0, "MCK4_01"},
+ {0xC0100080, 0xC010009C, 0, "MCK4_02"},
+ {0xC0100100, 0xC0100100, 0, "MCK4_03"},
+ {0xC0100110, 0xC0100110, 0, "MCK4_04"},
+ {0xC0100120, 0xC010012C, 0, "MCK4_05"},
+ {0xC010013C, 0xC0100158, 0, "MCK4_06"},
+ {0xC0100160, 0xC0100164, 0, "MCK4_07"},
+ {0xC0100170, 0xC0100170, 0, "MCK4_08"},
+ {0xC0100180, 0xC0100184, 0, "MCK4_09"},
+ {0xC01001C0, 0xC01001C0, 0, "MCK4_10"},
+ {0xC01001C8, 0xC01001CC, 0, "MCK4_11"},
+ {0xC0100220, 0xC0100220, 0, "MCK4_12"},
+ {0xC0100230, 0xC0100258, 0, "MCK4_13"},
+ {0xC0100280, 0xC0100288, 0, "MCK4_14"},
+ {0xC0100300, 0xC0100308, 0, "MCK4_15"},
+ {0xC0100380, 0xC0100390, 0, "MCK4_16"},
+ {0xC0100400, 0xC0100400, 0, "MCK4_17"},
+ {0xC0100410, 0xC0100414, 0, "MCK4_18"},
+ {0xC0100440, 0xC0100448, 0, "MCK4_19"},
+ {0xC0100450, 0xC010045c, 0, "MCK4_20"},
+ {0xD4015000, 0xD4015068, 0, "APB_clock"},
+ {0xD4282000, 0xD428217C, 0, "ICU_0"},
+ {0xD4282200, 0xD4282258, 0, "ICU_1"},
+ {0xD4282300, 0xD428235C, 0, "ICU_2"},
+
+/*
+ * below registers are arranged according their physical address.
+ * please -don't- delete the commented lines, they are kept as index
+ * some regs are already dumped above;
+ * some regs do not exist in spec;
+ * some modules are not enabled, if read the regs, system will hang;
+ * some regs are not necessary to dump at present, but may need in furture.
+ */
+
+/* {0xC0000000, 0xC000FFFC, 0, "SPH USB PHY"}, not necessary */
+/* {0xC0010000, 0xC001FFFC, 0, "SPH USB CTL"}, not necessary */
+/* {0xC0100000, 0xC010045C, 0, "MCK4"}, already dumped above */
+/* {0xC0400000, 0xC04FFFFC, 0, "GC 1000T"}, not necessary */
+
+/* 0xD1DF9000 ~ 0xD1DFDFFF are GIC registers */
+ {0xD1DF9000, 0xD1DF9008, 0, "GIC_Distributor_00"},
+ {0xD1DF9080, 0xD1DF90BC, 0, "GIC_Distributor_01"},
+ {0xD1DF9100, 0xD1DF913C, 0, "GIC_Distributor_02"},
+ {0xD1DF9180, 0xD1DF91BC, 0, "GIC_Distributor_03"},
+ {0xD1DF9200, 0xD1DF923C, 0, "GIC_Distributor_04"},
+ {0xD1DF9280, 0xD1DF92BC, 0, "GIC_Distributor_05"},
+ {0xD1DF9300, 0xD1DF933C, 0, "GIC_Distributor_06"},
+ {0xD1DF9380, 0xD1DF93BC, 0, "GIC_Distributor_07"},
+ {0xD1DF9400, 0xD1DF95FC, 0, "GIC_Distributor_08"},
+ {0xD1DF9800, 0xD1DF99FC, 0, "GIC_Distributor_09"},
+ {0xD1DF9C00, 0xD1DF9C7C, 0, "GIC_Distributor_10"},
+ {0xD1DF9D00, 0xD1DF9D3C, 0, "GIC_Distributor_11"},
+ {0xD1DF9F00, 0xD1DF9F2C, 0, "GIC_Distributor_12"},
+ {0xD1DF9FD0, 0xD1DF9FFC, 0, "GIC_Distributor_13"},
+ {0xD1DFA000, 0xD1DFA028, 0, "GIC_CPU_interface_0"},
+ {0xD1DFA0D0, 0xD1DFA0FC, 0, "GIC_CPU_interface_1"},
+ {0xD1DFB000, 0xD1DFB030, 0, "GIC_common_base_add_0"},
+ {0xD1DFB0F0, 0xD1DFB10C, 0, "GIC_common_base_add_1"},
+ {0xD1DFC000, 0xD1DFC030, 0, "GIC_processor_spc_add_0"},
+ {0xD1DFC0F0, 0xD1DFC10C, 0, "GIC_processor_spc_add_1"},
+ {0xD1DFD000, 0xD1DFD028, 0, "GIC_Vir_CPU_interface_0"},
+ {0xD1DFD0D0, 0xD1DFD0FC, 0, "GIC_Vir_CPU_interface_1"},
+
+/* 0xD4000000 ~ 0xD41FFFFF are APB Peripheral registers */
+ {0xD4000000, 0xD40003FC, 0, "DMA"},
+ {0xD4010000, 0xD4010024, 0, "RTC"},
+ {0xD4010800, 0xD4010858, 0, "IIC1"},
+ {0xD4011000, 0xD4011058, 0, "IIC0"},
+ {0xD4011800, 0xD4011810, 0, "OneWire"},
+ {0xD4012000, 0xD4012048, 0, "Keypad"},
+/* {0xD4013000, 0xD40130FC, 0, "Trackball"}, not exist in spec */
+ {0xD4013100, 0xD4013108, 0, "JTAG"},
+ {0xD4013200, 0xD4013230, 0, "DRO"},
+ {0xD4014000, 0xD40140AC, 0, "Timer0"},
+/* {0xD4015000, 0xD4015068, 0, "APB_clock"}, already dumped above */
+ {0xD4016000, 0xD40160AC, 0, "Timer1"},
+ {0xD4017000, 0xD401702C, 0, "UART1"},
+ {0xD4018000, 0xD401802C, 0, "UART2"},
+ {0xD4019000, 0xD40191A8, 0, "GPIO"},
+ {0xD4019800, 0xD401980C, 0, "GPIO_Edge"},
+ {0xD401A000, 0xD401A008, 0, "PWM0"},
+ {0xD401A400, 0xD401A408, 0, "PWM1"},
+ {0xD401A800, 0xD401A808, 0, "PWM2"},
+ {0xD401AC00, 0xD401AC08, 0, "PWM3"},
+ {0xD401B000, 0xD401B08C, 0, "SSP1"},
+ {0xD401C000, 0xD401C08C, 0, "SSP3"},
+ {0xD401D000, 0xD401D014, 0, "AP_IPC"},
+ {0xD401D800, 0xD401D814, 0, "CP_IPC"},
+ {0xD401E000, 0xD401E32C, 0, "MFPR"},
+ {0xD401E800, 0xD401E830, 0, "IO_Power_0"},
+/* {0xD401EC00, 0xD401EC14, 0, "IO_Power_1"}, overlap with SFO */
+ {0xD401EC00, 0xD401EC14, 0, "SFO"},
+ {0xD401F000, 0xD401F0B0, 0, "Timer2"},
+/* {0xD4030000, 0xD403004C, 0, "TCU_0"}, not necessary */
+/* {0xD4030400, 0xD40307FC, 0, "TCU_1"}, not necessary */
+/* {0xD4031000, 0xD40318F4, 0, "XIRQ"}, not necessary */
+/* {0xD4032000, 0xD4032044, 0, "USIM1"}, not necessary */
+/* {0xD4033000, 0xD4033044, 0, "USIM2"}, not necessary */
+/* {0xD4034000, 0xD4034050, 0, "E_cip_core"}, not necessary */
+/* {0xD4034100, 0xD4034100, 0, "E_cip_data"}, not necessary */
+/* {0xD4035000, 0xD4035FFC, 0, "E_cip_ctrl"}, not necessary */
+/* {0xD4036000, 0xD403602C, 0, "GB_UART0"}, not necessary */
+/* {0xD4037000, 0xD4037058, 0, "GB_IIC"}, not necessary */
+/* {0xD4038000, 0xD403802C, 0, "GB_SCLK"}, not necessary */
+/* {0xD403B00C, 0xD403B00C, 0, "GSSP"}, inside GB Mreg */
+/* {0xD403A000, 0xD403A0AC, 0, "TimerCP"}, not necessary */
+/* {0xD403B000, 0xD403B03C, 0, "APB_CP_clock_ctrl"}, not necessary */
+/* {0xD403C000, 0xD403C014, 0, "GB_IPC"}, not necessary */
+/* {0xD403D000, 0xD403D01C, 0, "GB_R_IPC_0"}, not necessary */
+/* {0xD403D100, 0xD403D11C, 0, "GB_R_IPC_1"}, not necessary */
+/* {0xD403D200, 0xD403D21C, 0, "GB_R_IPC_2"}, not necessary */
+/* {0xD403D300, 0xD403D31C, 0, "GB_R_IPC_3"}, not necessary */
+/* {0xD4050000, 0xD405104C, 0, "Main PMU"}, already dumped above */
+/* {0xD4052000, 0xD4052058, 0, "Main_PMU_DVC"}, already dumped above */
+/* {0xD4060000, 0xD406FFFC, 0, "PMU_SCK"}, not exist in spec */
+ {0xD4070000, 0xD4070020, 0, "APB_Aux"},
+ {0xD4080000, 0xD40800AC, 0, "PMU_Timer"},
+ {0xD4090000, 0xD409000C, 0, "APB_spare_0"},
+ {0xD4090100, 0xD409010C, 0, "APB_spare_1"},
+/* {0xD4100000, 0xD41FFFFC, 0, "CoreSight"}, not necessary */
+ {0xD4101000, 0xD4101020, 0, "GenericCounter"},
+
+/* 0xD4200000 ~ 0xD4284FFF are AXI Peripheral registers */
+ {0xD4200200, 0xD4200260, 0, "AXI_Fab_0"},
+ {0xD4200408, 0xD42004CC, 0, "AXI_Fab_1"},
+/* {0xD4201000, 0xD42014C8, 0, "GEU"}, not necessary */
+ {0xD4207000, 0xD4207064, 0, "USB_utmi_phy"},
+ {0xD4207100, 0xD4207134, 0, "USB_utmi_old"},
+ {0xD4208000, 0xD42081FC, 0, "USB_device"},
+ {0xD420A000, 0xD420A23C, 0, "CCIC"},
+ {0xD420B000, 0xD420B1F4, 0, "LCD"},
+ {0xD420B800, 0xD420B9EC, 0, "DSI"},
+/* {0xD420D000, 0xD420DFFC, 0, "7542_Video_Decoder"}, not necessary */
+/* {0xD420E000, 0xD420EFFC, 0, "DTE(DDR Test)"}, not exist in spec */
+/* {0xD420F000, 0xD420FE38, 0, "ISPDMA"}, not necessary */
+/* {0xD4240000, 0xD427FFFC, 0, "DXO DMA config"}, not exist in spec */
+ {0xD4280000, 0xD428006C, 0, "SDH1_0"},
+ {0xD42800E0, 0xD42800E0, 0, "SDH1_1"},
+ {0xD42800FC, 0xD428011C, 0, "SDH1_2"},
+ {0xD4280800, 0xD428086C, 0, "SDH2_0"},
+ {0xD42808E0, 0xD42808E0, 0, "SDH2_1"},
+ {0xD42808FC, 0xD428091C, 0, "SDH2_2"},
+ {0xD4281000, 0xD428106C, 0, "SDH3_0"},
+ {0xD42810E0, 0xD42810E0, 0, "SDH3_1"},
+ {0xD42810FC, 0xD428111C, 0, "SDH3_2"},
+/* {0xD4282000, 0xD42823FC, 0, "ICU"}, already dumped above */
+/* {0xD4282800, 0xD4282970, 0, "AP PMU"}, already dumped above */
+/* {0xD4282C00, 0xD42820FC, 0, "CIU"}, already dumped above */
+/* {0xD4283000, 0xD428307C, 0, "NAND"}, if read, will hang */
+ {0xD4283800, 0xD4283840, 0, "SMC"},
+/* {0xD4284000, 0xD42840C0, 0, "DTC"}, if read, will hang */
+/* {0xD4290000, 0xD4290B78, 0, "HSI"}, if read, will hang */
+ {0xD42A0C00, 0xD42A0C8C, 0, "SSP3"},
+ {0 , 0 , 0, NULL }
+};
+
+#endif /* __ASM_MACH_REG_MAP_H
+# */
diff --git a/marvell/linux/include/soc/asr/regs-mccu.h b/marvell/linux/include/soc/asr/regs-mccu.h
new file mode 100644
index 0000000..5fea649
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-mccu.h
@@ -0,0 +1,39 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/regs-mccu.h
+ *
+ * Main Clock Control Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_MCCU_H
+#define __ASM_MACH_REGS_MCCU_H
+
+#if defined(CONFIG_CPU_PXA1986)
+/*
+ * MCCU register offsets for PXA1986
+ */
+#define MCCU_APBCR (0x000)
+#define MCCU_AXICR (0x004)
+#define MCCU_DDRCR (0x008)
+#define MCCU_TIMSTCR (0x00C)
+#define MCCU_PDBGCR (0x010)
+#define MCCU_AP_CKREQ (0x014)
+#define MCCU_CP_CKREQ (0x018)
+#define MCCU_AUD_CKREQ (0x01C)
+#define MCCU_CKDBG (0x020)
+#define MCCU_TSCR (0x024)
+#define MCCU_I2CCR (0x028)
+#define MCCU_GPNMCR (0x02C)
+#define MCCU_GPNMEN (0x030)
+#define MCCU_TROCR (0x034)
+#define MCCU_CKENCR (0x038)
+#define MCCU_CKCTR (0x03C)
+#define MCCU_AP_CKSTAT (0x050)
+#define MCCU_CP_CKSTAT (0x054)
+#define MCCU_AUD_CKSTAT (0x058)
+#endif
+
+#endif /* __ASM_MACH_REGS_MCCU_H */
diff --git a/marvell/linux/include/soc/asr/regs-mcu.h b/marvell/linux/include/soc/asr/regs-mcu.h
new file mode 100644
index 0000000..5d1b03b
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-mcu.h
@@ -0,0 +1,204 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-mcu.h
+ *
+ * Memory Control Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_MCU_H
+#define __ASM_MACH_MCU_H
+
+#include <soc/asr/addr-map.h>
+
+#if defined(CONFIG_CPU_MMP3)
+#define FIXADDR(base, offset) ((u32 *)(((u32)base)+offset))
+#define DMCU_HWTCTRL(base) FIXADDR(base, 0x1c0)
+#define DMCU_HWTDAT0(base) FIXADDR(base, 0x1c8)
+#define DMCU_HWTDAT1(base) FIXADDR(base, 0x1cc)
+#elif defined(CONFIG_CPU_PXA1928)
+#define FIXADDR(base, offset) ((u32 *)(((u32)base)+offset))
+#define DMCU_HWTCTRL(base) FIXADDR(base, 0xc0)
+#define DMCU_HWTDAT0(base) FIXADDR(base, 0xc4)
+#define DMCU_HWTDAT1(base) FIXADDR(base, 0xc8)
+#define DMCU_REG(x) FIXADDR(DMCU_VIRT_BASE, (x))
+#else
+#define DMCU_VIRT_REG(x) (DMCU_VIRT_BASE + (x))
+#define DMCU_PHYS_REG(x) (DMCU_PHYS_BASE + (x))
+#define DMCU_HWTCTRL (0x1c0)
+#define DMCU_HWTDAT0 (0x1c8)
+#define DMCU_HWTDAT1 (0x1cc)
+#endif
+#define DMCU_HWTPAUSE (0x00010000)
+#define DMCU_HWTEND (0x00020000)
+#define DMCU_HWTWRITE (0x80000000)
+
+#define DMCU_CPU_ID_REV (0x00)
+#define DMCU_STATUS (0x04)
+#define DMCU_DRAM_STATUS (0x08)
+
+#define DMCU_DRAM_STATUS_PD (4)
+#define DMCU_DRAM_STATUS_DPD (2)
+#define DMCU_DRAM_STATUS_SR (1)
+
+#ifdef CONFIG_CPU_PXA1928
+#define DMCU_MAP_CS0 (0x200)
+#define DMCU_MAP_CS1 (0x204)
+#else
+#define DMCU_MAP_CS0 (0x10)
+#define DMCU_MAP_CS1 (0x14)
+#endif
+
+#define DMCU_MAP_VALID (1u << 0)
+#define DMCU_CMD_CSSEL_CS0 (1u << 24)
+#define DMCU_CMD_CSSEL_CS1 (1u << 25)
+
+#if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088)
+#define DMCU_MAP_CS2 (0x18)
+#define DMCU_MAP_CS3 (0x1c)
+#endif
+
+#define DMCU_SDRAM_CFG0_TYPE1 (0x20)
+#define DMCU_SDRAM_CFG1_TYPE1 (0x24)
+#if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088)
+#define DMCU_SDRAM_CFG2_TYPE1 (0x28)
+#define DMCU_SDRAM_CFG3_TYPE1 (0x2c)
+#endif
+
+#define DMCU_SDRAM_CFG0_TYPE2 (0x30)
+#define DMCU_SDRAM_CFG1_TYPE2 (0x34)
+#if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088)
+#define DMCU_SDRAM_CFG2_TYPE2 (0x38)
+#define DMCU_SDRAM_CFG3_TYPE2 (0x3c)
+#endif
+
+#define DMCU_SDRAM_CTRL1 (0x50)
+#define DMCU_SDRAM_CTRL2 (0x54)
+#define DMCU_SDRAM_CTRL4 (0x58)
+#define DMCU_SDRAM_TYPE_MASK (7u << 2)
+#define DMCU_SDRAM_TYPE_DDR3 (2u << 2)
+#define DMCU_SDRAM_TYPE_LPDDR2 (5u << 2)
+#define DMCU_SDRAM_CTRL4_CL_SHIFT (13)
+#define DMCU_SDRAM_CTRL4_CL_MASK (0xf << DMCU_SDRAM_CTRL4_CL_SHIFT)
+#define DMCU_SDRAM_CTRL4_BL_SHIFT (22)
+#define DMCU_SDRAM_CTRL4_BL_MASK (0x3 << DMCU_SDRAM_CTRL4_BL_SHIFT)
+#define DMCU_SDRAM_CTRL6 (0x5c)
+#define DMCU_SDRAM_CTRL7 (0x60)
+#define DMCU_SDRAM_CTRL13 (0x64)
+#define DMCU_SDRAM_CTRL14 (0x68)
+
+#ifdef CONFIG_CPU_PXA1928
+#define DMCU_SDRAM_TIMING1 (0x300)
+#define DMCU_SDRAM_TIMING2 (0x380)
+#define DMCU_SDRAM_TIMING3 (0x384)
+#define DMCU_SDRAM_TIMING4 (0x388)
+#define DMCU_SDRAM_TIMING5 (0x38c)
+#define DMCU_SDRAM_TIMING6 (0x390)
+#define DMCU_SDRAM_TIMING7 (0x394)
+#define DMCU_SDRAM_TIMING8 (0x398)
+#define DMCU_SDRAM_TIMING9 (0x39c)
+#define DMCU_SDRAM_TIMING10 (0x3a0)
+#define DMCU_SDRAM_TIMING11 (0x3a4)
+#define DMCU_SDRAM_TIMING12 (0x3a8)
+#define DMCU_SDRAM_TIMING13 (0x500)
+#define DMCU_SDRAM_TIMING14 (0x504)
+#define DMCU_SDRAM_TIMING15 (0x508)
+#define DMCU_SDRAM_TIMING16 (0x50c)
+#else
+#define DMCU_SDRAM_TIMING1 (0x80)
+#define DMCU_SDRAM_TIMING2 (0x84)
+#define DMCU_SDRAM_TIMING3 (0x88)
+#define DMCU_SDRAM_TIMING4 (0x8c)
+#define DMCU_SDRAM_TIMING5 (0x90)
+#define DMCU_SDRAM_TIMING6 (0x94)
+#define DMCU_SDRAM_TIMING7 (0x98)
+#define DMCU_SDRAM_TIMING8 (0x9c)
+#endif
+
+#define DMCU_EXCLUSIVE_MONITOR_CTRL (0x100)
+#define DMCU_DATA_COH_CTRL (0x110)
+#define DMCU_TRUSTZONE_SEL (0x120)
+#define DMCU_TRUSTZONE_RANGE0 (0x124)
+#define DMCU_TRUSTZONE_RANGE1 (0x128)
+#define DMCU_TRUSTZONE_PERMISSION (0x12C)
+#define DMCU_PORT_PRIORITY (0x140)
+#define DMCU_BQ_STARV_PREVENTION (0x144)
+#define DMCU_RRB_STARV_PREVENTION0 (0x148)
+#define DMCU_RRB_STARV_PREVENTION1 (0x14C)
+#define DMCU_SRAM_CTRL1 (0x150)
+#define DMCU_SRAM_CTRL2 (0x154)
+#define DMCU_SRAM_CTRL3 (0x158)
+
+#ifdef CONFIG_CPU_PXA1928
+#define DMCU_USER_COMMAND0 (0x20)
+#define DMCU_USER_COMMAND1 (0x24)
+#else
+#define DMCU_USER_COMMAND0 (0x160)
+#define DMCU_USER_COMMAND1 (0x164)
+#endif
+
+#define DMCU_MODE_RD_DATA (0x170)
+
+#if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088)
+#define DMCU_SMR1 (0x180)
+#define DMCU_SMR2 (0x184)
+#endif
+
+#if defined(CONFIG_CPU_PXA1928)
+#define DMCU_CTRL_0 (0x044)
+#define DMCU_CH0_PMAP0 (0x210)
+#define DMCU_PHY_CTRL3 (0x408)
+#define DMCU_PHY_CTRL8 (0x41c)
+#define DMCU_PHY_CTRL9 (0x420)
+#define DMCU_PHY_CTRL10 (0x424)
+#define DMCU_PHY_CTRL11 (0x428)
+#else
+#define DMCU_PHY_CTRL3 (0x220)
+#define DMCU_PHY_CTRL7 (0x230)
+#define DMCU_PHY_CTRL8 (0x234)
+#define DMCU_PHY_CTRL9 (0x238)
+#define DMCU_PHY_CTRL10 (0x23c)
+#define DMCU_PHY_CTRL11 (0x240)
+#endif
+
+#if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088)
+#define DMCU_PHY_CTRL12 (0x244)
+#endif
+
+#define DMCU_PHY_CTRL13 (0x248)
+#define DMCU_PHY_CTRL14 (0x24c)
+#define DMCU_PHY_CTRL15 (0x250)
+#define DMCU_PHY_CTRL16 (0x254)
+#define DMCU_PHY_CTRL21 (0x258)
+#define DMCU_PHY_CTRL19 (0x280)
+#define DMCU_PHY_CTRL20 (0x284)
+#define DMCU_PHY_CTRL22 (0x288)
+#define DMCU_PHY_DQ_BYTE_SEL (0x300)
+#define DMCU_PHY_DLL_CTRL_BYTE1 (0x304)
+#define DMCU_PHY_DLL_WL_SEL (0x380)
+#define DMCU_PHY_DLL_WL_CTRL0 (0x384)
+#define DMCU_PHY_DLL_WL_CTRL1 (0x388)
+#define DMCU_PHY_DLL_WL_CTRL2 (0x38C)
+#define DMCU_PHY_DLL_RL_CTRL (0x390)
+
+#define PHY_CTRL14_DLL_RESET (1u << 29)
+#define PHY_CTRL14_DLL_UPDATE (1u << 30)
+#define PHY_CTRL14_PHY_SYNC (1u << 31)
+
+#if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088)
+#define DMCU_PHY_CTRL_TESTMODE (0x400)
+#endif
+
+#define DMCU_TEST_MODE0 (0x410)
+#define DMCU_TEST_MODE1 (0x414)
+#define DMCU_PERF_CNT_CTRL0 (0x440)
+#define DMCU_PERF_CNT_STATUS (0x444)
+#define DMCU_PERF_CNT_SEL (0x448)
+#define DMCU_PERF_CNT0 (0x450)
+#define DMCU_PERF_CNT1 (0x454)
+#define DMCU_PERF_CNT2 (0x458)
+#define DMCU_PERF_CNT3 (0x45c)
+
+#endif /* __ASM_MACH_MCU_H */
diff --git a/marvell/linux/include/soc/asr/regs-mpmu.h b/marvell/linux/include/soc/asr/regs-mpmu.h
new file mode 100644
index 0000000..ec7c2a2
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-mpmu.h
@@ -0,0 +1,142 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-mpmu.h
+ *
+ * Main Power Management Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_MPMU_H
+#define __ASM_MACH_REGS_MPMU_H
+
+#ifdef CONFIG_CPU_PXA1986
+/*
+ * MPMU_PCR_0 : used by the Cortex-A7 CPU0 Apps Subsystem
+ * MPMU_PCR_1 : used by the Secure Processor subsystem
+ * MPMU_PCR_2 : used by the Comm Cortex R-5 subsystem core (aka CP1)
+ * MPMU_PCR_3 : used by the Comm MSA subsystem (aka CP2)
+ * MPMU_PCR_4 : used by the Audio subsystem
+ */
+#define MPMU_PCR_0 (0x0000)
+#define MPMU_PCR_1 (0x0004)
+#define MPMU_PCR_2 (0x0008)
+#define MPMU_PCR_3 (0x000C)
+#define MPMU_PCR_4 (0x0010)
+#define MPMU_VCXOCR (0x0014)
+#define MPMU_DFCCR (0x0018)
+#define MPMU_PLL1DLY (0x001C)
+#define MPMU_PLL2DLY (0x0020)
+#define MPMU_PLLDDLY (0x0024)
+#define MPMU_PLLADLY (0x0028)
+#define MPMU_ANAGCR (0x002C)
+#define MPMU_MCKCR (0x0030)
+#define MPMU_EXVCXOCR (0x0034)
+#define MPMU_RSTOCR (0x0038)
+#define MPMU_AP_PLLREQ (0x003C)
+#define MPMU_CP_PLLREQ (0x0040)
+#define MPMU_AUD_PLLREQ (0x0044)
+#define MPMU_SRD_PLLREQ (0x0048)
+#define MPMU_RSTSR (0x004C)
+#define MPMU_PWRDLY (0x0050)
+#define MPMU_CKEN32K (0x0054)
+#define MPMU_RST32K (0x0058)
+#define MPMU_CPCTL (0x005C)
+#define MPMU_AUDSSCR (0x0060)
+#define MPMU_RSRV1 (0x0064)
+#define MPMU_PLLSTAT (0x0068)
+#define MPMU_SLPIND_CR (0x006C)
+#define MPMU_PLL1_CF1 (0x0070)
+#define MPMU_PLL1_CF2 (0x0074)
+#define MPMU_PLL2_CF1 (0x0078)
+#define MPMU_PLL2_CF2 (0x007C)
+#define MPMU_PLL2_CF3 (0x0080)
+#define MPMU_PLLD_CF1 (0x0084)
+#define MPMU_PLLD_CF2 (0x0088)
+#define MPMU_PLLD_CF3 (0x008C)
+#define MPMU_PLLD_CF4 (0x0090)
+#define MPMU_PLLA_CF1 (0x0094)
+#define MPMU_PLLA_CF2 (0x0098)
+#define MPMU_PCSTAT (0x00A0)
+#define MPMU_PLL1FCGO (0x00A4)
+#define MPMU_PLL2FCGO (0x00A8)
+#define MPMU_PLLDFCGO (0x00AC)
+#define MPMU_PLLAFCGO (0x00B0)
+#define MPMU_LPMUDLY0 (0x00B4)
+#define MPMU_LPMUDLY1 (0x00B8)
+#define MPMU_LPMUDLY2 (0x00BC)
+#define MPMU_TROPCR (0x00C0)
+#define MPMU_AUD_PMUDLY (0x00C4)
+#define MPMU_TRO_PMUDLY (0x00C8)
+#define MPMU_CK32KCR (0x00CC)
+#define MPMU_MIPSHL_CR (0x00D0)
+#define MPMU_RSRV2 (0x00D4)
+#define MPMU_IOPADCR (0x00D8)
+#define MPMU_PLL1SEL (0x00DC)
+#define MPMU_WKUP_STAT (0x00E0)
+#define MPMU_GENSW1 (0x00E4)
+#define MPMU_GENSW2 (0x00E8)
+#define MPMU_GENSW3 (0x00EC)
+#define MPMU_GENSW4 (0x00F0)
+#define MPMU_AUDVDLY (0x00F4)
+#define MPMU_AVS_SNSCR (0x00F8)
+/*
+ * MPMU_PCR_AP_1 : used by the Cortex-A7 CPU1 Apps Subsystem
+ * MPMU_PCR_AP_2 : used by the Cortex-A15 CPU0 Apps Subsystem
+ * MPMU_PCR_AP_3 : used by the Cortex-A15 CPU1 Apps Subsystem
+ */
+#define MPMU_PCR_AP_1 (0x0100)
+#define MPMU_PCR_AP_2 (0x0104)
+#define MPMU_PCR_AP_3 (0x0108)
+#define MAVS_LVDDL (0x0120)
+#define MAVS_HVDDL (0x0124)
+#define MAVS_DELTA (0x0128)
+#define MAVS_SPDT_0 (0x012C)
+#define MAVS_SPDT_1 (0x0130)
+#define MAVS_EN_GEN (0x0134)
+#define MAVS_VC (0x0138)
+#define MAVS_GP1 (0x013C)
+#define MAVS_GP2 (0x0140)
+#define MAVS_DRO_CFG (0x0144)
+#define MAVS_TP (0x0148)
+#define MAVS_DRO_CNT_STATUS1 (0x014C)
+#define MAVS_DRO_CNT_STATUS2 (0x0150)
+#define MAVS_STATUS1 (0x0154)
+#define MAVS_STATUS2 (0x0158)
+#define CAVS_LVDDL (0x0160)
+#define CAVS_HVDDL (0x0164)
+#define CAVS_DELTA (0x0168)
+#define CAVS_SPDT_0 (0x016C)
+#define CAVS_SPDT_1 (0x0170)
+#define CAVS_EN_GEN (0x0174)
+#define CAVS_VC (0x0178)
+#define CAVS_GP1 (0x017C)
+#define CAVS_GP2 (0x0180)
+#define CAVS_DRO_CFG (0x0184)
+#define CAVS_TP (0x0188)
+#define CAVS_DRO_CNT_STATUS1 (0x018C)
+#define CAVS_DRO_CNT_STATUS2 (0x0190)
+#define CAVS_STATUS1 (0x0194)
+#define CAVS_STATUS2 (0x0198)
+#define GAVS_LVDDL (0x01A0)
+#define GAVS_HVDDL (0x01A4)
+#define GAVS_DELTA (0x01A8)
+#define GAVS_SPDT_0 (0x01AC)
+#define GAVS_SPDT_1 (0x01B0)
+#define GAVS_EN_GEN (0x01B4)
+#define GAVS_VC (0x01B8)
+#define GAVS_GP1 (0x01BC)
+#define GAVS_GP2 (0x01C0)
+#define GAVS_DRO_CFG (0x01C4)
+#define GAVS_TP (0x01C8)
+#define GAVS_DRO_CNT_STATUS1 (0x01CC)
+#define GAVS_DRO_CNT_STATUS2 (0x01D0)
+#define GAVS_STATUS1 (0x01D4)
+#define GAVS_STATUS2 (0x01D8)
+#define MDRO_CLCTR_CTL (0x01E0)
+#define CDRO_CLCTR_CTL (0x01E4)
+#define GDRO_CLCTR_CTL (0x01E8)
+#endif /* CONFIG_CPU_PXA1986 */
+
+#endif /* __ASM_MACH_REGS_MPMU_H */
diff --git a/marvell/linux/include/soc/asr/regs-rtc.h b/marvell/linux/include/soc/asr/regs-rtc.h
new file mode 100644
index 0000000..eef75bd
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-rtc.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_MACH_REGS_RTC_H
+#define __ASM_MACH_REGS_RTC_H
+
+#include <soc/asr/addr-map.h>
+
+#define RTC_VIRT_BASE (APB_VIRT_BASE + 0x10000)
+#define RTC_REG(x) (*((volatile u32 __iomem *)(RTC_VIRT_BASE + (x))))
+
+/*
+ * Real Time Clock
+ */
+
+#define RCNR RTC_REG(0x00) /* RTC Count Register */
+#define RTAR RTC_REG(0x04) /* RTC Alarm Register */
+#define RTSR RTC_REG(0x08) /* RTC Status Register */
+#define RTTR RTC_REG(0x0C) /* RTC Timer Trim Register */
+
+#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
+#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
+#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
+#define RTSR_AL (1 << 0) /* RTC alarm detected */
+
+#endif /* __ASM_MACH_REGS_RTC_H */
diff --git a/marvell/linux/include/soc/asr/regs-smc.h b/marvell/linux/include/soc/asr/regs-smc.h
new file mode 100644
index 0000000..0b5c4a2
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-smc.h
@@ -0,0 +1,37 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-smc.h
+ *
+ * Static Memory Controller Registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_SMC_H
+#define __ASM_MACH_REGS_SMC_H
+
+#include <soc/asr/addr-map.h>
+
+#define SMC_VIRT_BASE (AXI_VIRT_BASE + 0x83800)
+#define SMC_REG(x) (SMC_VIRT_BASE + (x))
+
+#define SMC_MSC0 SMC_REG(0x0020)
+#define SMC_MSC1 SMC_REG(0x0024)
+#define SMC_SXCNFG0 SMC_REG(0x0030)
+#define SMC_SXCNFG1 SMC_REG(0x0034)
+#define SMC_MEMCLKCFG SMC_REG(0x0068)
+#define SMC_CSDFICFG0 SMC_REG(0x0090)
+#define SMC_CSDFICFG1 SMC_REG(0x0094)
+#define SMC_CLK_RET_DEL SMC_REG(0x00b0)
+#define SMC_ADV_RET_DEL SMC_REG(0x00b4)
+#define SMC_CSADRMAP0 SMC_REG(0x00c0)
+#define SMC_CSADRMAP1 SMC_REG(0x00c4)
+#define SMC_WE_AP0 SMC_REG(0x00e0)
+#define SMC_WE_AP1 SMC_REG(0x00e4)
+#define SMC_OE_AP0 SMC_REG(0x00f0)
+#define SMC_OE_AP1 SMC_REG(0x00f4)
+#define SMC_ADV_AP0 SMC_REG(0x0100)
+#define SMC_ADV_AP1 SMC_REG(0x0104)
+
+#endif /* __ASM_MACH_REGS_SMC_H */
diff --git a/marvell/linux/include/soc/asr/regs-timers.h b/marvell/linux/include/soc/asr/regs-timers.h
new file mode 100644
index 0000000..48833c1
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-timers.h
@@ -0,0 +1,93 @@
+/*
+ * linux/arch/arm/mach-mmp/include/soc/asr/regs-timers.h
+ *
+ * Timers Module
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_TIMERS_H
+#define __ASM_MACH_REGS_TIMERS_H
+
+#include <soc/asr/addr-map.h>
+
+#ifdef CONFIG_CPU_PXA1986
+#define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x81000)
+#define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x82000)
+#else
+#define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000)
+#define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000)
+#endif
+#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
+
+#if defined(CONFIG_CPU_ASR18XX) || defined(CONFIG_CPU_ASR1901)
+#define TMR_CER (0x0000)
+#define TMR_CMR (0x0004)
+#define TMR_CRSR (0x0008)
+#define TMR_CCR (0x000C)
+#define TMR_TN_MM(n, m) (0x0010 + ((n) << 4) + ((m) << 2))
+#define TMR_PLVR(n) (0x0040 + ((n) << 2))
+#define TMR_PLCR(n) (0x0050 + ((n) << 2))
+#define TMR_IER(n) (0x0060 + ((n) << 2))
+#define TMR_ICR(n) (0x0070 + ((n) << 2))
+#define TMR_SR(n) (0x0080 + ((n) << 2))
+#define TMR_CR(n) (0x0090 + ((n) << 2))
+#define TMR_WFAR (0x00B0)
+#define TMR_WSAR (0x00B4)
+#define TMR_WMER (0x00B8)
+#define TMR_WMR (0x00BC)
+#define TMR_WSR (0x00C0)
+#define TMR_WICR (0x00C4)
+#define TMR_WCR (0x00C8)
+#define TMR_WVR (0x00CC)
+#define TMR_CVWR(n) (0x00D0 + ((n) << 2)) /*ASR18XX has no such register*/
+#else
+#define TMR_CCR (0x0000)
+#define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
+#define TMR_CR(n) (0x0028 + ((n) << 2))
+#define TMR_SR(n) (0x0034 + ((n) << 2))
+#define TMR_IER(n) (0x0040 + ((n) << 2))
+#define TMR_PLVR(n) (0x004c + ((n) << 2))
+#define TMR_PLCR(n) (0x0058 + ((n) << 2))
+#define TMR_WMER (0x0064)
+#define TMR_WMR (0x0068)
+#define TMR_WVR (0x006c)
+#define TMR_WSR (0x0070)
+#define TMR_ICR(n) (0x0074 + ((n) << 2))
+#define TMR_WICR (0x0080)
+#define TMR_CER (0x0084)
+#define TMR_CMR (0x0088)
+#define TMR_ILR(n) (0x008c + ((n) << 2))
+#define TMR_WCR (0x0098)
+#define TMR_WFAR (0x009c)
+#define TMR_WSAR (0x00A0)
+#define TMR_CVWR(n) (0x00A4 + ((n) << 2))
+#define TMR_CRSR (0x00B0) /* for PXA1928 and PXA1088 */
+#endif
+
+#define TMR_CCR_CS_0(x) (((x) & 0x3) << 0)
+#define TMR_CCR_CS_1(x) (((x) & 0x3) << 2)
+#define TMR_CCR_CS_2(x) (((x) & 0x3) << 5)
+
+#ifdef CONFIG_CPU_PXA1928
+/* TIMERS2_VIRT_BASE */
+#define PXA1928_TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x80000)
+#define GEN_TMR_CFG (0x00B0)
+#define GEN_TMR_RR (0x00B4)
+#define GEN_TMR_LD1 (0x00B8)
+#define GEN_TMR_LD2 (0x00BC)
+#define GEN_TMR_CNT1 (0x00C0)
+#define GEN_TMR_CNT2 (0x00C4)
+#undef TIMERS_VIRT_BASE
+#define TIMERS_VIRT_BASE PXA1928_TIMERS2_VIRT_BASE
+#endif
+
+#ifdef CONFIG_CPU_PXA1986
+/* Timestamp unit registers */
+#define TIMESTAMP_VIRT_BASE (APB_VIRT_BASE + 0x32A000)
+#define TIMESTAMP_CTRL (0)
+#endif
+
+#endif /* __ASM_MACH_REGS_TIMERS_H */
diff --git a/marvell/linux/include/soc/asr/regs-usb.h b/marvell/linux/include/soc/asr/regs-usb.h
new file mode 100644
index 0000000..b047bf4
--- /dev/null
+++ b/marvell/linux/include/soc/asr/regs-usb.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_ARCH_REGS_USB_H
+#define __ASM_ARCH_REGS_USB_H
+
+#define PXA168_U2O_REGBASE (0xd4208000)
+#define PXA168_U2O_PHYBASE (0xd4207000)
+
+#define PXA168_U2H_REGBASE (0xd4209000)
+#define PXA168_U2H_PHYBASE (0xd4206000)
+
+#define MMP3_HSIC1_REGBASE (0xf0001000)
+#define MMP3_HSIC1_PHYBASE (0xf0001800)
+
+#define MMP3_HSIC2_REGBASE (0xf0002000)
+#define MMP3_HSIC2_PHYBASE (0xf0002800)
+
+#define MMP3_FSIC_REGBASE (0xf0003000)
+#define MMP3_FSIC_PHYBASE (0xf0003800)
+
+
+#define USB_REG_RANGE (0x1ff)
+#define USB_PHY_RANGE (0xff)
+
+/* registers */
+#define U2x_CAPREGS_OFFSET 0x100
+
+/* phy regs */
+#define UTMI_REVISION 0x0
+#define UTMI_CTRL 0x4
+#define UTMI_PLL 0x8
+#define UTMI_TX 0xc
+#define UTMI_RX 0x10
+#define UTMI_IVREF 0x14
+#define UTMI_T0 0x18
+#define UTMI_T1 0x1c
+#define UTMI_T2 0x20
+#define UTMI_T3 0x24
+#define UTMI_T4 0x28
+#define UTMI_T5 0x2c
+#define UTMI_RESERVE 0x30
+#define UTMI_USB_INT 0x34
+#define UTMI_DBG_CTL 0x38
+#define UTMI_OTG_ADDON 0x3c
+
+/* For UTMICTRL Register */
+#define UTMI_CTRL_USB_CLK_EN (1 << 31)
+/* pxa168 */
+#define UTMI_CTRL_SUSPEND_SET1 (1 << 30)
+#define UTMI_CTRL_SUSPEND_SET2 (1 << 29)
+#define UTMI_CTRL_RXBUF_PDWN (1 << 24)
+#define UTMI_CTRL_TXBUF_PDWN (1 << 11)
+
+#define UTMI_CTRL_INPKT_DELAY_SHIFT 30
+#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28
+#define UTMI_CTRL_PU_REF_SHIFT 20
+#define UTMI_CTRL_ARC_PULLDN_SHIFT 12
+#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1
+#define UTMI_CTRL_PWR_UP_SHIFT 0
+
+/* For UTMI_PLL Register */
+#define UTMI_PLL_PLLCALI12_SHIFT 29
+#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29)
+
+#define UTMI_PLL_PLLVDD18_SHIFT 27
+#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27)
+
+#define UTMI_PLL_PLLVDD12_SHIFT 25
+#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25)
+
+#define UTMI_PLL_CLK_BLK_EN_SHIFT 24
+#define CLK_BLK_EN (0x1 << 24)
+#define PLL_READY (0x1 << 23)
+#define KVCO_EXT (0x1 << 22)
+#define VCOCAL_START (0x1 << 21)
+
+#define UTMI_PLL_KVCO_SHIFT 15
+#define UTMI_PLL_KVCO_MASK (0x7 << 15)
+
+#define UTMI_PLL_ICP_SHIFT 12
+#define UTMI_PLL_ICP_MASK (0x7 << 12)
+
+#define UTMI_PLL_FBDIV_SHIFT 4
+#define UTMI_PLL_FBDIV_MASK (0xFF << 4)
+
+#define UTMI_PLL_REFDIV_SHIFT 0
+#define UTMI_PLL_REFDIV_MASK (0xF << 0)
+
+/* For UTMI_TX Register */
+#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27
+#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27)
+
+#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26
+#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26)
+
+#define UTMI_TX_TXVDD12_SHIFT 22
+#define UTMI_TX_TXVDD12_MASK (0x3 << 22)
+
+#define UTMI_TX_CK60_PHSEL_SHIFT 17
+#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17)
+
+#define UTMI_TX_IMPCAL_VTH_SHIFT 14
+#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14)
+
+#define REG_RCAL_START (0x1 << 12)
+
+#define UTMI_TX_LOW_VDD_EN_SHIFT 11
+
+#define UTMI_TX_AMP_SHIFT 0
+#define UTMI_TX_AMP_MASK (0x7 << 0)
+
+/* For UTMI_RX Register */
+#define UTMI_REG_SQ_LENGTH_SHIFT 15
+#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15)
+
+#define UTMI_RX_SQ_THRESH_SHIFT 4
+#define UTMI_RX_SQ_THRESH_MASK (0xf << 4)
+
+#define UTMI_OTG_ADDON_OTG_ON (1 << 0)
+
+/* For MMP3 USB Phy */
+#define USB2_PLL_REG0 0x4
+#define USB2_PLL_REG1 0x8
+#define USB2_TX_REG0 0x10
+#define USB2_TX_REG1 0x14
+#define USB2_TX_REG2 0x18
+#define USB2_RX_REG0 0x20
+#define USB2_RX_REG1 0x24
+#define USB2_RX_REG2 0x28
+#define USB2_ANA_REG0 0x30
+#define USB2_ANA_REG1 0x34
+#define USB2_ANA_REG2 0x38
+#define USB2_DIG_REG0 0x3C
+#define USB2_DIG_REG1 0x40
+#define USB2_DIG_REG2 0x44
+#define USB2_DIG_REG3 0x48
+#define USB2_TEST_REG0 0x4C
+#define USB2_TEST_REG1 0x50
+#define USB2_TEST_REG2 0x54
+#define USB2_CHARGER_REG0 0x58
+#define USB2_OTG_REG0 0x5C
+#define USB2_PHY_MON0 0x60
+#define USB2_RESETVE_REG0 0x64
+#define USB2_ICID_REG0 0x78
+#define USB2_ICID_REG1 0x7C
+
+/* USB2_PLL_REG0 */
+/* This is for Ax stepping */
+#define USB2_PLL_FBDIV_SHIFT_MMP3 0
+#define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0)
+
+#define USB2_PLL_REFDIV_SHIFT_MMP3 8
+#define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8)
+
+#define USB2_PLL_VDD12_SHIFT_MMP3 12
+#define USB2_PLL_VDD18_SHIFT_MMP3 14
+
+/* This is for B0 stepping */
+#define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0
+#define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9
+#define USB2_PLL_VDD18_SHIFT_MMP3_B0 14
+#define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF
+#define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00
+
+#define USB2_PLL_CAL12_SHIFT_MMP3 0
+#define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0)
+
+#define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2
+
+#define USB2_PLL_KVCO_SHIFT_MMP3 4
+#define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4)
+
+#define USB2_PLL_ICP_SHIFT_MMP3 8
+#define USB2_PLL_ICP_MASK_MMP3 (0x7<<8)
+
+#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12
+
+#define USB2_PLL_PU_PLL_SHIFT_MMP3 13
+#define USB2_PLL_PU_PLL_MASK (0x1 << 13)
+
+#define USB2_PLL_READY_MASK_MMP3 (0x1 << 15)
+
+/* USB2_TX_REG0 */
+#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8
+#define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8)
+
+#define USB2_TX_RCAL_START_SHIFT_MMP3 13
+
+/* USB2_TX_REG1 */
+#define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0
+#define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0)
+
+#define USB2_TX_AMP_SHIFT_MMP3 4
+#define USB2_TX_AMP_MASK_MMP3 (0x7 << 4)
+
+#define USB2_TX_VDD12_SHIFT_MMP3 8
+#define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8)
+
+/* USB2_TX_REG2 */
+#define USB2_TX_DRV_SLEWRATE_SHIFT 10
+
+/* USB2_RX_REG0 */
+#define USB2_RX_SQ_THRESH_SHIFT_MMP3 4
+#define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4)
+
+#define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10
+#define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10)
+
+/* USB2_ANA_REG1*/
+#define USB2_ANA_PU_ANA_SHIFT_MMP3 14
+
+/* USB2_OTG_REG0 */
+#define USB2_OTG_PU_OTG_SHIFT_MMP3 3
+
+/* fsic registers */
+#define FSIC_MISC 0x4
+#define FSIC_INT 0x28
+#define FSIC_CTRL 0x30
+
+/* HSIC registers */
+#define HSIC_PAD_CTRL 0x4
+
+#define HSIC_CTRL 0x8
+#define HSIC_CTRL_HSIC_ENABLE (1<<7)
+#define HSIC_CTRL_PLL_BYPASS (1<<4)
+
+#define TEST_GRP_0 0xc
+#define TEST_GRP_1 0x10
+
+#define HSIC_INT 0x14
+#define HSIC_INT_READY_INT_EN (1<<10)
+#define HSIC_INT_CONNECT_INT_EN (1<<9)
+#define HSIC_INT_CORE_INT_EN (1<<8)
+#define HSIC_INT_HS_READY (1<<2)
+#define HSIC_INT_CONNECT (1<<1)
+#define HSIC_INT_CORE (1<<0)
+
+#define HSIC_CONFIG 0x18
+#define USBHSIC_CTRL 0x20
+
+#define HSIC_USB_CTRL 0x28
+#define HSIC_USB_CTRL_CLKEN 1
+#define HSIC_USB_CLK_PHY 0x0
+#define HSIC_USB_CLK_PMU 0x1
+
+#endif /* __ASM_ARCH_PXA_U2O_H */
diff --git a/marvell/linux/include/soc/asr/teton_bga.h b/marvell/linux/include/soc/asr/teton_bga.h
new file mode 100644
index 0000000..61a539b
--- /dev/null
+++ b/marvell/linux/include/soc/asr/teton_bga.h
@@ -0,0 +1,27 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/teton_bga.h
+ *
+ * Support for the Marvell PXA168 Teton BGA Development Platform.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#ifndef __ASM_MACH_TETON_BGA_H
+#define __ASM_MACH_TETON_BGA_H
+
+/* GPIOs */
+#define MMC_PWENA_GPIO 27
+#define USBHPENB_GPIO 55
+#define RTC_INT_GPIO 78
+#define LCD_VBLK_EN_GPIO 79
+#define LCD_DVDD_EN_GPIO 80
+#define RST_WIFI_GPIO 81
+#define CF_PWEN_GPIO 82
+#define USB_OC_GPIO 83
+#define PWM_GPIO 84
+#define USBHPENA_GPIO 85
+#define TS_INT_GPIO 86
+#define CIR_GPIO 108
+
+#endif /* __ASM_MACH_TETON_BGA_H */
diff --git a/marvell/linux/include/soc/asr/timex.h b/marvell/linux/include/soc/asr/timex.h
new file mode 100644
index 0000000..70c9f1d
--- /dev/null
+++ b/marvell/linux/include/soc/asr/timex.h
@@ -0,0 +1,13 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/timex.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifdef CONFIG_CPU_MMP2
+#define CLOCK_TICK_RATE 6500000
+#else
+#define CLOCK_TICK_RATE 3250000
+#endif
diff --git a/marvell/linux/include/soc/asr/uio_timestamp.h b/marvell/linux/include/soc/asr/uio_timestamp.h
new file mode 100644
index 0000000..a6994da
--- /dev/null
+++ b/marvell/linux/include/soc/asr/uio_timestamp.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-pxa/include/mach/timestamp.h
+ *
+ * PXA timestamp unit
+ *
+ * Oleksandr Krol <akrol@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ * (c) 2012
+ *
+ */
+
+#ifndef _TIMESTAMP_H
+#define _TIMESTAMP_H
+
+void timestamp_enable_cnt(void);
+void timestamp_disable_cnt(void);
+
+#endif /* _TIMESTAMP_H */
diff --git a/marvell/linux/include/soc/asr/uncompress.h b/marvell/linux/include/soc/asr/uncompress.h
new file mode 100644
index 0000000..c94e702
--- /dev/null
+++ b/marvell/linux/include/soc/asr/uncompress.h
@@ -0,0 +1,45 @@
+/*
+ * arch/arm/mach-mmp/include/soc/asr/uncompress.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_reg.h>
+#include <soc/asr/addr-map.h>
+#include <asm/mach-types.h>
+
+#define UART1_BASE (APB_PHYS_BASE + 0x36000)
+#define UART2_BASE (APB_PHYS_BASE + 0x17000)
+#define UART3_BASE (APB_PHYS_BASE + 0x18000)
+
+volatile unsigned long *UART;
+
+static inline void putc(char c)
+{
+ /* UART enabled? */
+ if (!(UART[UART_IER] & UART_IER_UUE))
+ return;
+
+ while (!(UART[UART_LSR] & UART_LSR_THRE))
+ barrier();
+
+ UART[UART_TX] = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+ /* default to UART2 */
+ UART = (unsigned long *)UART2_BASE;
+
+ if (machine_is_avengers_lite())
+ UART = (unsigned long *)UART3_BASE;
+}
diff --git a/marvell/linux/include/soc/asr/wakeup_defines.h b/marvell/linux/include/soc/asr/wakeup_defines.h
new file mode 100644
index 0000000..9f6bbae
--- /dev/null
+++ b/marvell/linux/include/soc/asr/wakeup_defines.h
@@ -0,0 +1,108 @@
+#ifndef __ASR_WAKEUP_DEFINES_H
+#define __ASR_WAKEUP_DEFINES_H
+
+enum main_wakeup_list {
+ MAIN_WAKEUP_UNKNOW = 0,
+ MAIN_WAKEUP_GSM,
+ MAIN_WAKEUP_3GBB,
+ /* sub id of gpio wakeup is GPIO number */
+ MAIN_WAKEUP_GPIO,
+ MAIN_WAKEUP_KEYPRESS,
+ MAIN_WAKEUP_TRACKBALL,
+ MAIN_WAKEUP_GMAC,
+ MAIN_WAKEUP_NEWROTARY,
+ MAIN_WAKEUP_WDT,
+ MAIN_WAKEUP_RTCALARM,
+ MAIN_WAKEUP_AP_TIMER0_2_TIMER1,
+ MAIN_WAKEUP_AP_TIMER0_2_TIMER2,
+ MAIN_WAKEUP_AP_TIMER0_2_TIMER3,
+ MAIN_WAKEUP_AP_TIMER1_1,
+ MAIN_WAKEUP_AP_TIMER1_2,
+ MAIN_WAKEUP_AP_TIMER1_3,
+ MAIN_WAKEUP_CP_TIMER1,
+ MAIN_WAKEUP_CP_TIMER2,
+ MAIN_WAKEUP_CP_TIMER3,
+ /* sub id of IRQ wakeup is the irq number,
+ * check /proc/interrupts to get the detailed info
+ */
+ MAIN_WAKEUP_IRQ,
+ MAIN_WAKEUP_USB,
+ MAIN_WAKEUP_SQU_SDH1,
+ MAIN_WAKEUP_SDH23_HSI,
+ MAIN_WAKEUP_PMIC,
+ MAIN_WAKEUP_CP_IPC,
+ MAIN_WAKEUP_MISC,
+};
+
+#define GPIO_INT_HIGH_LELVE_NUM (1000)
+
+#define MAX_MAIN_WAKEUP_EVENT 6
+#define MAX_GPIO_WAKEUP_EVENT 6
+#define MAX_IRQ_WAKEUP_EVENT 6
+#define MAX_GPIO_INT_WAKEUP_EVENT 6
+
+struct pm_wakeup_status {
+ u32 sys_main_wakeup_id[MAX_MAIN_WAKEUP_EVENT];
+ u32 sys_gpio_wakeup_id[MAX_GPIO_WAKEUP_EVENT];
+ u32 sys_irq_wakeup_id[MAX_IRQ_WAKEUP_EVENT];
+ u16 main_wakeup_idx;
+ u16 gpio_wakeup_idx;
+ u16 irq_wakeup_idx;
+};
+
+/* sub id of MAIN_WAKEUP_CP_IPC definition */
+union cp_wakeup_struct {
+ struct {
+ unsigned int service_id:16;
+ unsigned int service_grp:8;
+ unsigned int reserved:3;
+ unsigned int wakeup_main_id:4;
+ unsigned int is_cp_wakeup:1;
+ } b;
+ unsigned int val;
+};
+
+enum {
+ CP_WAKEUP_MASTER_UNKNOWN = 0,
+ CP_WAKEUP_MASTER_PSD,
+ CP_WAKEUP_MASTER_MSOCKET,
+ CP_WAKEUP_MASTER_DIAG,
+};
+
+enum {
+ CP_WAKEUP_MAINID_UNKNOWN = 0,
+ CP_WAKEUP_MAINID_CI,
+ CP_WAKEUP_MAINID_NVM,
+ CP_WAKEUP_MAINID_IMS,
+ CP_WAKEUP_MAINID_AUDIO,
+ CP_WAKEUP_MAINID_DIAG,
+ CP_WAKEUP_MAINID_PSD,
+ CP_WAKEUP_MAINID_CISH,
+};
+
+//sub id of GPIO wakeup is the GPIO number,
+//CP wakeup: read the sub id from telephony subsys
+enum sub_sub_list {
+ SUB_WAKEUP_UNKNOW = 0,
+};
+
+
+#define AP_WAKEUP_IOC_MAGIC 'W'
+#define AP_WAKEUP_ENABLE_WAKEUP _IOW(AP_WAKEUP_IOC_MAGIC, 1, int)
+#define AP_WAKEUP_DISABLE_WAKEUP _IOW(AP_WAKEUP_IOC_MAGIC, 2, int)
+
+
+struct ap_wkup_ioctl_arg {
+ u32 arg1;
+ u32 arg2;
+};
+
+
+enum wakeup_source_ctrl_list {
+ AP_WAKEUP_UNKNOWN,
+ AP_WAKEUP_RTC,
+ AP_WAKEUP_GPIO,
+ AP_WAKEUP_UART,
+};
+
+#endif /* __ASR_WAKEUP_DEFINES_H */