ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/obm/Common/SDRam/ddr_test.h b/marvell/obm/Common/SDRam/ddr_test.h
new file mode 100644
index 0000000..402d409
--- /dev/null
+++ b/marvell/obm/Common/SDRam/ddr_test.h
@@ -0,0 +1,30 @@
+#ifndef __DDR_TEST_H__
+#define __DDR_TEST_H__
+
+
+#define NR_TEST_PATTERN 16
+
+#ifndef data_write32
+#define data_write32(ptrReg, value) \
+ (*((u32 *)(ptrReg)) = value)
+#endif
+
+#ifndef data_read32
+#define data_read32(ptrReg) \
+ (*((u32 *)(ptrReg)))
+#endif
+
+#define DDR_TEST_PASS (0)
+#define DDR_TEST_FAIL (1)
+
+
+//enable CONFIG_USE_DDR_ALL_PATTERN as obm only test [20M -> tos end address]
+#define CONFIG_USE_DDR_ALL_PATTERN 1
+
+typedef unsigned int u32;
+
+//for extern call
+u32 asr_ddr_pattern_test(u32 uiStartBase, u32 uiSize);
+
+#endif
+