ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/uboot/arch/avr32/lib/interrupts.c b/marvell/uboot/arch/avr32/lib/interrupts.c
new file mode 100644
index 0000000..bacb2d1
--- /dev/null
+++ b/marvell/uboot/arch/avr32/lib/interrupts.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+#include <asm/sysreg.h>
+
+void enable_interrupts(void)
+{
+ asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET));
+}
+
+int disable_interrupts(void)
+{
+ unsigned long sr;
+
+ sr = sysreg_read(SR);
+ asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET));
+
+#ifdef CONFIG_AT32UC3A0xxx
+ /* Two NOPs are required after masking interrupts on the
+ * AT32UC3A0512ES. See errata 41.4.5.5. */
+ asm("nop");
+ asm("nop");
+#endif
+
+ return !SYSREG_BFEXT(GM, sr);
+}