ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/marvell/uboot/arch/sparc/include/asm/cache.h b/marvell/uboot/arch/sparc/include/asm/cache.h
new file mode 100644
index 0000000..d9671d1
--- /dev/null
+++ b/marvell/uboot/arch/sparc/include/asm/cache.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2008,
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SPARC_CACHE_H__
+#define __SPARC_CACHE_H__
+
+#include <asm/processor.h>
+
+/*
+ * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
+ * use 32-bytes, the cacheline size for Sparc.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 32
+#endif
+
+#endif