ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/target/linux/layerscape/patches-5.4/302-dts-0084-arm64-dts-ls1028a-define-networking-options-for-QDS.patch b/target/linux/layerscape/patches-5.4/302-dts-0084-arm64-dts-ls1028a-define-networking-options-for-QDS.patch
new file mode 100644
index 0000000..8680f34
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/302-dts-0084-arm64-dts-ls1028a-define-networking-options-for-QDS.patch
@@ -0,0 +1,355 @@
+From 0c767bcfe1b4d940f2889820f12d278cbba764b5 Mon Sep 17 00:00:00 2001
+From: Alex Marginean <alexandru.marginean@nxp.com>
+Date: Tue, 27 Aug 2019 15:12:00 +0300
+Subject: [PATCH] arm64: dts: ls1028a: define networking options for QDS
+
+Defines connectivity for a few serdes protocol combinations (85xx, 65xx,
+13xx, 9999, 7777).
+
+Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
+---
+ .../boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi | 20 ++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi | 20 ++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi | 56 ++++++++++++++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi | 19 +++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi | 60 ++++++++++++++++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi | 48 +++++++++++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi | 44 ++++++++++++++++
+ arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 27 ++++++++++
+ 8 files changed, 294 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi
+@@ -0,0 +1,20 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for LS1028A QDS board, serdes 1xxx
++ *
++ * Copyright 2019 NXP
++ *
++ */
++
++&mdio_slot1 {
++ slot1_sgmii: ethernet-phy@2 {
++ /* AQR112 */
++ reg = <0x2>;
++ compatible = "ethernet-phy-ieee802.3-c45";
++ };
++};
++
++&enetc_port0 {
++ phy-handle = <&slot1_sgmii>;
++ phy-connection-type = "usxgmii";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi
+@@ -0,0 +1,20 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for LS1028A QDS board, serdes 6xxx
++ *
++ * Copyright 2019 NXP
++ *
++ */
++
++&mdio_slot1 {
++ slot1_sgmii: ethernet-phy@2 {
++ /* AQR112 */
++ reg = <0x2>;
++ compatible = "ethernet-phy-ieee802.3-c45";
++ };
++};
++
++&enetc_port0 {
++ phy-handle = <&slot1_sgmii>;
++ phy-connection-type = "2500base-x";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
+@@ -0,0 +1,56 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for LS1028A QDS board, serdes 9999
++ *
++ * Copyright 2019 NXP
++ *
++ */
++
++&mdio_slot1 {
++ /* two ports on AQR412 */
++ slot1_sxgmii2: ethernet-phy@2 {
++ reg = <0x2>;
++ compatible = "ethernet-phy-ieee802.3-c45";
++ };
++ slot1_sxgmii3: ethernet-phy@3 {
++ reg = <0x3>;
++ compatible = "ethernet-phy-ieee802.3-c45";
++ };
++};
++
++&mdio_slot2 {
++ slot2_sxgmii0: ethernet-phy@2 {
++ /* AQR112 */
++ reg = <0x2>;
++ compatible = "ethernet-phy-ieee802.3-c45";
++ };
++};
++
++&mdio_slot3 {
++ slot3_sxgmii0: ethernet-phy@2 {
++ /* AQR112 */
++ reg = <0x2>;
++ compatible = "ethernet-phy-ieee802.3-c45";
++ };
++};
++
++/* l2switch ports */
++&switch_port0 {
++ phy-handle = <&slot1_sxgmii2>;
++ phy-connection-type = "2500base-x";
++};
++
++&switch_port1 {
++ phy-handle = <&slot2_sxgmii0>;
++ phy-connection-type = "2500base-x";
++};
++
++&switch_port2 {
++ phy-handle = <&slot3_sxgmii0>;
++ phy-connection-type = "2500base-x";
++};
++
++&switch_port3 {
++ phy-handle = <&slot1_sxgmii3>;
++ phy-connection-type = "2500base-x";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi
+@@ -0,0 +1,19 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for LS1028A QDS board, serdes 8xxx
++ *
++ * Copyright 2019 NXP
++ *
++ */
++
++&mdio_slot1 {
++ slot1_sgmii: ethernet-phy@1c {
++ /* 1st port on VSC8234 */
++ reg = <0x1c>;
++ };
++};
++
++&enetc_port0 {
++ phy-handle = <&slot1_sgmii>;
++ phy-connection-type = "sgmii";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
+@@ -0,0 +1,60 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for LS1028A QDS board, serdes 9999
++ *
++ * Copyright 2019 NXP
++ *
++ */
++
++&mdio_slot1 {
++ /* VSC8234 */
++ slot1_sgmii0: ethernet-phy@1c {
++ reg = <0x1c>;
++ };
++ slot1_sgmii1: ethernet-phy@1d {
++ reg = <0x1d>;
++ };
++ slot1_sgmii2: ethernet-phy@1e {
++ reg = <0x1e>;
++ };
++ slot1_sgmii3: ethernet-phy@1f {
++ reg = <0x1f>;
++ };
++};
++
++&mdio_slot2 {
++ /* VSC8234 */
++ slot2_sgmii0: ethernet-phy@1c {
++ reg = <0x1c>;
++ };
++ slot2_sgmii1: ethernet-phy@1d {
++ reg = <0x1d>;
++ };
++ slot2_sgmii2: ethernet-phy@1e {
++ reg = <0x1e>;
++ };
++ slot2_sgmii3: ethernet-phy@1f {
++ reg = <0x1f>;
++ };
++};
++
++/* l2switch ports */
++&switch_port0 {
++ phy-handle = <&slot1_sgmii0>;
++ phy-connection-type = "sgmii";
++};
++
++&switch_port1 {
++ phy-handle = <&slot2_sgmii0>;
++ phy-connection-type = "sgmii";
++};
++
++&switch_port2 {
++ phy-handle = <&slot1_sgmii2>;
++ phy-connection-type = "sgmii";
++};
++
++&switch_port3 {
++ phy-handle = <&slot1_sgmii3>;
++ phy-connection-type = "sgmii";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
+@@ -0,0 +1,48 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for LS1028A QDS board, serdes x3xx
++ *
++ * Copyright 2019 NXP
++ *
++ */
++
++&mdio_slot2 {
++ /* 4 ports on AQR412 */
++ slot2_qsgmii0: ethernet-phy@0 {
++ reg = <0x0>;
++ compatible = "ethernet-phy-ieee802.3-c45";
++ };
++ slot2_qsgmii1: ethernet-phy@1 {
++ reg = <0x1>;
++ compatible = "ethernet-phy-ieee802.3-c45";
++ };
++ slot2_qsgmii2: ethernet-phy@2 {
++ reg = <0x2>;
++ compatible = "ethernet-phy-ieee802.3-c45";
++ };
++ slot2_qsgmii3: ethernet-phy@3 {
++ reg = <0x3>;
++ compatible = "ethernet-phy-ieee802.3-c45";
++ };
++};
++
++/* l2switch ports */
++&switch_port0 {
++ phy-handle = <&slot2_qsgmii0>;
++ phy-connection-type = "usxgmii";
++};
++
++&switch_port1 {
++ phy-handle = <&slot2_qsgmii1>;
++ phy-connection-type = "usxgmii";
++};
++
++&switch_port2 {
++ phy-handle = <&slot2_qsgmii2>;
++ phy-connection-type = "usxgmii";
++};
++
++&switch_port3 {
++ phy-handle = <&slot2_qsgmii3>;
++ phy-connection-type = "usxgmii";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
+@@ -0,0 +1,44 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for LS1028A QDS board, serdes x5xx
++ *
++ * Copyright 2019 NXP
++ *
++ */
++
++&mdio_slot2 {
++ /* 4 ports on VSC8514 */
++ slot2_qsgmii0: ethernet-phy@8 {
++ reg = <0x8>;
++ };
++ slot2_qsgmii1: ethernet-phy@9 {
++ reg = <0x9>;
++ };
++ slot2_qsgmii2: ethernet-phy@a {
++ reg = <0xa>;
++ };
++ slot2_qsgmii3: ethernet-phy@b {
++ reg = <0xb>;
++ };
++};
++
++/* l2switch ports */
++&switch_port0 {
++ phy-handle = <&slot2_qsgmii0>;
++ phy-connection-type = "qsgmii";
++};
++
++&switch_port1 {
++ phy-handle = <&slot2_qsgmii1>;
++ phy-connection-type = "qsgmii";
++};
++
++&switch_port2 {
++ phy-handle = <&slot2_qsgmii2>;
++ phy-connection-type = "qsgmii";
++};
++
++&switch_port3 {
++ phy-handle = <&slot2_qsgmii3>;
++ phy-connection-type = "qsgmii";
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+@@ -104,6 +104,30 @@
+ reg = <5>;
+ };
+ };
++
++ mdio_slot1: mdio@4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ };
++
++ mdio_slot2: mdio@5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ };
++
++ mdio_slot3: mdio@6 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <6>;
++ };
++
++ mdio_slot4: mdio@7 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <7>;
++ };
+ };
+ };
+
+@@ -260,3 +284,6 @@
+ edp_num_lanes = <0x4>;
+ status = "okay";
+ };
++
++#include "fsl-ls1028a-qds-8xxx.dtsi"
++#include "fsl-ls1028a-qds-x5xx.dtsi"