ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/target/linux/layerscape/patches-5.4/302-dts-0100-arm64-dts-ls208xa-Update-qspi-node-properties-for-LS.patch b/target/linux/layerscape/patches-5.4/302-dts-0100-arm64-dts-ls208xa-Update-qspi-node-properties-for-LS.patch
new file mode 100644
index 0000000..6efbe1e
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/302-dts-0100-arm64-dts-ls208xa-Update-qspi-node-properties-for-LS.patch
@@ -0,0 +1,64 @@
+From 121cd10d9ec4466b09ac33986c7b4c1f8eff9363 Mon Sep 17 00:00:00 2001
+From: Kuldeep Singh <kuldeep.singh@nxp.com>
+Date: Wed, 18 Dec 2019 15:09:41 +0530
+Subject: [PATCH] arm64: dts: ls208xa: Update qspi node properties for
+ LS2088ARDB
+
+LS2088ADB has one spansion flash s25fs512s of size 64M.
+
+Update qspi dts entry for the board using compatibles as "jedec,spi-nor"
+to probe flash successfully. Also, align properties with other board dts
+properties.
+
+Since device properties are different, so remove fsl, ls1021a-qspi.
+ls1021a-qspi is to be used only for Big-endian verion of QSPI
+controller. Use dt-bindings constants in interrupts instead of using
+numbers.
+
+Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 8 ++++----
+ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 6 +++---
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+@@ -110,12 +110,12 @@
+
+ &qspi {
+ status = "okay";
+- flash0: s25fs512s@0 {
++
++ s25fs512s0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+- compatible = "spansion,m25p80";
+- m25p,fast-read;
+- spi-max-frequency = <20000000>;
++ compatible = "jedec,spi-nor";
++ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+@@ -609,16 +609,16 @@
+ };
+
+ qspi: spi@20c0000 {
+- status = "disabled";
+- compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
++ compatible = "fsl,ls2080a-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+- interrupts = <0 25 0x4>; /* Level high type */
++ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "qspi_en", "qspi";
++ status = "disabled";
+ };
+
+ pcie1: pcie@3400000 {