ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/target/linux/layerscape/patches-5.4/801-audio-0019-MLK-13609-ASoC-fsl_sai-fix-for-synchronize-mode.patch b/target/linux/layerscape/patches-5.4/801-audio-0019-MLK-13609-ASoC-fsl_sai-fix-for-synchronize-mode.patch
new file mode 100644
index 0000000..40915d4
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/801-audio-0019-MLK-13609-ASoC-fsl_sai-fix-for-synchronize-mode.patch
@@ -0,0 +1,56 @@
+From 7b5c62dc6c1de58ee1d527059ae69152ed1380f2 Mon Sep 17 00:00:00 2001
+From: Shengjiu Wang <shengjiu.wang@freescale.com>
+Date: Mon, 12 Dec 2016 11:52:24 +0800
+Subject: [PATCH] MLK-13609: ASoC: fsl_sai: fix for synchronize mode
+
+TX synchronous with receiver: the RMR should not be changed and
+the RCSR.RE should be set in playback.
+RX synchronous with transmitter: the TMR should not be changed and
+the TCSR.TE should be set in recording.
+
+Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
+---
+ sound/soc/fsl/fsl_sai.c | 15 ++++++++-------
+ 1 file changed, 8 insertions(+), 7 deletions(-)
+
+--- a/sound/soc/fsl/fsl_sai.c
++++ b/sound/soc/fsl/fsl_sai.c
+@@ -528,8 +528,6 @@ static int fsl_sai_hw_params(struct snd_
+ regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
+ FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
+ FSL_SAI_CR5_FBT_MASK, val_cr5);
+- regmap_write(sai->regmap, FSL_SAI_TMR,
+- ~0UL - ((1 << channels) - 1));
+ } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
+ regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
+ FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
+@@ -537,8 +535,6 @@ static int fsl_sai_hw_params(struct snd_
+ regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
+ FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
+ FSL_SAI_CR5_FBT_MASK, val_cr5);
+- regmap_write(sai->regmap, FSL_SAI_RMR,
+- ~0UL - ((1 << channels) - 1));
+ }
+ }
+
+@@ -627,12 +623,17 @@ static int fsl_sai_trigger(struct snd_pc
+ if (tx)
+ udelay(10);
+
+- regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
+- FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
+- regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
++ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
+ FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
+ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
+ FSL_SAI_CSR_SE, FSL_SAI_CSR_SE);
++ if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
++ regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx)),
++ FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
++ } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
++ regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx)),
++ FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
++ }
+
+ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
+ FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);