commit e958203796650e3959a43708d67534bf36f4c83b
author b.liu <b.liu@mobiletek.cn> Thu Apr 17 19:18:16 2025 +0800
committer b.liu <b.liu@mobiletek.cn> Thu Apr 17 19:18:16 2025 +0800
tree b2d43b7c77053224287779c12b5e890cadc3d327
parent f51a5559b56d8fd47d9623531065443befb43e5b

ASR_BASE

Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1

target/linux/layerscape/patches-5.4/802-can-0013-can-flexcan-convert-struct-flexcan_priv-rx_mask-1-2-.patch

diff --git a/target/linux/layerscape/patches-5.4/802-can-0013-can-flexcan-convert-struct-flexcan_priv-rx_mask-1-2-.patch b/target/linux/layerscape/patches-5.4/802-can-0013-can-flexcan-convert-struct-flexcan_priv-rx_mask-1-2-.patch
new file mode 100644
index 0000000..9533726
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/802-can-0013-can-flexcan-convert-struct-flexcan_priv-rx_mask-1-2-.patch
@@ -0,0 +1,107 @@
+From 6adf87956ee1043e6bf0ef83fa0eec1e755c0d48 Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Fri, 1 Mar 2019 12:17:30 +0100
+Subject: [PATCH] can: flexcan: convert struct flexcan_priv::rx_mask{1,2} to
+ rx_mask
+
+The flexcan IP core has up to 64 mailboxes, each one has a corresponding
+interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
+imask1 or imask2 registers.
+
+In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX
+interrupt sources and uses the precomputed values rx_mask1 and rx_mask2 of
+struct flexcan_priv for this.
+
+This patch merges the two u32 rx_mask1 and rx_mask2 to a single u64 rx_mask
+variable, which simplifies the code a bit.
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+---
+ drivers/net/can/flexcan.c | 30 +++++++++++++-----------------
+ 1 file changed, 13 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/can/flexcan.c
++++ b/drivers/net/can/flexcan.c
+@@ -142,6 +142,7 @@
+ #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO		8
+ #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP	0
+ #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST	(FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
++#define FLEXCAN_IFLAG_MB(x)		BIT_ULL(x)
+ #define FLEXCAN_IFLAG2_MB(x)		BIT((x) & 0x1f)
+ #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW	BIT(7)
+ #define FLEXCAN_IFLAG_RX_FIFO_WARN	BIT(6)
+@@ -277,9 +278,8 @@ struct flexcan_priv {
+ 	u8 mb_size;
+ 	u8 clk_src;	/* clock source of CAN Protocol Engine */
+ 
++	u64 rx_mask;
+ 	u32 reg_ctrl_default;
+-	u32 rx_mask1;
+-	u32 rx_mask2;
+ 
+ 	struct clk *clk_ipg;
+ 	struct clk *clk_per;
+@@ -880,16 +880,15 @@ static struct sk_buff *flexcan_mailbox_r
+ 	return skb;
+ }
+ 
+-
+ static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
+ {
+ 	struct flexcan_regs __iomem *regs = priv->regs;
+-	u32 iflag1, iflag2;
++	u64 iflag;
+ 
+-	iflag2 = priv->read(&regs->iflag2) & priv->rx_mask2;
+-	iflag1 = priv->read(&regs->iflag1) & priv->rx_mask1;
++	iflag = (u64)priv->read(&regs->iflag2) << 32 |
++		priv->read(&regs->iflag1);
+ 
+-	return (u64)iflag2 << 32 | iflag1;
++	return iflag & priv->rx_mask;
+ }
+ 
+ static irqreturn_t flexcan_irq(int irq, void *dev_id)
+@@ -1060,6 +1059,7 @@ static int flexcan_chip_start(struct net
+ 	struct flexcan_priv *priv = netdev_priv(dev);
+ 	struct flexcan_regs __iomem *regs = priv->regs;
+ 	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
++	u64 reg_imask;
+ 	int err, i;
+ 	struct flexcan_mb __iomem *mb;
+ 
+@@ -1232,8 +1232,9 @@ static int flexcan_chip_start(struct net
+ 	/* enable interrupts atomically */
+ 	disable_irq(dev->irq);
+ 	priv->write(priv->reg_ctrl_default, &regs->ctrl);
+-	priv->write(priv->rx_mask1, &regs->imask1);
+-	priv->write(priv->rx_mask2 | FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), &regs->imask2);
++	reg_imask = priv->rx_mask | FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
++	priv->write(upper_32_bits(reg_imask), &regs->imask2);
++	priv->write(lower_32_bits(reg_imask), &regs->imask1);
+ 	enable_irq(dev->irq);
+ 
+ 	/* print chip status */
+@@ -1330,19 +1331,14 @@ static int flexcan_open(struct net_devic
+ 	priv->offload.mailbox_read = flexcan_mailbox_read;
+ 
+ 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
+-		u64 imask;
+-
+ 		priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
+ 		priv->offload.mb_last = priv->mb_count - 2;
+ 
+-		imask = GENMASK_ULL(priv->offload.mb_last,
+-				    priv->offload.mb_first);
+-		priv->rx_mask1 = imask;
+-		priv->rx_mask2 = imask >> 32;
+-
++		priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
++					    priv->offload.mb_first);
+ 		err = can_rx_offload_add_timestamp(dev, &priv->offload);
+ 	} else {
+-		priv->rx_mask1 = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
++		priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
+ 			FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
+ 		err = can_rx_offload_add_fifo(dev, &priv->offload,
+ 					      FLEXCAN_NAPI_WEIGHT);