ASR_BASE
Change-Id: Icf3719cc0afe3eeb3edc7fa80a2eb5199ca9dda1
diff --git a/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch b/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch
new file mode 100644
index 0000000..2635c7a
--- /dev/null
+++ b/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch
@@ -0,0 +1,62 @@
+From: William Wu <william.wu@rock-chips.com>
+
+RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
+core's general architecture. It can act as static xHCI host
+controller, static device controller, USB 3.0/2.0 OTG basing
+on ID of USB3.0 PHY.
+
+Signed-off-by: William Wu <william.wu@rock-chips.com>
+Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
+
+---
+
+NOTE: This binding still has issues. From the original thread:
+
+the rk3328 usb3-phy has an issue with detecting any plugin events
+after a previous device got removed - see the inno-usb3-phy driver
+in the vendor kernel.
+
+The current state is good-enough for enabling the USB3 attached LAN
+port of the NanoPi R2S. However, it might explode depending on your
+use-case. You've been warned.
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -938,6 +938,33 @@
+ status = "disabled";
+ };
+
++ usbdrd3: usb@ff600000 {
++ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
++ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
++ <&cru ACLK_USB3OTG>;
++ clock-names = "ref_clk", "suspend_clk",
++ "bus_clk";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++ status = "disabled";
++
++ usbdrd_dwc3: dwc3@ff600000 {
++ compatible = "snps,dwc3";
++ reg = <0x0 0xff600000 0x0 0x100000>;
++ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
++ dr_mode = "otg";
++ phy_type = "utmi_wide";
++ snps,dis_enblslpm_quirk;
++ snps,dis-u2-freeclk-exists-quirk;
++ snps,dis_u2_susphy_quirk;
++ snps,dis_u3_susphy_quirk;
++ snps,dis-del-phy-power-chg-quirk;
++ snps,dis-tx-ipgap-linecheck-quirk;
++ status = "disabled";
++ };
++ };
++
+ gic: interrupt-controller@ff811000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;