| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2023 ASR Microelectronics |
| */ |
| |
| /dts-v1/; |
| #include "asr1903.dtsi" |
| |
| #ifdef CONFIG_FB_ASR |
| /* #define CONFIG_FB_ASR_MIPI_CMD 1 */ |
| #endif |
| |
| / { |
| model = "ASR 1903(LAPWING) EVB Board"; |
| compatible = "asr,1803-evb", "asr,1803"; |
| |
| chosen { |
| bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M"; |
| }; |
| |
| memory { |
| reg = <0x00000000 0x10000000>; |
| }; |
| |
| firmware { |
| optee { |
| compatible = "linaro,optee-tz"; |
| method = "smc"; |
| }; |
| }; |
| |
| soc { |
| axi@d4200000 { /* AXI */ |
| #ifdef CONFIG_FB_ASR |
| lcd: lcd@d420a000 { |
| compatible = "asr,fb"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&lcd_pmx_func>; |
| interrupts = <42>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| reg = <0xd420a000 0x800>; |
| #ifdef CONFIG_FB_ASR_MIPI |
| dsi_base = <0xd420a800>; |
| #ifdef CONFIG_FB_ASR_MIPI_CMD |
| panel_type = <1>; /* cmd */ |
| #else |
| panel_type = <0>; /* video */ |
| #endif |
| |
| gpio_ctrl = <0>; |
| |
| #ifdef CONFIG_FB_ASR_MIPI_CMD |
| power_gpio = <&gpio 127 0>; |
| #endif |
| #endif |
| reset_gpio = <&gpio 82 0>; |
| vsync_gpio = <&gpio 81 0>; |
| //avdd-supply = <&ldo1>; |
| status = "okay"; |
| }; |
| |
| backlight: pwm_bl { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm2 50000>; |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <6>; |
| #ifdef CONFIG_FB_ASR_MIPI_CMD |
| status = "disabled"; |
| #else |
| status = "okay"; |
| #endif |
| }; |
| #endif |
| |
| usb3phy: usb3phy@c0030000 { |
| status = "okay"; |
| }; |
| #ifndef CONFIG_USB_DWC3_ASR_OTG |
| usb3_0: usb3-0 { |
| status = "okay"; |
| }; |
| #else |
| usb3_0_otg: usb3-0-otg { |
| pinctrl-names = "default","sleep"; |
| pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>; |
| pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>; |
| usbid_gpio = <99>; |
| edge_detect_gpio = <99>; |
| otg,use-gpio-vbus; |
| gpio-num = <122>; |
| status = "okay"; |
| }; |
| #endif |
| eth0: asr-eth@0xd428c000 { |
| compatible = "asr,asr-eth-v3"; |
| pinctrl-names = "default", "rgmii-pins"; |
| pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>; |
| pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>; |
| reg = <0xd428c000 0x200 |
| 0xd4228000 0x100>; |
| interrupts = <16 17 61 63>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| clocks = <&soc_clocks ASR1803_CLK_EMAC |
| &soc_clocks ASR1803_CLK_EMAC_PTP>; |
| clock-names = "emac-clk", "ptp-clk"; |
| ptp-support; |
| tso-support; |
| ptp-clk-rate = <38400000>; |
| eth,sram = <&sram>; |
| #if defined(CONFIG_FB_ASR_SPI) || defined(CONFIG_FB_ASR_MCU) |
| status = "disabled"; |
| #else |
| status = "okay"; |
| #endif |
| reset-gpio = <&gpio 20 0>; |
| reset-active-low; |
| |
| reset-delays-us = <0 100000 100000>; |
| |
| clk-tuning-enable; |
| /* clk-config(32bit) |
| * |
| * rmii_ref_clk(clk-config[31:24]) |
| * 0 - from SOC |
| * 1 - from phy |
| * clk_sel(clk-config[23:16]) |
| * RGMII: |
| * tx | clk_sel: 0 - from RX clock |
| * 1 - from SOC clock |
| * rx | clk_sel: not care |
| * |
| * RMII: |
| * tx | clk_sel: 0 - RMII clock |
| * 1 - Inverted RMII clock |
| * rx | clk_sel: 0 - RMII clock |
| * 1 - Inverted RMII clock |
| * |
| * delay_code(clk-config[15:8]) |
| * 0 ~ 255 |
| * |
| * delay_step(clk-config[7:0]) |
| * 0b000 - 28.14ps |
| * 0b001 - 37.9ps |
| * 0b010 - 32.91ps |
| * 0b011 - 52.76ps |
| */ |
| #if 1 |
| tx-clk-config = <0x0>; |
| rx-clk-config = <0x0>; |
| /* enable 1000M phy*/ |
| 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */ |
| phy-handle = <&phy0>; |
| #else |
| tx-clk-config = <0x0>; |
| rx-clk-config = <0x0>; |
| /* enable 100M phy*/ |
| 3v3-enable = <1>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */ |
| phy-handle = <&phy3>; |
| #endif |
| |
| /* enable fix link for ethernet switch */ |
| /* |
| fixed-link { |
| speed = <100>; |
| full-duplex; |
| phy-mode = "rmii"; |
| }; |
| */ |
| |
| mdio: mdio-bus { |
| #address-cells = <0x1>; |
| #size-cells = <0x0>; |
| /* YT8521 10M/100M/100OM 1.8V RGMII PHY */ |
| phy0: phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| device_type = "ethernet-phy"; |
| reg = <0x0>; /* set phy address*/ |
| phy-mode = "rgmii"; |
| tx_rx_delay = <0xb 0x1>; /* 150ps per step*/ |
| }; |
| |
| /* YT8512B 10M/100M 3.3V RMII PHY */ |
| phy3: phy@3 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| device_type = "ethernet-phy"; |
| reg = <0x3>; /* set phy address*/ |
| phy-mode = "rmii"; |
| driver_strength = <0x3>; |
| }; |
| |
| /* IP175D 10M/100M 3.3V RMII SWITCH */ |
| phy1: phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| device_type = "ethernet-phy"; |
| reg = <0x1>; /* set phy address*/ |
| phy-mode = "rmii"; |
| }; |
| }; |
| }; |
| qspi: spi@0xd420b000 { |
| asr,qspi-freq = <78000000>; |
| status = "okay"; |
| }; |
| /* SD card */ |
| sdh0: sdh@d4280000 { |
| pinctrl-names = "default", "slow", "fast"; |
| pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>; |
| pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>; |
| pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>; |
| vmmc-supply = <&vcc_sdh1>; |
| vqmmc-supply = <&pm802ldo6>; |
| bus-width = <4>; |
| no-mmc; |
| no-sdio; |
| non-removable; |
| broken-cd; |
| wp-inverted; |
| asr,sdh-pm-runtime-en; |
| asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>; |
| asr,sdh-quirks = <( |
| SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| )>; |
| asr,sdh-quirks2 = <( |
| SDHCI_QUIRK2_SET_AIB_MMC | |
| SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
| )>; |
| /* prop "sdh-dtr-data": |
| <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */ |
| asr,sdh-dtr-data = |
| <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>, |
| <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>, |
| <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>, |
| <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>, |
| <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>, |
| <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>; |
| status = "okay"; |
| }; |
| |
| /* SDIO */ |
| sdh1: sdh@d4280800 { |
| pinctrl-names = "default", "fast", "sleep"; |
| pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2 &sdh1_pmx_func3>; |
| pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast &sdh1_pmx_func3>; |
| pinctrl-2 = <&sdh1_pmx_edge_wakeup>; |
| bus-width = <4>; |
| no-mmc; |
| no-sd; |
| non-removable; |
| keep-power-in-suspend; |
| enable-sdio-wakeup; |
| /* clk-scaling-config: |
| <up_threshold down_threshold polling_interval> */ |
| clk-scaling-config = <25 12 200>; |
| min-ddr-qos = <156000 312000 400000>; |
| asr,sdh-pm-runtime-en; |
| asr,sdh-quirks = <( |
| SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| )>; |
| asr,sdh-quirks2 = <( |
| SDHCI_QUIRK2_NO_TIMER_RETUNING | |
| SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
| SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON |
| )>; |
| asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>; |
| asr,sdh-host-caps2 = <( |
| MMC_CAP2_ONLY_1_8V | |
| MMC_CAP2_DISABLE_PROBE_CDSCAN | |
| MMC_CAP2_CLK_SCALE | |
| MMC_CAP2_BUS_CLK_NO_SCALE |
| )>; |
| /* prop "sdh-dtr-data": |
| <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */ |
| asr,sdh-dtr-data = |
| <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>, |
| <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>, |
| <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>, |
| <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 3>, |
| <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>, |
| <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>; |
| status = "okay"; |
| }; |
| pcie0: pcie@0xd4288000{ |
| reset-gpios = <&gpio 42 0 >; |
| status = "okay"; |
| }; |
| pciephy0: pcie-phy@d4210000 { |
| status = "okay"; |
| }; |
| camera: camera@d420c000 { |
| compatible = "asr,camera"; |
| reg = <0xd420c000 0x1000>, /* IPE registers */ |
| <0xd420e000 0x1000>; /* ISP registers */ |
| reg-names = "ipe", "isp"; |
| interrupts = <58>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&isp_spi_data>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| clock-frequency = <24>; |
| clocks = <&soc_clocks ASR1803_CLK_CAMERA>; |
| clock-names = "cam_clk"; |
| status = "okay"; |
| port { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| spi_in_cam: endpoint@0 { |
| reg = <0>; |
| remote-endpoint = <&gc0312_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| apb@d4000000 { |
| ssp_dai1: pxa-ssp-dai@1 { |
| compatible = "asr,pxa-ssp-dai"; |
| reg = <0x1 0x0>; |
| |
| port = <&ssp1>; |
| pinctrl-names = "default","ssp"; |
| pinctrl-0 = <&i2s_gpio>; |
| pinctrl-1 = <&i2s_func>; |
| ssp-gpio = <&gpio 25 0 &gpio 26 0 &gpio 27 0 &gpio 28 0>; |
| |
| dmas = <&pdma0 54 1 |
| &pdma0 55 1>; |
| dma-names = "rx", "tx"; |
| |
| platform_driver_name = "pdma_platform"; |
| burst_size = <4>; |
| playback_period_bytes = <2048>; |
| playback_buffer_bytes = <4096>; |
| capture_period_bytes = <2048>; |
| capture_buffer_bytes = <4096>; |
| }; |
| mfpr: mfpr@d401e000 { |
| status = "okay"; |
| /* intend to replace lpm-board-cfg |
| no-apbsd-in-d1pp = <0x1>; //"wakeup-state-d1pp" |
| pin1:pin1@d401e01B0 { |
| offset = <0x1B0>; |
| udr-cfg = <0xA040>; |
| }; |
| pin2:pin2@d401e01B4 { |
| offset = <0x1B4>; |
| udr-cfg = <0xA040>; |
| }; |
| */ |
| }; |
| timer0: timer@d4014000 { |
| status = "okay"; |
| }; |
| /* ap uart1, gps uart */ |
| uart1: uart@d4017000 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart1_pmx_func>; |
| status = "disabled"; |
| }; |
| /* ap uart2, gps uart */ |
| uart2: uart@d4018000 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pmx_func>; |
| status = "okay"; |
| }; |
| /* ap uart3 */ |
| uart3: uart@d401f000 { /* nezhas evb use ap uart */ |
| pinctrl-names = "default","sleep"; |
| pinctrl-0 = <&uart3_pmx_func1 &uart3_pmx_func2>; |
| pinctrl-1 = <&uart3_pmx_func1_sleep &uart3_pmx_func2>; |
| edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */ |
| status = "okay"; |
| }; |
| /* ap uart4 */ |
| uart4: uart@d401f800 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart4_pmx_rxd &uart4_pmx_txd>; |
| status = "disabled"; |
| }; |
| rtc: rtc@d4010000 { |
| status = "okay"; |
| }; |
| pmx: pinmux@d401e000 { |
| /* pin base = base_addr / 4, nr pins & gpio function */ |
| pinctrl-single,gpio-range = < |
| /* |
| * GPIO number is hardcoded for range at here. |
| * In gpio chip, GPIO number is not hardcoded for range. |
| * Since one gpio pin may be routed to multiple pins, |
| * define these gpio range in pxa910-dkb.dts not pxa910.dtsi. |
| */ |
| /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */ |
| &range 55 32 0 /* GPIO0 ~ GPIO31 */ |
| &range 87 32 0 /* GPIO32 ~ GPIO63 */ |
| &range 119 32 0 /* GPIO64 ~ GPIO95 */ |
| &range 151 32 0 /* GPIO96 ~ GPIO127 */ |
| >; |
| |
| #ifdef CONFIG_FB_ASR |
| lcd_pmx_func: lcd_pmx_func { |
| pinctrl-single,pins = < |
| #ifdef CONFIG_FB_ASR_SPI |
| GPIO00 AF3 /* SPI_DCLK */ |
| GPIO01 AF3 /* SPI_DCX */ |
| GPIO16 AF3 /* SPI_DOUT_1 */ |
| GPIO02 AF3 /* SPI_CS0 */ |
| GPIO03 AF3 /* SPI_DIN */ |
| GPIO06 AF3 /* SPI_DOUT */ |
| GPIO81 AF1 /* SPI_VSYNC */ |
| GPIO82 AF1 /* SPI_RSTB */ |
| #elif defined(CONFIG_FB_ASR_MCU) |
| GPIO00 AF5 /* MCU_D0 */ |
| GPIO01 AF5 /* MCU_D5 */ |
| GPIO02 AF5 /* MCU_CS0 */ |
| GPIO03 AF5 /* MCU_RDB */ |
| GPIO06 AF5 /* MCU_WRB */ |
| GPIO81 AF1 /* MCU_VSYNC */ |
| GPIO82 AF1 /* MCU_RSTB */ |
| GPIO16 AF5 /* MCU_D6 */ |
| GPIO17 AF5 /* MCU_A0 */ |
| GPIO18 AF5 /* MCU_D7 */ |
| GPIO33 AF3 /* MCU_D3 */ |
| GPIO34 AF3 /* MCU_D4 */ |
| GPIO35 AF3 /* MCU_D1 */ |
| GPIO36 AF3 /* MCU_D2 */ |
| #elif defined(CONFIG_FB_ASR_MIPI) |
| GPIO81 AF1 /* MIPI_VSYNC */ |
| GPIO82 AF1 /* MIPI_RSTB */ |
| #endif |
| >; |
| /* NOTE: need to PULL_UP here */ |
| DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE; |
| }; |
| #endif |
| |
| ssp0_pmx_func: ssp0_pmx_func { |
| pinctrl-single,pins = < |
| GPIO36 AF1 /* TXD */ |
| GPIO35 AF1 /* RXD */ |
| GPIO34 AF1 /* FRM */ |
| /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */ |
| GPIO33 AF1 /* SCLK */ |
| >; |
| DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| }; |
| lcd_bl_func: lcd_bl_func { |
| pinctrl-single,pins = < |
| VCXO_OUT AF1 /* GPIO126, lcd bl */ |
| GPIO82 AF0 /* reset */ |
| >; |
| MFP_DEFAULT; |
| }; |
| twsi0_pmx_func: twsi0_pmx_func { |
| pinctrl-single,pins = < |
| GPIO49 AF1 |
| GPIO50 AF1 |
| >; |
| MFP_LPM_FLOAT; |
| }; |
| twsi0_pmx_gpio: twsi0_pmx_gpio { |
| pinctrl-single,pins = < |
| GPIO49 AF0 |
| GPIO50 AF0 |
| >; |
| MFP_LPM_FLOAT; |
| }; |
| twsi1_pmx_func: twsi1_pmx_func { |
| pinctrl-single,pins = < |
| GPIO10 AF1 |
| GPIO11 AF1 |
| >; |
| MFP_LPM_FLOAT; |
| }; |
| twsi1_pmx_gpio: twsi1_pmx_gpio { |
| pinctrl-single,pins = < |
| GPIO10 AF0 |
| GPIO11 AF0 |
| >; |
| MFP_LPM_FLOAT; |
| }; |
| /* no pull, no LPM */ |
| dvc_pmx_func: dvc_pmx_func { |
| /* hw-dvc */ |
| pinctrl-single,pins = < |
| TDS_DIO0 AF0 |
| TDS_DIO1 AF0 |
| >; |
| DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| }; |
| leds_pmx_func: leds_pmx_func { |
| pinctrl-single,pins = < |
| DF_IO10 AF1 |
| DF_IO11 AF1 |
| DF_IO12 AF1 |
| >; |
| DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| }; |
| |
| gps_pmx_onoff: gps_pmx_onoff { |
| pinctrl-single,pins = < |
| TDS_TXREV AF1 |
| >; |
| DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| }; |
| gps_pmx_reset: gps_pmx_reset { |
| pinctrl-single,pins = < |
| TDS_RXON AF1 |
| >; |
| DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| }; |
| gnss_clk_on: gnss_clk_on { |
| pinctrl-single,pins = < |
| GPIO43 AF2 /*GPIO[43] */ |
| GPIO62 AF2 /*GPIO62->GPS_BLANK*/ |
| VBUS_DRV AF1 /* GPIO[122] */ |
| PRI_TDO AF1 |
| >; |
| DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW; |
| }; |
| uart1_pmx_func: uart1_pmx_func { |
| pinctrl-single,pins = < |
| GPIO37 AF1 |
| GPIO38 AF1 |
| >; |
| MFP_DEFAULT; |
| }; |
| uart2_pmx_func: uart2_pmx_func { |
| pinctrl-single,pins = < |
| GPIO44 AF1 |
| GPIO45 AF1 |
| >; |
| MFP_DEFAULT; |
| }; |
| uart3_pmx_func1: uart3_pmx_func1 { |
| pinctrl-single,pins = < |
| GPIO29 AF1 |
| >; |
| MFP_DEFAULT; |
| }; |
| uart3_pmx_func2: uart3_pmx_func2 { |
| pinctrl-single,pins = < |
| GPIO30 AF1 |
| >; |
| MFP_DEFAULT; |
| }; |
| uart3_pmx_func1_sleep: uart3_pmx_func1_sleep { |
| pinctrl-single,pins = < |
| GPIO29 AF1 |
| >; |
| DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL; |
| }; |
| uart4_pmx_rxd: uart4_pmx_rxd { |
| /* gps dedicated uart */ |
| pinctrl-single,pins = < |
| GPIO51 AF1 |
| GPIO32 AF1 |
| >; |
| MFP_DEFAULT; |
| }; |
| uart4_pmx_txd: uart4_pmx_txd { |
| /* gps dedicated uart */ |
| pinctrl-single,pins = < |
| GPIO52 AF1 |
| GPIO31 AF1 |
| >; |
| MFP_DEFAULT; |
| }; |
| panel_rst_func: panel_rst_func { |
| pinctrl-single,pins = < |
| DF_nCS1 AF1 |
| >; |
| DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| }; |
| |
| sd_ldo_en: sd_ldo_en { |
| pinctrl-single,pins = < |
| GPIO19 AF0 |
| >; |
| MFP_PULL_DOWN; |
| }; |
| sdh0_pmx_func1: sdh0_pmx_func1 { |
| pinctrl-single,pins = < |
| MMC1_DAT3 AF0 |
| MMC1_DAT2 AF0 |
| MMC1_DAT1 AF0 |
| MMC1_DAT0 AF0 |
| MMC1_CMD AF0 |
| >; |
| DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| }; |
| sdh0_pmx_func2: sdh0_pmx_func2 { |
| pinctrl-single,pins = < |
| MMC1_CLK AF0 |
| >; |
| DS_MEDIUM;PULL_NONE;EDGE_NONE; |
| }; |
| sdh0_pmx_func3: sdh0_pmx_func3 { |
| pinctrl-single,pins = < |
| MMC1_CD AF0 |
| >; |
| MFP_PULL_UP; |
| }; |
| sdh0_pmx_func1_slow: sdh0_pmx_func1_slow { |
| pinctrl-single,pins = < |
| MMC1_DAT3 AF0 |
| MMC1_DAT2 AF0 |
| MMC1_DAT1 AF0 |
| MMC1_DAT0 AF0 |
| MMC1_CMD AF0 |
| >; |
| DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| }; |
| sdh0_pmx_func2_slow: sdh0_pmx_func2_slow { |
| pinctrl-single,pins = < |
| MMC1_CLK AF0 |
| >; |
| DS_FAST0;PULL_NONE;EDGE_NONE; |
| }; |
| sdh0_pmx_func1_fast: sdh0_pmx_func1_fast { |
| pinctrl-single,pins = < |
| MMC1_DAT3 AF0 |
| MMC1_DAT2 AF0 |
| MMC1_DAT1 AF0 |
| MMC1_DAT0 AF0 |
| MMC1_CMD AF0 |
| >; |
| DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| }; |
| sdh0_pmx_func2_fast: sdh0_pmx_func2_fast { |
| pinctrl-single,pins = < |
| MMC1_CLK AF0 |
| >; |
| DS_FAST1;PULL_NONE;EDGE_NONE; |
| }; |
| sdh1_pmx_func1_fast: sdh1_pmx_func1_fast { |
| pinctrl-single,pins = < |
| TDS_DIO13 AF0 /* WLAN_DAT3 */ |
| TDS_DIO14 AF0 /* WLAN_DAT2 */ |
| TDS_DIO15 AF0 /* WLAN_DAT1 */ |
| TDS_DIO16 AF0 /* WLAN_DAT0 */ |
| TDS_DIO17 AF0 /* WLAN_CMD */ |
| >; |
| DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| }; |
| sdh1_pmx_func2_fast: sdh1_pmx_func2_fast { |
| pinctrl-single,pins = < |
| TDS_DIO18 AF0 /* WLAN_CLK */ |
| >; |
| DS_FAST1;PULL_DOWN;EDGE_NONE; |
| }; |
| sdh1_pmx_func1: sdh1_pmx_func1 { |
| pinctrl-single,pins = < |
| TDS_DIO13 AF0 /* WLAN_DAT3 */ |
| TDS_DIO14 AF0 /* WLAN_DAT2 */ |
| TDS_DIO15 AF0 /* WLAN_DAT1 */ |
| TDS_DIO16 AF0 /* WLAN_DAT0 */ |
| TDS_DIO17 AF0 /* WLAN_CMD */ |
| >; |
| DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| }; |
| sdh1_pmx_func2: sdh1_pmx_func2 { |
| pinctrl-single,pins = < |
| TDS_DIO18 AF0 /* WLAN_CLK */ |
| >; |
| DS_MEDIUM;PULL_DOWN;EDGE_NONE; |
| }; |
| sdh1_pmx_func3: sdh1_pmx_func3 { |
| pinctrl-single,pins = < |
| GPIO37 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */ |
| >; |
| MFP_PULL_DOWN; |
| }; |
| sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup { |
| pinctrl-single,pins = < |
| GPIO37 AF0 /* VCXO_REQ AF1 */ |
| >; |
| DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL; |
| }; |
| sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off { |
| pinctrl-single,pins = < |
| GPIO83 AF0 /* WLAN_PDn */ |
| GPIO38 AF0 /* HOST_WAKEUP_WLAN */ |
| GPIO14 AF0 /* HOST RESET WLAN */ |
| >; |
| MFP_PULL_DOWN; |
| }; |
| sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on { |
| pinctrl-single,pins = < |
| GPIO83 AF0 /* WLAN_PDn */ |
| GPIO38 AF0 /* HOST_WAKEUP_WLAN */ |
| GPIO14 AF0 /* HOST RESET WLAN */ |
| >; |
| MFP_PULL_UP; |
| }; |
| eta6005_charger_en: eta6005_charger_en { |
| pinctrl-single,pins = < |
| GPIO08 AF0 |
| >; |
| MFP_PULL_UP; |
| }; |
| eta6005_charger_stat: eta6005_charger_stat { |
| pinctrl-single,pins = < |
| PRI_TMS AF1 |
| >; |
| MFP_DEFAULT; |
| }; |
| |
| alc5616_pmx_func1: alc5616_pmx_func1 { |
| pinctrl-single,pins = < |
| GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */ |
| >; |
| MFP_DEFAULT; |
| }; |
| alc5616_pmx_func2: alc5616_pmx_func2 { |
| pinctrl-single,pins = < |
| GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */ |
| >; |
| MFP_DEFAULT; |
| }; |
| |
| audio_pa_pmx_func: audio_pa_pmx_func { |
| pinctrl-single,pins = < |
| GPIO39 AF0 /* PA */ |
| >; |
| MFP_DEFAULT; |
| }; |
| ecall_pmx_func: ecall_pmx_func { |
| pinctrl-single,pins = < |
| GPIO08 AF0 /* auto mode ecall */ |
| GPIO09 AF0 /* manual mode ecall */ |
| >; |
| MFP_DEFAULT; |
| }; |
| slic_pmx_func1: slic_pmx_func1 { |
| pinctrl-single,pins = < |
| GPIO24 AF0 /* SLIC_INT, GPIO24 */ |
| VCXO_OUT AF1 /* GPIO127, SLIC_3V3LDO_EN/LCD_BK_EN */ |
| >; |
| MFP_DEFAULT; |
| }; |
| slic_pmx_func2: slic_pmx_func2 { |
| pinctrl-single,pins = < |
| GPIO23 AF0 /* SLIC_RESET, GPIO23 */ |
| >; |
| MFP_DEFAULT; |
| }; |
| slic_pmx_func1_sleep: slic_pmx_func1_sleep { |
| pinctrl-single,pins = < |
| GPIO24 AF0 /* SLIC_INT, GPIO24 */ |
| >; |
| DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| }; |
| |
| otg_vbus_func: otg_vbus_func { |
| pinctrl-single,pins = < |
| VBUS_DRV AF1 /* GPIO[122] */ |
| >; |
| DS_MEDIUM;PULL_DOWN;EDGE_NONE; |
| }; |
| |
| emac_pmx_func0: emac_pmx_func0 { |
| pinctrl-single,pins = < |
| GPIO00 AF1 /* GMAC1_RX_DV */ |
| GPIO01 AF1 /* GMAC1_RX_D0 */ |
| GPIO02 AF1 /* GMAC1_RX_D1 */ |
| GPIO03 AF1 /* GMAC1_RX_CLK */ |
| /* GPIO04 AF1 GMAC1_RX_D2 */ |
| /* GPIO05 AF1 GMAC1_RX_D3 */ |
| GPIO06 AF1 /* GMAC1_TX_D0 */ |
| GPIO07 AF1 /* GMAC1_TX_D1 */ |
| /* GPIO12 AF1 GMAC1_TX_CLK */ |
| /* GPIO13 AF1 GMAC1_TX_D2 */ |
| /* GPIO14 AF1 GMAC1_TX_D3 */ |
| GPIO15 AF1 /* GMAC1_TX_EN */ |
| GPIO16 AF1 /* GMAC1_TX_MDC */ |
| /* GPIO17 AF1 GMAC1_TX_MDIO */ |
| >; |
| DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| }; |
| emac_pmx_func1: emac_pmx_func1 { |
| pinctrl-single,pins = < |
| GPIO04 AF1 /* GMAC1_RX_D2 */ |
| GPIO05 AF1 /* GMAC1_RX_D3 */ |
| GPIO12 AF1 /* GMAC1_TX_CLK */ |
| GPIO13 AF1 /* GMAC1_TX_D2 */ |
| GPIO14 AF1 /* GMAC1_TX_D3 */ |
| >; |
| DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| }; |
| emac_pmx_func2: emac_pmx_func2 { |
| pinctrl-single,pins = < |
| GPIO17 AF1 /* GMAC1_TX_MDIO */ |
| GPIO18 AF1 /* GMAC1_TX_INT_N */ |
| >; |
| DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| }; |
| emac_pmx_func3: emac_pmx_func3 { |
| pinctrl-single,pins = < |
| GPIO20 AF0 /* RESET */ |
| /* GPIO54 AF0 LDO_EN */ |
| >; |
| DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| }; |
| usim1_pmx_func: usim1_pmx_func { |
| pinctrl-single,pins = < |
| GPIO54 AF0 |
| >; |
| DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| }; |
| usim1_pmx_func_sleep: usim1_pmx_func_sleep { |
| pinctrl-single,pins = < |
| GPIO54 AF0 |
| >; |
| DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| }; |
| usim2_pmx_func: usim2_pmx_func { |
| pinctrl-single,pins = < |
| GPIO53 AF0 |
| >; |
| DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| }; |
| usim2_pmx_func_sleep: usim2_pmx_func_sleep { |
| pinctrl-single,pins = < |
| GPIO53 AF0 |
| >; |
| DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| }; |
| pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off { |
| pinctrl-single,pins = < |
| GPIO42 AF0 /* PERST_N */ |
| GPIO48 AF0 /* DC_EN */ |
| >; |
| MFP_PULL_DOWN; |
| }; |
| pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on { |
| pinctrl-single,pins = < |
| GPIO42 AF0 /* PERST_N */ |
| GPIO48 AF0 /* DC_EN */ |
| >; |
| MFP_PULL_UP; |
| }; |
| gc032a_pmx_func: gc032a_pmx_func { |
| pinctrl-single,pins = < |
| GPIO21 AF2 /* mclk */ |
| GPIO40 AF0 /* CAM_LDO_EN */ |
| GPIO48 AF0 /* CAM_PWDN */ |
| >; |
| DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| }; |
| isp_spi_data: isp_spi_data { |
| pinctrl-single,pins = < |
| /* spi_data0 ... spi_data1 */ |
| GPIO24 AF2 |
| GPIO23 AF2 |
| /* camera spi clk */ |
| GPIO22 AF2 |
| >; |
| DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| }; |
| gpiokey_pmx_func: gpiokey_pmx_func { |
| pinctrl-single,pins = < |
| GPIO09 AF0 |
| >; |
| DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| }; |
| usb_id_pinmux: usb_id_pinmux { |
| pinctrl-single,pins = < |
| USB_ID AF1 /* usbid-gpio99 */ |
| >; |
| DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE; |
| }; |
| usb_id_pinmux_slp: usb_id_pinmux_slp { |
| pinctrl-single,pins = < |
| USB_ID AF1 /* usbid-gpio99 */ |
| >; |
| DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE; |
| }; |
| usb_host_pinmux: usb_host_pinmux { |
| pinctrl-single,pins = < |
| VBUS_DRV AF1 /* gpio-122 */ |
| >; |
| DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE; |
| }; |
| i2s_func: i2s_func { |
| pinctrl-single,pins = < |
| GPIO25 AF1 |
| GPIO26 AF1 |
| GPIO27 AF1 |
| GPIO28 AF1 |
| >; |
| MFP_DEFAULT; |
| }; |
| i2s_gpio: i2s_gpio { |
| pinctrl-single,pins = < |
| GPIO25 AF0 |
| GPIO26 AF0 |
| GPIO27 AF0 |
| GPIO28 AF0 |
| >; |
| MFP_LPM_FLOAT; |
| }; |
| }; |
| |
| ssp0: spi@d401b000 { |
| #ifdef CONFIG_FB_ASR_MCU |
| status = "disabled"; |
| #else |
| status = "okay"; |
| #endif |
| pinctrl-names = "default"; |
| pinctrl-0 = <&ssp0_pmx_func>; |
| asr,spi-inc-mode; |
| #ifdef CONFIG_FB_SPI_LCD |
| /* this enhancemnet feature is not suitable for |
| 3 line 9bits spi lcd. */ |
| /* asr,ssp-enhancement; */ |
| |
| lcd: spidev@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "spilcd"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&lcd_bl_func>; |
| reg = <0>; |
| /* ST7735: need to set spi-max-frequency to 26M |
| * ST7789V: can set spi-max-frequency to 52M |
| */ |
| spi-max-frequency = <26000000>; |
| xres = <128>; |
| yres = <128>; |
| bits = <8>; /* 8: 4line, 9: 3line */ |
| rst_gpio = <&gpio 24 0>; |
| bl_gpio = <&gpio 126 0>; |
| rs_gpio = <&gpio 22 0>; |
| /* if comment the following statement, it means |
| * the avdd is sit on the "always-on" ldo. |
| */ |
| /* avdd-supply = <&LDO1>; */ |
| }; |
| #else |
| /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */ |
| slic: spidev@0{ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "asr,slic"; |
| reg = <0>; |
| spi-cpol; |
| spi-cpha; |
| spi-max-frequency = <6500000>; |
| }; |
| #endif |
| }; |
| twsi0: i2c@d4011000 { |
| status= "okay"; |
| alc5616@1b { |
| compatible = "asrmicro,alc5616"; |
| reg = <0x1b>; |
| asr,mclk-from-bclk; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&alc5616_pmx_func1>; |
| pinctrl-1 = <&alc5616_pmx_func2>; |
| #if 0 |
| 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */ |
| irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */ |
| #else |
| irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */ |
| #endif |
| }; |
| |
| /* |
| pmic4: 88pm805@38 { |
| compatible = "marvell,88pm805"; |
| reg = <0x38>; |
| }; |
| */ |
| }; |
| twsi1: i2c@d4010800 { |
| pinctrl-names = "default","gpio"; |
| pinctrl-0 = <&twsi1_pmx_func>; |
| pinctrl-1 = <&twsi1_pmx_gpio>; |
| i2c-gpio = <&gpio 10 0 &gpio 11 0>; |
| status= "okay"; |
| |
| gc032a: gc032a@21{ |
| compatible = "galaxycore,gc032a"; |
| reg = <0x21>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&gc032a_pmx_func>; |
| pwdn-gpios = <&gpio 48 0>; |
| power-gpios = <&gpio 40 0>; |
| |
| status = "okay"; |
| port { |
| gc0312_out: endpoint { |
| remote-endpoint = <&spi_in_cam>; |
| }; |
| }; |
| }; |
| }; |
| twsi2: i2c@d4037000 { |
| status = "okay"; |
| |
| pmic4: 88pm805@38 { |
| compatible = "marvell,88pm805"; |
| reg = <0x38>; |
| }; |
| |
| pmic5: pm802@0 { |
| compatible = "asr,pm802"; |
| reg = <0x00>; |
| interrupts = <4>; |
| interrupt-parent = <&intc>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| chg_irq_from_exton; |
| /* set scs-int-active-high depending on board connection */ |
| scs-int-active-high; |
| battery { |
| compatible = "asr,pm802-bat"; |
| status = "disabled"; |
| |
| online-gpadc = <1>; |
| temperature-gpadc = <1>; |
| |
| hi-volt-online = <1150>; /* mV */ |
| lo-volt-online = <20>; /* mV */ |
| hi-volt-temp = <1150>; /* mV */ |
| lo-volt-temp = <200>; /* mV */ |
| |
| sw-fg-use-ntc; |
| full-capacity = <2050>; /* mAh */ |
| r1-resistor = <40>; /* mohm */ |
| r2-resistor = <30>; /* mohm */ |
| rs-resistor = <120>; /* mohm */ |
| roff-resistor = <0>; /* mohm */ |
| roff-initial-resistor = <0>; /* mohm */ |
| |
| times-in-zero-degree = <1>; |
| offset-in-zero-degree = <0>; |
| |
| times-in-ten-degree = <2>; |
| offset-in-ten-degree = <100>; |
| |
| power-off-threshold = <3350>; /* mV */ |
| safe-power-off-threshold = <3200>; /* mV */ |
| |
| online-gp-bias-curr = <11>; /* uA */ |
| |
| soc-ramp-up-interval = <150>; /* s */ |
| /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */ |
| tbat-threshold = <20 0 10 40 45 55>; /* ohm */ |
| ntc-table-size = <88>; |
| stop-chg-for-vbatmeas; |
| /* -24C, -23C, ..., 62C, 63C */ |
| ntc-table = < |
| 89680 85130 80840 76790 72970 69360 65960 62740 |
| 59700 56830 54130 51530 49100 46800 44610 42550 |
| 40590 38730 36970 35300 33710 32210 30780 29420 |
| 28130 26910 25750 24640 23590 22580 21630 20720 |
| 19860 19030 18250 17500 16790 16110 15460 14840 |
| 14250 13690 13150 12640 12150 11680 11230 10800 |
| 10390 10000 9620 9270 8920 8590 8280 7980 |
| 7690 7410 7150 6890 6650 6410 6190 5970 |
| 5770 5570 5380 5190 5020 4850 4680 4530 |
| 4380 4230 4100 3960 3830 3710 3590 3480 |
| 3370 3260 3160 3060 2960 2870 2780 2700 |
| >; |
| }; |
| usb { |
| status = "disabled"; |
| vbus_gpio = <0xff>; /* set_vbus */ |
| id-gpadc = <0xff>; /* usb-id */ |
| vchg-from-exton = <1>; |
| vbus-detect = <1>; /* vbus-irq */ |
| get-vbus = <1>; /* get-vbus */ |
| }; |
| }; |
| pmic6: pm803@30 { |
| compatible = "asr,pm803"; |
| reg = <0x30>; |
| interrupts = <4>; |
| interrupt-parent = <&intc>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| chg_irq_from_exton; |
| /* set scs-int-active-high depending on board connection */ |
| scs-int-active-high; |
| battery { |
| compatible = "asr,pm803-bat"; |
| status = "disabled"; |
| |
| online-gpadc = <1>; |
| temperature-gpadc = <1>; |
| |
| hi-volt-online = <1150>; /* mV */ |
| lo-volt-online = <20>; /* mV */ |
| hi-volt-temp = <1150>; /* mV */ |
| lo-volt-temp = <200>; /* mV */ |
| |
| sw-fg-use-ntc; |
| full-capacity = <2050>; /* mAh */ |
| r1-resistor = <40>; /* mohm */ |
| r2-resistor = <30>; /* mohm */ |
| rs-resistor = <120>; /* mohm */ |
| roff-resistor = <0>; /* mohm */ |
| roff-initial-resistor = <0>; /* mohm */ |
| |
| times-in-zero-degree = <1>; |
| offset-in-zero-degree = <0>; |
| |
| times-in-ten-degree = <2>; |
| offset-in-ten-degree = <100>; |
| |
| power-off-threshold = <3350>; /* mV */ |
| safe-power-off-threshold = <3200>; /* mV */ |
| |
| online-gp-bias-curr = <11>; /* uA */ |
| |
| soc-ramp-up-interval = <150>; /* s */ |
| /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */ |
| tbat-threshold = <20 0 10 40 45 55>; /* ohm */ |
| ntc-table-size = <88>; |
| stop-chg-for-vbatmeas; |
| /* -24C, -23C, ..., 62C, 63C */ |
| ntc-table = < |
| 89680 85130 80840 76790 72970 69360 65960 62740 |
| 59700 56830 54130 51530 49100 46800 44610 42550 |
| 40590 38730 36970 35300 33710 32210 30780 29420 |
| 28130 26910 25750 24640 23590 22580 21630 20720 |
| 19860 19030 18250 17500 16790 16110 15460 14840 |
| 14250 13690 13150 12640 12150 11680 11230 10800 |
| 10390 10000 9620 9270 8920 8590 8280 7980 |
| 7690 7410 7150 6890 6650 6410 6190 5970 |
| 5770 5570 5380 5190 5020 4850 4680 4530 |
| 4380 4230 4100 3960 3830 3710 3590 3480 |
| 3370 3260 3160 3060 2960 2870 2780 2700 |
| >; |
| }; |
| usb { |
| status = "disabled"; |
| vbus_gpio = <0xff>; /* set_vbus */ |
| id-gpadc = <0xff>; /* usb-id */ |
| vchg-from-exton = <1>; |
| vbus-detect = <1>; /* vbus-irq */ |
| get-vbus = <1>; /* get-vbus */ |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| vcc_sdh1: sd-regulator { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&sd_ldo_en>; |
| regulator-name = "SDH1 VCC"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio 19 0>; |
| enable-active-high; |
| }; |
| |
| asr-rfkill { |
| compatible = "asr,asr-rfkill"; |
| pinctrl-names = "off", "on"; |
| pinctrl-0 = <&sdh1_pmx_pd_rst_off>; |
| pinctrl-1 = <&sdh1_pmx_pd_rst_on>; |
| sd-host = <&sdh1>; |
| pd-gpio = <&gpio 83 0>; |
| #if 0 /* for rtk wifi */ |
| 3v3-ldo-gpio = <&gpio 38 0>; |
| #else /* for asr5811 and AIC wifi */ |
| host-wakeup-wlan-gpio = <&gpio 38 0>; |
| rst-gpio = <&gpio 55 0>; |
| #endif |
| wlan-wakeup-host-gpio = <&gpio 37 0>; |
| edge-wakeup-gpio = <&gpio 37 0>; |
| status = "okay"; |
| }; |
| |
| pcie-rfkill { |
| compatible = "mrvl,pcie-rfkill"; |
| pinctrl-names = "off", "on"; |
| pinctrl-0 = <&pcie_pmx_pd_rst_off>; |
| pinctrl-1 = <&pcie_pmx_pd_rst_on>; |
| rst-gpio = <&gpio 42 0>; |
| 3v3-ldo-gpio = <&gpio 48 0>; |
| #ifdef CONFIG_ASR_CAMERA |
| status = "disabled"; |
| #else |
| status = "okay"; |
| #endif |
| }; |
| |
| charger { |
| status= "disabled"; |
| compatible = "asr,eta6005-chg"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&eta6005_charger_en &eta6005_charger_stat>; |
| chg-en-gpio = <8>; |
| chg-stat-gpio = <118>; |
| }; |
| |
| asr-gps { |
| compatible = "asr,asr-gnss"; |
| clocks = <&soc_clocks ASR1803_CLK_VCTCXO_REQ>; |
| clock-names = "gnss_26m"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&gnss_clk_on>; |
| host-wakeup-gnss-gpio = <&gpio 120 0>; |
| gnss-wakeup-host-gpio = <&gpio 117 0>; |
| rst-gpio = <&gpio 122 0>; |
| status = "okay"; |
| }; |
| sound { |
| compatible = "ASRMICRO,asrmicro-snd-card"; |
| ssp-controllers = <&ssp_dai1>; |
| }; |
| |
| ecall { |
| compatible = "asr,ecall-event"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&ecall_pmx_func>; |
| gpio-auto-ecall = <8>; |
| gpio-manual-ecall = <9>; |
| status = "disabled"; |
| }; |
| |
| usim1: usim1 { |
| compatible = "asr,usim1"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&usim1_pmx_func>; |
| pinctrl-1 = <&usim1_pmx_func_sleep>; |
| edge_detect_gpio = <54>; /* GPIO54: SIM detect pin */ |
| status = "okay"; |
| }; |
| /* set okay for this node if usim2 is needed */ |
| usim2: usim2 { |
| compatible = "asr,usim2"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&usim2_pmx_func>; |
| pinctrl-1 = <&usim2_pmx_func_sleep>; |
| edge_detect_gpio = <53>; /* GPIO53: SIM detect pin */ |
| #ifdef CONFIG_ASR_DSDS |
| status = "okay"; |
| #else |
| status = "disabled"; |
| #endif |
| }; |
| gpio_keys { |
| compatible = "gpio-keys"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| /* autorepeat; */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&gpiokey_pmx_func>; |
| button@1 { |
| label = "qrcode-key"; |
| linux,code = <139>; /* KEY_MENU, refer to linux/input.h */ |
| /* NOTE: |
| * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB. |
| * Customer SHOULD change it to any other gpios. |
| * Because user may do the misoperation that |
| * powerup with FDL key pressed, |
| * then the borad will enter force download mode. |
| */ |
| gpios = <&gpio 9 1>; |
| gpio-key,wakeup; |
| }; |
| }; |
| |
| audio_pa { |
| compatible = "asrmicro,audio-pa"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&audio_pa_pmx_func>; |
| pa-gpio = <&gpio 39 0>; |
| status = "okay"; |
| }; |
| |
| audio_regs { |
| compatible = "ASRMICRO,audio-registers"; |
| reg = <0xD4050044 0x4>; |
| status = "okay"; |
| }; |
| |
| nz3-slic { |
| compatible = "asr,nz3-slic"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>; |
| pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>; |
| rst-gpio = <&gpio 23 0>; |
| edge-wakeup-gpio = <&gpio 24 0>; |
| vdd-3v3-gpio = <&gpio 127 0>; |
| status = "disabled"; |
| }; |
| microsemi-slic { |
| compatible = "asr,microsemi-slic"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&slic_pmx_func1>; |
| pinctrl-1 = <&slic_pmx_func1_sleep>; |
| edge-wakeup-gpio = <&gpio 24 0>; |
| vdd-3v3-gpio = <&gpio 127 0>; |
| status = "disabled"; |
| }; |
| maxlinear-slic { |
| compatible = "asr,maxlinear-slic"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>; |
| pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>; |
| rst-gpio = <&gpio 23 0>; |
| edge-wakeup-gpio = <&gpio 24 0>; |
| vdd-3v3-gpio = <&gpio 127 0>; |
| status = "disabled"; |
| }; |
| /* deprecated, move to mfpr@d401e000 |
| lpm-board-cfg { |
| compatible = "asr,lpm-board-cfg"; |
| wakeup-state-d1pp = <0x1>; |
| udr-mfpr-config = <0x1B0 0xA040 0x0 |
| 0x1B4 0xA040 0x0>; |
| }; |
| */ |
| }; |
| #ifdef CONFIG_ASR_DSDS |
| #include "asr_pm802_2usim.dtsi" |
| #include "88pm805.dtsi" |
| #include "asr_pm803_2usim.dtsi" |
| #else |
| #include "asr_pm802.dtsi" |
| #include "88pm805.dtsi" |
| #include "asr_pm803.dtsi" |
| #endif |
| |
| #ifdef CONFIG_AB_SYSTEM |
| #include "asr1903_ab_flash_layout.dtsi" |
| #else |
| #include "asr1903_flash_layout.dtsi" |
| #endif |