marvell/linux/drivers/crypto/asr/te200/asr-te200.c

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/hw_random.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/of_device.h>
#include <linux/delay.h>
#include <linux/crypto.h>
#include <linux/cputype.h>
#include <crypto/scatterwalk.h>
#include <crypto/algapi.h>
#include <crypto/aes.h>

#include "asr-te200.h"
#include "../asr_aes_clk.h"

static inline u32 asr_te200_read(struct asr_te200_dev *dd, u32 offset)
{
	u32 value = readl_relaxed(dd->io_base + offset);
	return value;
}

static inline void asr_te200_write(struct asr_te200_dev *dd,
					u32 offset, u32 value)
{
	writel_relaxed(value, dd->io_base + offset);
}

static int asr_te200_clk_sync(struct asr_te200_dev *dd)
{
	struct clk *te200_clk;

	if (dd->clk_synced)
		return 0;

	te200_clk = dd->te200_clk;
	/* TE200 clk will be disable by CP core, but the enable count is still 1.
	* Need to sync the clk enable state here and re-enable the clk.
	*/
	if (__clk_is_enabled(te200_clk) == false &&
		__clk_get_enable_count(te200_clk))
	{
		asr_aes_clk_put(te200_clk);
		asr_aes_clk_get(te200_clk);
		dd->clk_synced = 1;
		dev_dbg(dd->dev, "sync te200 clk done\n");
		return 1;
	}

	return 0;
}

static int asr_te200_dev_get(struct asr_te200_dev *dd)
{
	mutex_lock(&dd->te200_lock);

	asr_te200_clk_sync(dd);
	asr_aes_clk_get(dd->te200_clk);

	return 0;
}

static int asr_te200_dev_put(struct asr_te200_dev *dd)
{
	asr_aes_clk_put(dd->te200_clk);

	mutex_unlock(&dd->te200_lock);
	return 0;
}

static void asr_te200_hw_init(struct asr_te200_dev *dd)
{
	asr_te200_write(dd, TE200_CLOCK_CTRL, 0);
	asr_te200_write(dd, TE200_RESET_CTRL, 0);
}

#if defined(CONFIG_OF)
static const struct of_device_id asr_te200_dt_ids[] = {
	{ .compatible = "asr,asr-te200" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, asr_te200_dt_ids);
#endif

static struct asr_te200_ops te200_ops = {
	.dev_get = asr_te200_dev_get,
	.dev_put = asr_te200_dev_put,
};

static int asr_te200_probe(struct platform_device *pdev)
{
	struct asr_te200_dev *te200_dd;
	struct device *dev = &pdev->dev;
	struct resource *te200_res;
	struct device_node *np = NULL;
	int err = 0, devnum = 0;

	te200_dd = devm_kzalloc(&pdev->dev, sizeof(*te200_dd), GFP_KERNEL);
	if (te200_dd == NULL) {
		err = -ENOMEM;
		goto res_err;
	}

	np = dev->of_node;
	te200_dd->dev = dev;
	te200_dd->te200_ops = &te200_ops;

	platform_set_drvdata(pdev, te200_dd);

	mutex_init(&te200_dd->te200_lock);

	/* Get the base address */
	te200_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!te200_res) {
		dev_err(dev, "no MEM resource info\n");
		err = -ENODEV;
		goto res_err;
	}
	te200_dd->phys_base = te200_res->start;

	/* Initializing the clock */
	te200_dd->te200_clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(te200_dd->te200_clk)) {
		dev_err(dev, "clock initialization failed.\n");
		err = PTR_ERR(te200_dd->te200_clk);
		goto res_err;
	}
	te200_dd->clk_synced = 0;

	te200_dd->io_base = devm_ioremap_resource(&pdev->dev, te200_res);
	if (IS_ERR(te200_dd->io_base)) {
		dev_err(dev, "can't ioremap\n");
		err = PTR_ERR(te200_dd->io_base);
		goto res_err;
	}

	err = clk_prepare(te200_dd->te200_clk);
	if (err)
		goto res_err;

	err = asr_aes_clk_get(te200_dd->te200_clk);
	if (err)
		goto te200_clk_unprepare;

	asr_te200_hw_init(te200_dd);

#ifdef CONFIG_ASR_TE200_CIPHER
	if (of_get_property(np, "asr,asr-cipher", NULL)) {
		err = asr_te200_cipher_register(te200_dd);
		if (err)
			goto te200_asr_aes_clk_put;
		dev_info(dev, "CIPHER engine is initialized\n");
		devnum ++;
	}
#endif

#ifdef CONFIG_ASR_TE200_SHA
	if (of_get_property(np, "asr,asr-sha", NULL)) {
		err = asr_te200_sha_register(te200_dd);
		if (err)
			goto sha_err;
		dev_info(dev, "SHA engine is initialized\n");
		devnum ++;
	}
#endif

#ifdef CONFIG_ASR_TE200_RSA
	if (of_get_property(np, "asr,asr-rsa", NULL)) {
		err = asr_te200_rsa_register(te200_dd);
		if (err)
			goto rsa_err;
		dev_info(dev, "RSA engine is initialized\n");
		devnum ++;
	}
#endif

	if (!devnum) {
		dev_err(dev, "No TE200 device enabled\n");
		err = -ENODEV;
		goto te200_asr_aes_clk_put;
	}

	return 0;

#ifdef CONFIG_ASR_TE200_RSA
rsa_err:
#ifdef CONFIG_ASR_TE200_SHA
	asr_te200_sha_unregister(te200_dd);
#endif
#endif
#ifdef CONFIG_ASR_TE200_SHA
sha_err:
#ifdef CONFIG_ASR_TE200_CIPHER
	asr_te200_cipher_unregister(te200_dd);
#endif
#endif
te200_asr_aes_clk_put:
	asr_aes_clk_put(te200_dd->te200_clk);
te200_clk_unprepare:
	clk_unprepare(te200_dd->te200_clk);
res_err:
	devm_kfree(dev, te200_dd);
	dev_err(dev, "initialization failed.\n");

	return err;
}

static int asr_te200_remove(struct platform_device *pdev)
{
	struct asr_te200_dev *te200_dd;

	te200_dd = platform_get_drvdata(pdev);
	if (!te200_dd)
		return -ENODEV;

	clk_unprepare(te200_dd->te200_clk);
	asr_aes_clk_put(te200_dd->te200_clk);

#ifdef CONFIG_ASR_TE200_CIPHER
	asr_te200_cipher_unregister(te200_dd);
#endif

#ifdef CONFIG_ASR_TE200_SHA
	asr_te200_sha_unregister(te200_dd);
#endif

#ifdef CONFIG_ASR_TE200_RSA
	asr_te200_rsa_unregister(te200_dd);
#endif

	devm_kfree(te200_dd->dev, te200_dd);

	return 0;
}

#ifdef CONFIG_PM
static int asr_te200_suspend(struct device *dev)
{
	struct asr_te200_dev *te200_dd = dev_get_drvdata(dev);

	asr_aes_clk_put(te200_dd->te200_clk);

	return 0;
}

static int asr_te200_resume(struct device *dev)
{
	struct asr_te200_dev *te200_dd = dev_get_drvdata(dev);

	return asr_aes_clk_get(te200_dd->te200_clk);
}

static const struct dev_pm_ops asr_te200_pm_ops = {
	.suspend	= asr_te200_suspend,
	.resume		= asr_te200_resume,
};
#endif /* CONFIG_PM */

static struct platform_driver asr_te200_driver = {
	.probe		= asr_te200_probe,
	.remove		= asr_te200_remove,
	.driver		= {
		.name	= "asr_te200",
#ifdef CONFIG_PM
		.pm	= &asr_te200_pm_ops,
#endif
		.of_match_table = of_match_ptr(asr_te200_dt_ids),
	},
};

static int __init asr_te200_init(void)
{
	int ret;

	if (!cpu_is_asr1903_b0()) {
		return 0;
	}

	ret = platform_driver_register(&asr_te200_driver);

	return ret;
}

device_initcall_sync(asr_te200_init);

MODULE_DESCRIPTION("ASR Trust Engine support.");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Yonggan Wang");