| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2021 ASR Micro Limited |
| * |
| * Authors: |
| * Fei Lv <feilv@asrmicro.com> |
| */ |
| |
| #include <linux/device.h> |
| #include <linux/kernel.h> |
| #include <linux/mtd/spinand.h> |
| |
| #define SPINAND_MFR_XTX 0xA1 |
| #define SPINAND_MFR_XTX2 0x0B |
| #define SPINAND_MFR_XTX3 0x2C |
| |
| #define XT26Q01D_STATUS_ECC_MASK (0xF << 4) |
| #define XT26Q01D_STATUS_ECC_NO_BITFLIPS (0 << 4) |
| #define XT26Q01D_STATUS_ECC_1_4_BITFLIPS (1 << 4) |
| #define XT26Q01D_STATUS_ECC_5_BITFLIPS (5 << 4) |
| #define XT26Q01D_STATUS_ECC_6_BITFLIPS (9 << 4) |
| #define XT26Q01D_STATUS_ECC_7_BITFLIPS (0xD << 4) |
| #define XT26Q01D_STATUS_ECC_8_BITFLIPS (3 << 4) |
| |
| #define XT26Q01E_STATUS_ECC_MASK GENMASK(6, 4) |
| #define XT26Q01E_STATUS_ECC_NO_BITFLIPS (0 << 4) |
| #define XT26Q01E_STATUS_ECC_1_3_BITFLIPS (1 << 4) |
| #define XT26Q01E_STATUS_ECC_UNCOR_ERROR (2 << 4) |
| #define XT26Q01E_STATUS_ECC_4_6_BITFLIPS (3 << 4) |
| #define XT26Q01E_STATUS_ECC_7_8_BITFLIPS (5 << 4) |
| |
| static SPINAND_OP_VARIANTS(read_cache_variants, |
| SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| |
| static SPINAND_OP_VARIANTS(read_cache_variants2, |
| SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| |
| static SPINAND_OP_VARIANTS(write_cache_variants, |
| SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), |
| SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
| |
| static SPINAND_OP_VARIANTS(update_cache_variants, |
| SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), |
| SPINAND_PROG_LOAD(false, 0, NULL, 0)); |
| |
| static int pn26q01a_ooblayout_ecc(struct mtd_info *mtd, int section, |
| struct mtd_oob_region *region) |
| { |
| if (section > 3) |
| return -ERANGE; |
| |
| region->offset = (9 * section) + 6; |
| region->length = 13; |
| |
| return 0; |
| } |
| |
| static int pn26q01a_ooblayout_free(struct mtd_info *mtd, int section, |
| struct mtd_oob_region *region) |
| { |
| if (section > 3) |
| return -ERANGE; |
| |
| region->offset = (16 * section) + 64; |
| region->length = 16; |
| |
| return 0; |
| } |
| |
| static const struct mtd_ooblayout_ops pn26q01a_ooblayout = { |
| .ecc = pn26q01a_ooblayout_ecc, |
| .free = pn26q01a_ooblayout_free, |
| }; |
| |
| static int pn26q01a_get_ecc_status(struct spinand_device *spinand, u8 status) |
| { |
| switch (status & STATUS_ECC_MASK) { |
| case STATUS_ECC_NO_BITFLIPS: |
| return 0; |
| |
| case STATUS_ECC_HAS_BITFLIPS: |
| return 7; |
| |
| case STATUS_ECC_UNCOR_ERROR: |
| return -EBADMSG; |
| |
| default: |
| return 8; |
| } |
| |
| return -EINVAL; |
| } |
| |
| static int xt26q01d_ooblayout_ecc(struct mtd_info *mtd, int section, |
| struct mtd_oob_region *region) |
| { |
| return -ERANGE; |
| } |
| |
| static int xt26q01d_ooblayout_free(struct mtd_info *mtd, int section, |
| struct mtd_oob_region *region) |
| { |
| if (section > 3) |
| return -ERANGE; |
| |
| if (section == 0) { |
| region->offset = 2; |
| region->length = 14; |
| } else { |
| region->offset = 16 * section; |
| region->length = 16; |
| } |
| |
| return 0; |
| } |
| |
| static const struct mtd_ooblayout_ops xt26q01d_ooblayout = { |
| .ecc = xt26q01d_ooblayout_ecc, |
| .free = xt26q01d_ooblayout_free, |
| }; |
| |
| static int xt26q01d_get_ecc_status(struct spinand_device *spinand, u8 status) |
| { |
| switch (status & STATUS_ECC_MASK) { |
| case STATUS_ECC_NO_BITFLIPS: |
| return 0; |
| |
| case STATUS_ECC_HAS_BITFLIPS: |
| switch (status & XT26Q01D_STATUS_ECC_MASK) { |
| case XT26Q01D_STATUS_ECC_1_4_BITFLIPS: |
| return 4; |
| case XT26Q01D_STATUS_ECC_5_BITFLIPS: |
| return 5; |
| case XT26Q01D_STATUS_ECC_6_BITFLIPS: |
| return 6; |
| case XT26Q01D_STATUS_ECC_7_BITFLIPS: |
| return 7; |
| } |
| break; |
| |
| case STATUS_ECC_UNCOR_ERROR: |
| return -EBADMSG; |
| |
| default: |
| return 8; |
| } |
| |
| return -EINVAL; |
| } |
| |
| static int xt26q01e_ecc_get_status(struct spinand_device *spinand, u8 status) |
| { |
| switch (status & XT26Q01E_STATUS_ECC_MASK) { |
| case XT26Q01E_STATUS_ECC_NO_BITFLIPS: |
| return 0; |
| |
| case XT26Q01E_STATUS_ECC_1_3_BITFLIPS: |
| return 3; |
| |
| case XT26Q01E_STATUS_ECC_4_6_BITFLIPS: |
| return 6; |
| |
| case XT26Q01E_STATUS_ECC_7_8_BITFLIPS: |
| return 8; |
| |
| case XT26Q01E_STATUS_ECC_UNCOR_ERROR: |
| return -EBADMSG; |
| |
| default: |
| break; |
| } |
| |
| return -EINVAL; |
| } |
| |
| static const struct spinand_info xtx_spinand_table[] = { |
| SPINAND_INFO("PN26Q01AWSIUG", 0xC1, |
| NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT | SPINAND_RDM_CMD_LOAD_PAGE | \ |
| SPINAND_ECC_EN_IN_FEATURE, |
| SPINAND_ECCINFO(&pn26q01a_ooblayout, |
| pn26q01a_get_ecc_status)), |
| SPINAND_INFO("XT26Q01D-BE", 0x51, |
| NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&xt26q01d_ooblayout, |
| xt26q01d_get_ecc_status)), |
| SPINAND_INFO("XT26Q02D", 0x52, |
| NAND_MEMORG(1, 2048, 64, 64, 2048, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&xt26q01d_ooblayout, |
| xt26q01d_get_ecc_status)), |
| SPINAND_INFO("XT26Q02E", 0x25, |
| NAND_MEMORG(1, 2048, 64, 64, 2048, 20, 2, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS_TIMING( |
| &read_cache_variants2, |
| &write_cache_variants, |
| &update_cache_variants, |
| 8, 2, 2, 52000000), |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&xt26q01d_ooblayout, |
| xt26q01e_ecc_get_status)), |
| }; |
| |
| /** |
| * xtx_spinand_detect - initialize device related part in spinand_device |
| * struct if it is a Winbond device. |
| * @spinand: SPI NAND device structure |
| */ |
| static int xtx_spinand_detect(struct spinand_device *spinand) |
| { |
| u8 *id = spinand->id.data; |
| int ret; |
| |
| if (id[1] != SPINAND_MFR_XTX && id[1] != SPINAND_MFR_XTX2 && |
| id[1] != SPINAND_MFR_XTX3) |
| return 0; |
| |
| ret = spinand_match_and_init(spinand, xtx_spinand_table, |
| ARRAY_SIZE(xtx_spinand_table), id[2]); |
| if (ret) |
| return ret; |
| |
| return 1; |
| } |
| |
| static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { |
| .detect = xtx_spinand_detect, |
| }; |
| |
| const struct spinand_manufacturer xtx_spinand_manufacturer = { |
| .id = SPINAND_MFR_XTX, |
| .name = "XTX", |
| .ops = &xtx_spinand_manuf_ops, |
| }; |
| |
| const struct spinand_manufacturer xtx2_spinand_manufacturer = { |
| .id = SPINAND_MFR_XTX2, |
| .name = "XTX2", |
| .ops = &xtx_spinand_manuf_ops, |
| }; |
| |
| const struct spinand_manufacturer xtx3_spinand_manufacturer = { |
| .id = SPINAND_MFR_XTX3, |
| .name = "XTX3", |
| .ops = &xtx_spinand_manuf_ops, |
| }; |