| #ifndef _DT_BINDINGS_MMC_PXA_SDHCI_H |
| #define _DT_BINDINGS_MMC_PXA_SDHCI_H |
| |
| /* |
| * PXA platform special preset/src clock rate |
| * use to preset the MMC defined clock rate |
| */ |
| #define PXA_SDH_DTR_25M 25000000 |
| #define PXA_SDH_DTR_26M 26000000 |
| #define PXA_SDH_DTR_45M 45000000 |
| #define PXA_SDH_DTR_48M 48000000 |
| #define PXA_SDH_DTR_52M 52000000 |
| #define PXA_SDH_DTR_78M 78000000 |
| #define PXA_SDH_DTR_83M 83200000 |
| #define PXA_SDH_DTR_89M 89142857 |
| #define PXA_SDH_DTR_104M 104000000 |
| #define PXA_SDH_DTR_156M 156000000 |
| #define PXA_SDH_DTR_178M 178000000 |
| #define PXA_SDH_DTR_208M 208000000 |
| #define PXA_SDH_DTR_312M 312000000 |
| #define PXA_SDH_DTR_416M 416000000 |
| #define PXA_SDH_DTR_624M 624000000 |
| #define PXA_SDH_DTR_PS_NONE 0xffffffff |
| |
| #define PXA_MMC_TIMING_LEGACY 0 |
| #define PXA_MMC_TIMING_MMC_HS 1 |
| #define PXA_MMC_TIMING_SD_HS 2 |
| #define PXA_MMC_TIMING_UHS_SDR12 3 |
| #define PXA_MMC_TIMING_UHS_SDR25 4 |
| #define PXA_MMC_TIMING_UHS_SDR50 5 |
| #define PXA_MMC_TIMING_UHS_SDR104 6 |
| #define PXA_MMC_TIMING_UHS_DDR50 7 |
| #define PXA_MMC_TIMING_MMC_DDR52 8 |
| #define PXA_MMC_TIMING_MMC_HS200 9 |
| #define PXA_MMC_TIMING_MAX 10 |
| |
| /* stand for invalid number for dvfs level, tuning value, etc. */ |
| #define PXA_SDH_INVALID 0xffffffff |
| |
| /* pxa specific flag */ |
| /* Enable bus clock hardware auto-gating */ |
| #define PXA_FLAG_ENABLE_CLOCK_GATING (1<<0) |
| /* card always wired to host, like on-chip emmc */ |
| #define PXA_FLAG_CARD_PERMANENT (1<<1) |
| /* Board design supports 8-bit data on SD/SDIO BUS */ |
| #define PXA_FLAG_SD_8_BIT_CAPABLE_SLOT (1<<2) |
| /* SDIO device/SD Card detect wakeup host sleep feature */ |
| #define PXA_FLAG_WAKEUP_HOST (1<<3) |
| /* disable card scanning in probe procedure */ |
| #define PXA_FLAG_DISABLE_PROBE_CDSCAN (1<<4) |
| /* whether supports RPM in driver, it can used for source clock gating */ |
| #define PXA_FLAG_EN_PM_RUNTIME (1<<5) |
| /* whether Rx configure Reg is changed, like pxa988, 1088 */ |
| #define PXA_FLAG_NEW_RX_CFG_REG (1<<6) |
| /* whether Tx configure support bus clock as internal clock */ |
| #define PXA_FLAG_TX_SEL_BUS_CLK (1<<7) |
| /* Disable bus clock hardware auto-gating */ |
| #define PXA_FLAG_DISABLE_CLOCK_AUTO_GATING (1<<8) |
| |
| #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ |
| #define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ |
| #define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ |
| #define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ |
| #define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ |
| #define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ |
| #define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ |
| #define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */ |
| #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ |
| #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ |
| #define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ |
| #define MMC_CAP_3_3V_DDR (1 << 11) /* Host supports eMMC DDR 3.3V */ |
| #define MMC_CAP_1_8V_DDR (1 << 12) /* Host supports eMMC DDR 1.8V */ |
| #define MMC_CAP_1_2V_DDR (1 << 13) /* Host supports eMMC DDR 1.2V */ |
| #define MMC_CAP_POWER_OFF_CARD (1 << 14) /* Can power off after boot */ |
| #define MMC_CAP_BUS_WIDTH_TEST (1 << 15) /* CMD14/CMD19 bus width ok */ |
| #define MMC_CAP_CD_WAKE (1 << 28) /* Enable card detect wake */ |
| |
| #define MMC_CAP2_NO_CMD_BEFORE_CMD5 (1 << 1) /* No any other cmd can be sent before cmd5 */ |
| #define MMC_CAP2_SDIO_CLK_52M_ONLY_DNLD_FW (1 << 3) /* Only support SDIO clock 52MHz when downloading firmware */ |
| #define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ |
| #define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ |
| #define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \ |
| MMC_CAP2_HS200_1_2V_SDR) |
| #define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */ |
| #define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */ |
| #define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \ |
| MMC_CAP2_HS400_1_2V) |
| #define MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V) |
| #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) |
| #define MMC_CAP2_ONLY_1_8V (1 << 28) /* Some SDIO cards only work in 1.8V */ |
| #define MMC_CAP2_DISABLE_PROBE_CDSCAN (1 << 29) |
| #define MMC_CAP2_BUS_AUTO_CLK_GATE (1 << 30) /* host can auto gate bus clk */ |
| #define MMC_CAP2_CLK_SCALE (1 << 31) /* Allow dynamic clk scaling */ |
| #define MMC_CAP2_BUS_CLK_NO_SCALE (1 << 13) /* Not allow dynamic bus clk scaling */ |
| |
| #define MMC_CAP_UHS_SDR12 (1 << 16) /* Host supports UHS SDR12 mode */ |
| #define MMC_CAP_UHS_SDR25 (1 << 17) /* Host supports UHS SDR25 mode */ |
| #define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */ |
| #define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */ |
| #define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */ |
| |
| /* common flag */ |
| /* Controller has an unusable DMA engine */ |
| #define SDHCI_QUIRK_BROKEN_DMA (1<<5) |
| /* Controller has an unusable ADMA engine */ |
| #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) |
| #define SDHCI_QUIRK2_BUS_CLK_GATE_ENABLED (1<<6) |
| #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) |
| #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) |
| |
| #define MMC_CAP2_IGNORE_18V_CHECK (1 << 21) |
| #define MMC_CAP2_SKIP_CMD11 (1 << 22) |
| |
| #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) |
| |
| #define SDHCI_QUIRK2_NO_1_8_V (1<<2) |
| #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) |
| /* Controller's SDHC_TX_CFG_REG register must always select clock from inverter of internal work clock. */ |
| #define SDHCI_QUIRK2_TX_INT_CLOCK (1<<19) |
| /* some SD host need to set IO capability by SOC part register */ |
| #define SDHCI_QUIRK2_SET_AIB_MMC (1<<20) |
| /* After SD host request, prevent system to suspend state for a while */ |
| #define SDHCI_QUIRK2_HOLDSUSPEND_AFTER_REQUEST (1<<21) |
| /* Some Pxa SDH, fake interrupt would happens during CMD53 in UHS mode */ |
| #define SDHCI_QUIRK2_FAKE_SDIO_IRQ_IN_UHS (1<<9) |
| /* HS200/SDR104 SW tuning can't use ADMA */ |
| #define SDHCI_QUIRK2_TUNING_ADMA_BROKEN (1<<10) |
| /* Controller supported max data timeout is too short (~10s for 52Mhz bus clock) */ |
| #define SDHCI_QUIRK2_TIMEOUT_SHORT (1<<22) |
| /* Card detect will be triggered manually */ |
| #define SDHCI_QUIRK2_MANUAL_CARD_DETECT (1<<23) |
| /* HS200/SDR104 tuning broken and must use predefined fixed delay */ |
| #define SDHCI_QUIRK2_TUNING_BROKEN (1<<24) |
| /* Disable Timer re-tuning */ |
| #define SDHCI_QUIRK2_NO_TIMER_RETUNING (1<<25) |
| /* Some platform may use ASYNC_INT for clock gating */ |
| #define SDHCI_QUIRK2_CLK_GATE_USE_ASYNC_INT (1<<26) |
| /* Base clock must always on during working. Some sdio/sd card host detect need this. */ |
| #define SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON (1<<27) |
| /* CRC status of device need to delay 3 cycle */ |
| #define SDHCI_QUIRK2_LONG_DATA_CRC_STATUS (1<<30) |
| /* Support change SDIO clock frequency dynamically. */ |
| #define SDHCI_QUIRK2_CHANGE_SDIO_CLOCK_FREQ_DYNAMIC (1<<31) |
| |
| #define MMC_PM_KEEP_POWER (1 << 0) |
| #define MMC_CAP2_NO_VOLTAGE_SWITCH (1 << 18) |
| |
| /* Tuning mode define */ |
| #define PXA_SDH_TUNING_DEFAULT 0 |
| #define PXA_SDH_TUNING_DVFS 1 |
| |
| #endif |