| #ifndef __ASM_MACH_IRQS_H |
| #define __ASM_MACH_IRQS_H |
| |
| /* |
| * Interrupt numbers for PXA1928 |
| */ |
| |
| #if defined(CONFIG_GIC_BYPASS) /* Use ICU for Interrupt Handling */ |
| #if defined(CONFIG_SMP) /* Use GIC+ICU */ |
| #define IRQ_PXA1928_START 32 |
| #else /* ICU Only */ |
| #define IRQ_PXA1928_START 0 |
| #endif |
| #else /* GIC Only Mode */ |
| #define IRQ_PXA1928_START 32 |
| #endif |
| |
| #define IRQ_PXA1928_NONE (-1) |
| #define IRQ_PXA1928_SSP1 (IRQ_PXA1928_START + 0) |
| #define IRQ_PXA1928_SSP2 (IRQ_PXA1928_START + 1) |
| #define IRQ_PXA1928_SSPA1 (IRQ_PXA1928_START + 2) |
| #define IRQ_PXA1928_SSPA2 (IRQ_PXA1928_START + 3) |
| /* PMIC & USB Charger Intr. Mux */ |
| #define IRQ_PXA1928_INT4 (IRQ_PXA1928_START + 4) |
| /* RTC Intr. Mux */ |
| #define IRQ_PXA1928_INT5 (IRQ_PXA1928_START + 5) |
| #define IRQ_PXA1928_TWSI1 (IRQ_PXA1928_START + 7) |
| /* GPU Intr. Mux */ |
| #define IRQ_PXA1928_INT8 (IRQ_PXA1928_START + 8) |
| #define IRQ_PXA1928_KEYPAD (IRQ_PXA1928_START + 9) |
| #define IRQ_PXA1928_ROTARY (IRQ_PXA1928_START + 10) |
| #define IRQ_PXA1928_TRACKBALL (IRQ_PXA1928_START + 11) |
| #define IRQ_PXA1928_ONEWIRE (IRQ_PXA1928_START + 12) |
| #define IRQ_PXA1928_TIMER1 (IRQ_PXA1928_START + 13) |
| #define IRQ_PXA1928_TIMER2 (IRQ_PXA1928_START + 14) |
| #define IRQ_PXA1928_TIMER3 (IRQ_PXA1928_START + 15) |
| #define IRQ_PXA1928_IPC1 (IRQ_PXA1928_START + 16) |
| /* TWSI2 ~ TWSI6 Intr. Mux */ |
| #define IRQ_PXA1928_INT17 (IRQ_PXA1928_START + 17) |
| /* Multicore cpu1 (IRQ & FIQ) Intr. */ |
| #define IRQ_PXA1928_INT18 (IRQ_PXA1928_START + 18) |
| #define IRQ_PXA1928_HDMI (IRQ_PXA1928_START + 19) |
| #define IRQ_PXA1928_SSP3 (IRQ_PXA1928_START + 20) |
| #define IRQ_PXA1928_USB_HS (IRQ_PXA1928_START + 22) |
| #define IRQ_PXA1928_UART3 (IRQ_PXA1928_START + 24) |
| #define IRQ_PXA1928_VPU (IRQ_PXA1928_START + 26) |
| #define IRQ_PXA1928_UART1 (IRQ_PXA1928_START + 27) |
| #define IRQ_PXA1928_UART2 (IRQ_PXA1928_START + 28) |
| #define IRQ_PXA1928_MIPI_DSI (IRQ_PXA1928_START + 29) |
| /* ISP & Multicore cpu0 (IRQ & FIQ) Intr. Mux */ |
| #define IRQ_PXA1928_INT30 (IRQ_PXA1928_START + 30) |
| #define IRQ_PXA1928_PMU_TIMER1 (IRQ_PXA1928_START + 31) |
| #define IRQ_PXA1928_PMU_TIMER2 (IRQ_PXA1928_START + 32) |
| #define IRQ_PXA1928_PMU_TIMER3 (IRQ_PXA1928_START + 33) |
| /* Miscellaneous Intr. Mux */ |
| #define IRQ_PXA1928_INT35 (IRQ_PXA1928_START + 35) |
| #define IRQ_PXA1928_WDT1 (IRQ_PXA1928_START + 36) |
| #define IRQ_PXA1928_NAND_DMA (IRQ_PXA1928_START + 37) |
| #define IRQ_PXA1928_USIM (IRQ_PXA1928_START + 38) |
| #define IRQ_PXA1928_MMC (IRQ_PXA1928_START + 39) |
| #define IRQ_PXA1928_WTM (IRQ_PXA1928_START + 40) |
| #define IRQ_PXA1928_LCD (IRQ_PXA1928_START + 41) |
| /* CCIC Intr. Mux */ |
| #define IRQ_PXA1928_INT42 (IRQ_PXA1928_START + 42) |
| #define IRQ_PXA1928_PAD_EDGE (IRQ_PXA1928_START + 43) |
| #define IRQ_PXA1928_USB_OTG (IRQ_PXA1928_START + 44) |
| #define IRQ_PXA1928_NAND (IRQ_PXA1928_START + 45) |
| #define IRQ_PXA1928_UART4 (IRQ_PXA1928_START + 46) |
| #define IRQ_PXA1928_DMA_FIQ (IRQ_PXA1928_START + 47) |
| #define IRQ_PXA1928_DMA_IRQ (IRQ_PXA1928_START + 48) |
| #define IRQ_PXA1928_GPIO (IRQ_PXA1928_START + 49) |
| #define IRQ_PXA1928_SECURITY (IRQ_PXA1928_START + 50) |
| /* SSP Intr. Mux */ |
| #define IRQ_PXA1928_INT51 (IRQ_PXA1928_START + 51) |
| #define IRQ_PXA1928_MMC2 (IRQ_PXA1928_START + 52) |
| #define IRQ_PXA1928_MMC3 (IRQ_PXA1928_START + 53) |
| #define IRQ_PXA1928_MMC4 (IRQ_PXA1928_START + 54) |
| #define IRQ_PXA1928_IPC2 (IRQ_PXA1928_START + 56) |
| /* DSP & Thermal Intr. Mux */ |
| #define IRQ_PXA1928_INT57 (IRQ_PXA1928_START + 57) |
| #define IRQ_PXA1928_IPC_CP (IRQ_PXA1928_START + 59) |
| #define IRQ_PXA1928_CA7_FREQ_CHG (IRQ_PXA1928_START + 60) |
| #define IRQ_PXA1928_SMC (IRQ_PXA1928_START + 63) |
| |
| #if defined(CONFIG_GIC_BYPASS) |
| |
| #define IRQ_PXA1928_MUX_START (IRQ_PXA1928_START + 64) |
| |
| /* secondary interrupt of INT #4 */ |
| #define IRQ_PXA1928_INT4_BASE (IRQ_PXA1928_MUX_START) |
| #define IRQ_PXA1928_CHARGER (IRQ_PXA1928_INT4_BASE + 0) |
| #define IRQ_PXA1928_PMIC (IRQ_PXA1928_INT4_BASE + 1) |
| #define IRQ_PXA1928_CHRG_DTC_OUT (IRQ_PXA1928_INT4_BASE + 3) |
| |
| /* secondary interrupt of INT #5 */ |
| #define IRQ_PXA1928_INT5_BASE (IRQ_PXA1928_INT4_BASE + 4) |
| #define IRQ_PXA1928_RTC_ALARM (IRQ_PXA1928_INT5_BASE + 0) |
| #define IRQ_PXA1928_RTC (IRQ_PXA1928_INT5_BASE + 1) |
| |
| /* secondary interrupt of INT #8 */ |
| #define IRQ_PXA1928_INT8_BASE (IRQ_PXA1928_INT5_BASE + 2) |
| #define IRQ_PXA1928_GC2200 (IRQ_PXA1928_INT8_BASE + 0) |
| #define IRQ_PXA1928_GC320 (IRQ_PXA1928_INT8_BASE + 2) |
| #define IRQ_PXA1928_MULTICORE_INT_CPU3 (IRQ_PXA1928_INT8_BASE + 3) |
| |
| /* secondary interrupt of INT #17 */ |
| #define IRQ_PXA1928_INT17_BASE (IRQ_PXA1928_INT8_BASE + 4) |
| #define IRQ_PXA1928_TWSI2 (IRQ_PXA1928_INT17_BASE + 0) |
| #define IRQ_PXA1928_TWSI3 (IRQ_PXA1928_INT17_BASE + 1) |
| #define IRQ_PXA1928_TWSI4 (IRQ_PXA1928_INT17_BASE + 2) |
| #define IRQ_PXA1928_TWSI5 (IRQ_PXA1928_INT17_BASE + 3) |
| #define IRQ_PXA1928_TWSI6 (IRQ_PXA1928_INT17_BASE + 4) |
| #define IRQ_PXA1928_MULTICORE_INT_CPU2 (IRQ_PXA1928_INT17_BASE + 5) |
| |
| /* secondary interrupt of INT #18 */ |
| #define IRQ_PXA1928_INT18_BASE (IRQ_PXA1928_INT17_BASE + 6) |
| #define IRQ_PXA1928_MULTICORE_INT_CPU1 (IRQ_PXA1928_INT18_BASE + 2) |
| |
| /* secondary interrupt of INT #30 */ |
| #define IRQ_PXA1928_INT30_BASE (IRQ_PXA1928_INT18_BASE + 3) |
| #define IRQ_PXA1928_ISP_DMA (IRQ_PXA1928_INT30_BASE + 0) |
| #define IRQ_PXA1928_DXO_ISP (IRQ_PXA1928_INT30_BASE + 1) |
| #define IRQ_PXA1928_MULTICORE_INT_CPU0 (IRQ_PXA1928_INT30_BASE + 2) |
| |
| /* secondary interrupt of INT #35 */ |
| #define IRQ_PXA1928_INT35_BASE (IRQ_PXA1928_INT30_BASE + 3) |
| #define IRQ_PXA1928_CA7_MP_TRIGGER0 (IRQ_PXA1928_INT35_BASE + 0) |
| #define IRQ_PXA1928_CA7_MP_TRIGGER1 (IRQ_PXA1928_INT35_BASE + 1) |
| #define IRQ_PXA1928_CA7_MP_TRIGGER2 (IRQ_PXA1928_INT35_BASE + 2) |
| #define IRQ_PXA1928_CA7_MP_TRIGGER3 (IRQ_PXA1928_INT35_BASE + 3) |
| #define IRQ_PXA1928_CA7_MP_COMMTX0 (IRQ_PXA1928_INT35_BASE + 4) |
| #define IRQ_PXA1928_CA7_MP_COMMTX1 (IRQ_PXA1928_INT35_BASE + 5) |
| #define IRQ_PXA1928_CA7_MP_COMMTX2 (IRQ_PXA1928_INT35_BASE + 6) |
| #define IRQ_PXA1928_CA7_MP_COMMTX3 (IRQ_PXA1928_INT35_BASE + 7) |
| #define IRQ_PXA1928_CA7_MP_COMMRX0 (IRQ_PXA1928_INT35_BASE + 8) |
| #define IRQ_PXA1928_CA7_MP_COMMRX1 (IRQ_PXA1928_INT35_BASE + 9) |
| #define IRQ_PXA1928_CA7_MP_COMMRX2 (IRQ_PXA1928_INT35_BASE + 10) |
| #define IRQ_PXA1928_CA7_MP_COMMRX3 (IRQ_PXA1928_INT35_BASE + 11) |
| #define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ0 (IRQ_PXA1928_INT35_BASE + 12) |
| #define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ1 (IRQ_PXA1928_INT35_BASE + 13) |
| #define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ2 (IRQ_PXA1928_INT35_BASE + 14) |
| #define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ3 (IRQ_PXA1928_INT35_BASE + 15) |
| #define IRQ_PXA1928_MULTICORE_NPMUIRQ0 (IRQ_PXA1928_INT35_BASE + 16) |
| #define IRQ_PXA1928_MULTICORE_NPMUIRQ1 (IRQ_PXA1928_INT35_BASE + 17) |
| #define IRQ_PXA1928_MULTICORE_NPMUIRQ2 (IRQ_PXA1928_INT35_BASE + 18) |
| #define IRQ_PXA1928_MULTICORE_NPMUIRQ3 (IRQ_PXA1928_INT35_BASE + 19) |
| #define IRQ_PXA1928_CORE_MP_NAXIERRIRQ (IRQ_PXA1928_INT35_BASE + 20) |
| #define IRQ_PXA1928_WDT2_INT (IRQ_PXA1928_INT35_BASE + 21) |
| #define IRQ_PXA1928_MULTICORE_NCNTPNSIRQ0 (IRQ_PXA1928_INT35_BASE + 23) |
| #define IRQ_PXA1928_MULTICORE_NCNTPNSIRQ1 (IRQ_PXA1928_INT35_BASE + 24) |
| #define IRQ_PXA1928_MULTICORE_NCNTPNSIRQ2 (IRQ_PXA1928_INT35_BASE + 25) |
| #define IRQ_PXA1928_MULTICORE_NCNTPNSIRQ3 (IRQ_PXA1928_INT35_BASE + 26) |
| #define IRQ_PXA1928_MULTICORE_NCNTPSIRQ0 (IRQ_PXA1928_INT35_BASE + 27) |
| #define IRQ_PXA1928_MULTICORE_NCNTPSIRQ1 (IRQ_PXA1928_INT35_BASE + 28) |
| #define IRQ_PXA1928_MULTICORE_NCNTPSIRQ2 (IRQ_PXA1928_INT35_BASE + 29) |
| #define IRQ_PXA1928_MULTICORE_NCNTPSIRQ3 (IRQ_PXA1928_INT35_BASE + 30) |
| #define IRQ_PXA1928_MCK_PML_OVERFLOW (IRQ_PXA1928_INT35_BASE + 31) |
| |
| /* secondary interrupt of INT #42 */ |
| #define IRQ_PXA1928_INT42_BASE (IRQ_PXA1928_INT35_BASE + 32) |
| #define IRQ_PXA1928_CCIC2 (IRQ_PXA1928_INT42_BASE + 0) |
| #define IRQ_PXA1928_CCIC1 (IRQ_PXA1928_INT42_BASE + 1) |
| |
| /* secondary interrupt of INT #48 (DMA_IRQ) */ |
| #define IRQ_PXA1928_INT48_BASE (IRQ_PXA1928_INT42_BASE + 2) |
| #define IRQ_PXA1928_DMA_CHNL_INT0 (IRQ_PXA1928_INT48_BASE + 0) |
| #define IRQ_PXA1928_DMA_CHNL_INT1 (IRQ_PXA1928_INT48_BASE + 1) |
| #define IRQ_PXA1928_DMA_CHNL_INT2 (IRQ_PXA1928_INT48_BASE + 2) |
| #define IRQ_PXA1928_DMA_CHNL_INT3 (IRQ_PXA1928_INT48_BASE + 3) |
| #define IRQ_PXA1928_DMA_CHNL_INT4 (IRQ_PXA1928_INT48_BASE + 4) |
| #define IRQ_PXA1928_DMA_CHNL_INT5 (IRQ_PXA1928_INT48_BASE + 5) |
| #define IRQ_PXA1928_DMA_CHNL_INT6 (IRQ_PXA1928_INT48_BASE + 6) |
| #define IRQ_PXA1928_DMA_CHNL_INT7 (IRQ_PXA1928_INT48_BASE + 7) |
| #define IRQ_PXA1928_DMA_CHNL_INT8 (IRQ_PXA1928_INT48_BASE + 8) |
| #define IRQ_PXA1928_DMA_CHNL_INT9 (IRQ_PXA1928_INT48_BASE + 9) |
| #define IRQ_PXA1928_DMA_CHNL_INT10 (IRQ_PXA1928_INT48_BASE + 10) |
| #define IRQ_PXA1928_DMA_CHNL_INT11 (IRQ_PXA1928_INT48_BASE + 11) |
| #define IRQ_PXA1928_DMA_CHNL_INT12 (IRQ_PXA1928_INT48_BASE + 12) |
| #define IRQ_PXA1928_DMA_CHNL_INT13 (IRQ_PXA1928_INT48_BASE + 13) |
| #define IRQ_PXA1928_DMA_CHNL_INT14 (IRQ_PXA1928_INT48_BASE + 14) |
| #define IRQ_PXA1928_DMA_CHNL_INT15 (IRQ_PXA1928_INT48_BASE + 15) |
| #define IRQ_PXA1928_MDMA_CHNL_INT0 (IRQ_PXA1928_INT48_BASE + 16) |
| #define IRQ_PXA1928_MDMA_CHNL_INT1 (IRQ_PXA1928_INT48_BASE + 17) |
| #define IRQ_PXA1928_ADMA_CHNL_INT0 (IRQ_PXA1928_INT48_BASE + 18) |
| #define IRQ_PXA1928_ADMA_CHNL_INT1 (IRQ_PXA1928_INT48_BASE + 19) |
| #define IRQ_PXA1928_ADMA_CHNL_INT2 (IRQ_PXA1928_INT48_BASE + 20) |
| #define IRQ_PXA1928_ADMA_CHNL_INT3 (IRQ_PXA1928_INT48_BASE + 21) |
| #define IRQ_PXA1928_VDMA_INT (IRQ_PXA1928_INT48_BASE + 22) |
| |
| /* secondary interrupt of INT #51 */ |
| #define IRQ_PXA1928_INT51_BASE (IRQ_PXA1928_INT48_BASE + 23) |
| #define IRQ_PXA1928_SSP1_SRDY (IRQ_PXA1928_INT51_BASE + 0) |
| #define IRQ_PXA1928_SSP3_SRDY (IRQ_PXA1928_INT51_BASE + 1) |
| |
| /* secondary interrupt of INT #57 */ |
| #define IRQ_PXA1928_INT57_BASE (IRQ_PXA1928_INT51_BASE + 2) |
| #define IRQ_PXA1928_DSP_INT_2 (IRQ_PXA1928_INT57_BASE + 2) |
| #define IRQ_PXA1928_DSP_INT_3 (IRQ_PXA1928_INT57_BASE + 3) |
| #define IRQ_PXA1928_DSP_INT_4 (IRQ_PXA1928_INT57_BASE + 4) |
| #define IRQ_PXA1928_DSP_INT_5 (IRQ_PXA1928_INT57_BASE + 5) |
| #define IRQ_PXA1928_DSP_INT_6 (IRQ_PXA1928_INT57_BASE + 6) |
| #define IRQ_PXA1928_DSP_INT_7 (IRQ_PXA1928_INT57_BASE + 7) |
| #define IRQ_PXA1928_DSP_INT_9 (IRQ_PXA1928_INT57_BASE + 9) |
| #define IRQ_PXA1928_DSP_INT_10 (IRQ_PXA1928_INT57_BASE + 10) |
| #define IRQ_PXA1928_DSP_INT_11 (IRQ_PXA1928_INT57_BASE + 11) |
| #define IRQ_PXA1928_THERMAL_SENSOR (IRQ_PXA1928_INT57_BASE + 13) |
| #define IRQ_PXA1928_MAIN_PMU_INT (IRQ_PXA1928_INT57_BASE + 14) |
| #define IRQ_PXA1928_MULTICORE_NCNTVIRQ0 (IRQ_PXA1928_INT57_BASE + 15) |
| #define IRQ_PXA1928_MULTICORE_NCNTVIRQ1 (IRQ_PXA1928_INT57_BASE + 16) |
| #define IRQ_PXA1928_MULTICORE_NCNTVIRQ2 (IRQ_PXA1928_INT57_BASE + 17) |
| #define IRQ_PXA1928_MULTICORE_NCNTVIRQ3 (IRQ_PXA1928_INT57_BASE + 18) |
| #define IRQ_PXA1928_MULTICORE_NCNTHPIRQ0 (IRQ_PXA1928_INT57_BASE + 19) |
| #define IRQ_PXA1928_MULTICORE_NCNTHPIRQ1 (IRQ_PXA1928_INT57_BASE + 20) |
| #define IRQ_PXA1928_MULTICORE_NCNTHPIRQ2 (IRQ_PXA1928_INT57_BASE + 21) |
| #define IRQ_PXA1928_MULTICORE_NCNTHPIRQ3 (IRQ_PXA1928_INT57_BASE + 22) |
| #define IRQ_PXA1928_APMU_INT (IRQ_PXA1928_INT57_BASE + 23) |
| |
| #define IRQ_PXA1928_END (IRQ_PXA1928_INT57_BASE + 24) |
| |
| #else /* Use GIC Only Mode */ |
| |
| #define IRQ_PXA1928_KEYPAD_WAKEUP (IRQ_PXA1928_START + 64) |
| #define IRQ_PXA1928_USB_OTG_WAKEUP (IRQ_PXA1928_START + 66) |
| #define IRQ_PXA1928_MMC1_WAKEUP (IRQ_PXA1928_START + 68) |
| #define IRQ_PXA1928_MMC2_WAKEUP (IRQ_PXA1928_START + 70) |
| #define IRQ_PXA1928_MMC3_WAKEUP (IRQ_PXA1928_START + 72) |
| #define IRQ_PXA1928_MMC4_WAKEUP (IRQ_PXA1928_START + 74) |
| #define IRQ_PXA1928_CHARGER (IRQ_PXA1928_START + 76) |
| #define IRQ_PXA1928_PMIC (IRQ_PXA1928_START + 77) |
| #define IRQ_PXA1928_CHRG_DTC_OUT (IRQ_PXA1928_START + 78) |
| #define IRQ_PXA1928_RTC_ALARM (IRQ_PXA1928_START + 79) |
| #define IRQ_PXA1928_RTC (IRQ_PXA1928_START + 80) |
| #define IRQ_PXA1928_GC2200 (IRQ_PXA1928_START + 81) |
| #define IRQ_PXA1928_GC320 (IRQ_PXA1928_START + 82) |
| #define IRQ_PXA1928_MULTICORE_INT_CPU3 (IRQ_PXA1928_START + 83) |
| #define IRQ_PXA1928_TWSI2 (IRQ_PXA1928_START + 84) |
| #define IRQ_PXA1928_TWSI3 (IRQ_PXA1928_START + 85) |
| #define IRQ_PXA1928_TWSI4 (IRQ_PXA1928_START + 86) |
| #define IRQ_PXA1928_TWSI5 (IRQ_PXA1928_START + 87) |
| #define IRQ_PXA1928_TWSI6 (IRQ_PXA1928_START + 88) |
| #define IRQ_PXA1928_MULTICORE_INT_CPU2 (IRQ_PXA1928_START + 89) |
| #define IRQ_PXA1928_MULTICORE_INT_CPU1 (IRQ_PXA1928_START + 90) |
| #define IRQ_PXA1928_ISP_DMA (IRQ_PXA1928_START + 91) |
| #define IRQ_PXA1928_DXO_ISP (IRQ_PXA1928_START + 92) |
| #define IRQ_PXA1928_MULTICORE_INT_CPU0 (IRQ_PXA1928_START + 93) |
| #define IRQ_PXA1928_CA7_MP_TRIGGER0 (IRQ_PXA1928_START + 94) |
| #define IRQ_PXA1928_CA7_MP_TRIGGER1 (IRQ_PXA1928_START + 95) |
| #define IRQ_PXA1928_CA7_MP_TRIGGER2 (IRQ_PXA1928_START + 96) |
| #define IRQ_PXA1928_CA7_MP_TRIGGER3 (IRQ_PXA1928_START + 97) |
| #define IRQ_PXA1928_CA7_MP_COMMTX0 (IRQ_PXA1928_START + 98) |
| #define IRQ_PXA1928_CA7_MP_COMMTX1 (IRQ_PXA1928_START + 99) |
| #define IRQ_PXA1928_CA7_MP_COMMTX2 (IRQ_PXA1928_START + 100) |
| #define IRQ_PXA1928_CA7_MP_COMMTX3 (IRQ_PXA1928_START + 101) |
| #define IRQ_PXA1928_CA7_MP_COMMRX0 (IRQ_PXA1928_START + 102) |
| #define IRQ_PXA1928_CA7_MP_COMMRX1 (IRQ_PXA1928_START + 103) |
| #define IRQ_PXA1928_CA7_MP_COMMRX2 (IRQ_PXA1928_START + 104) |
| #define IRQ_PXA1928_CA7_MP_COMMRX3 (IRQ_PXA1928_START + 105) |
| #define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ0 (IRQ_PXA1928_START + 106) |
| #define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ1 (IRQ_PXA1928_START + 107) |
| #define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ2 (IRQ_PXA1928_START + 108) |
| #define IRQ_PXA1928_MULTICORE_CTI_NCTIIRQ3 (IRQ_PXA1928_START + 109) |
| #define IRQ_PXA1928_MULTICORE_NPMUIRQ0 (IRQ_PXA1928_START + 110) |
| #define IRQ_PXA1928_MULTICORE_NPMUIRQ1 (IRQ_PXA1928_START + 111) |
| #define IRQ_PXA1928_MULTICORE_NPMUIRQ2 (IRQ_PXA1928_START + 112) |
| #define IRQ_PXA1928_MULTICORE_NPMUIRQ3 (IRQ_PXA1928_START + 113) |
| #define IRQ_PXA1928_CORE_MP_NAXIERRIRQ (IRQ_PXA1928_START + 114) |
| #define IRQ_PXA1928_WDT2_INT (IRQ_PXA1928_START + 115) |
| #define IRQ_PXA1928_MCK_PML_OVERFLOW (IRQ_PXA1928_START + 118) |
| #define IRQ_PXA1928_CCIC2 (IRQ_PXA1928_START + 119) |
| #define IRQ_PXA1928_CCIC1 (IRQ_PXA1928_START + 120) |
| #define IRQ_PXA1928_SSP1_SRDY (IRQ_PXA1928_START + 121) |
| #define IRQ_PXA1928_SSP3_SRDY (IRQ_PXA1928_START + 122) |
| #define IRQ_PXA1928_DSP_INT_2 (IRQ_PXA1928_START + 123) |
| #define IRQ_PXA1928_DSP_INT_3 (IRQ_PXA1928_START + 124) |
| #define IRQ_PXA1928_DSP_INT_4 (IRQ_PXA1928_START + 125) |
| #define IRQ_PXA1928_DSP_INT_5 (IRQ_PXA1928_START + 126) |
| #define IRQ_PXA1928_DSP_INT_6 (IRQ_PXA1928_START + 127) |
| #define IRQ_PXA1928_DSP_INT_7 (IRQ_PXA1928_START + 128) |
| #define IRQ_PXA1928_DSP_INT_9 (IRQ_PXA1928_START + 129) |
| #define IRQ_PXA1928_DSP_INT_10 (IRQ_PXA1928_START + 130) |
| #define IRQ_PXA1928_DSP_INT_11 (IRQ_PXA1928_START + 131) |
| #define IRQ_PXA1928_THERMAL_SENSOR (IRQ_PXA1928_START + 132) |
| #define IRQ_PXA1928_MAIN_PMU_INT (IRQ_PXA1928_START + 133) |
| #define IRQ_PXA1928_APMU_INT (IRQ_PXA1928_START + 134) |
| #define IRQ_PXA1928_DMA_CHNL_INT0 (IRQ_PXA1928_START + 135) |
| #define IRQ_PXA1928_DMA_CHNL_INT1 (IRQ_PXA1928_START + 136) |
| #define IRQ_PXA1928_DMA_CHNL_INT2 (IRQ_PXA1928_START + 137) |
| #define IRQ_PXA1928_DMA_CHNL_INT3 (IRQ_PXA1928_START + 138) |
| #define IRQ_PXA1928_DMA_CHNL_INT4 (IRQ_PXA1928_START + 139) |
| #define IRQ_PXA1928_DMA_CHNL_INT5 (IRQ_PXA1928_START + 140) |
| #define IRQ_PXA1928_DMA_CHNL_INT6 (IRQ_PXA1928_START + 141) |
| #define IRQ_PXA1928_DMA_CHNL_INT7 (IRQ_PXA1928_START + 142) |
| #define IRQ_PXA1928_DMA_CHNL_INT8 (IRQ_PXA1928_START + 143) |
| #define IRQ_PXA1928_DMA_CHNL_INT9 (IRQ_PXA1928_START + 144) |
| #define IRQ_PXA1928_DMA_CHNL_INT10 (IRQ_PXA1928_START + 145) |
| #define IRQ_PXA1928_DMA_CHNL_INT11 (IRQ_PXA1928_START + 146) |
| #define IRQ_PXA1928_DMA_CHNL_INT12 (IRQ_PXA1928_START + 147) |
| #define IRQ_PXA1928_DMA_CHNL_INT13 (IRQ_PXA1928_START + 148) |
| #define IRQ_PXA1928_DMA_CHNL_INT14 (IRQ_PXA1928_START + 149) |
| #define IRQ_PXA1928_DMA_CHNL_INT15 (IRQ_PXA1928_START + 150) |
| #define IRQ_PXA1928_MDMA_CHNL_INT0 (IRQ_PXA1928_START + 151) |
| #define IRQ_PXA1928_MDMA_CHNL_INT1 (IRQ_PXA1928_START + 152) |
| #define IRQ_PXA1928_ADMA_CHNL_INT0 (IRQ_PXA1928_START + 153) |
| #define IRQ_PXA1928_ADMA_CHNL_INT1 (IRQ_PXA1928_START + 154) |
| #define IRQ_PXA1928_ADMA_CHNL_INT2 (IRQ_PXA1928_START + 155) |
| #define IRQ_PXA1928_ADMA_CHNL_INT3 (IRQ_PXA1928_START + 156) |
| #define IRQ_PXA1928_VDMA_INT (IRQ_PXA1928_START + 157) |
| |
| #define IRQ_PXA1928_END (IRQ_PXA1928_START + 160) |
| #endif |
| |
| #if defined(CONFIG_CPU_PXA1928) |
| #define IRQ_GPIO_START IRQ_PXA1928_END |
| #else |
| #define IRQ_GPIO_START 128 |
| #endif |
| #define MMP_NR_BUILTIN_GPIO 192 |
| |
| #define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO) |
| #define MMP_NR_IRQS IRQ_BOARD_START |
| #define MMP_GPIO_TO_IRQ(gpio) (IRQ_GPIO_START + (gpio)) |
| |
| #endif /* __ASM_MACH_IRQS_H */ |