| /* |
| * linux/arch/arm/mach-mmp/include/soc/asr/regs-icu.h |
| * |
| * Interrupt Control Unit |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| #ifndef __ASM_MACH_ICU_H |
| #define __ASM_MACH_ICU_H |
| |
| #include <soc/asr/addr-map.h> |
| |
| #if defined(CONFIG_CPU_PXA1928) |
| #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x84000) |
| #else |
| #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000) |
| #endif |
| #define ICU_REG(x) (ICU_VIRT_BASE + (x)) |
| |
| #define ICU_INT_CONF(n) ICU_REG((n) << 2) |
| #define ICU_INT_CONF_MASK (0xf) |
| |
| /************ PXA168/PXA910 (MMP) *********************/ |
| #define ICU_INT_CONF_AP_INT (1 << 6) |
| #define ICU_INT_CONF_CP_INT (1 << 5) |
| #define ICU_INT_CONF_IRQ (1 << 4) |
| |
| #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */ |
| #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */ |
| #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */ |
| #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */ |
| #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */ |
| |
| /************************** MMP2 ***********************/ |
| |
| /* |
| * IRQ0/FIQ0 is routed to SP IRQ/FIQ. |
| * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ. |
| */ |
| #define ICU_INT_ROUTE_SP_IRQ (1 << 4) |
| #define ICU_INT_ROUTE_PJ4_IRQ (1 << 5) |
| #define ICU_INT_ROUTE_PJ4_FIQ (1 << 6) |
| |
| #define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138) |
| #define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c) |
| #define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140) |
| #define MMP2_ICU_PJ4_FIQ_STATUS1 ICU_REG(0x144) |
| |
| #define MMP2_ICU_INT4_STATUS ICU_REG(0x150) |
| #define MMP2_ICU_INT5_STATUS ICU_REG(0x154) |
| #define MMP2_ICU_INT17_STATUS ICU_REG(0x158) |
| #define MMP2_ICU_INT35_STATUS ICU_REG(0x15c) |
| #define MMP2_ICU_INT51_STATUS ICU_REG(0x160) |
| |
| #define MMP2_ICU_INT4_MASK ICU_REG(0x168) |
| #define MMP2_ICU_INT5_MASK ICU_REG(0x16C) |
| #define MMP2_ICU_INT17_MASK ICU_REG(0x170) |
| #define MMP2_ICU_INT35_MASK ICU_REG(0x174) |
| #define MMP2_ICU_INT51_MASK ICU_REG(0x178) |
| |
| #define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100) |
| #define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104) |
| #define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108) |
| |
| #define MMP2_ICU_INVERT ICU_REG(0x164) |
| |
| #define MMP2_ICU_INV_PMIC (1 << 0) |
| #define MMP2_ICU_INV_PERF (1 << 1) |
| #define MMP2_ICU_INV_COMMTX (1 << 2) |
| #define MMP2_ICU_INV_COMMRX (1 << 3) |
| |
| #if defined(CONFIG_CPU_PXA1928) |
| #define PXA1928_ICU_INT_CONF_AP(n) (1 << (6 + ((n & 0x3) << 1))) |
| #define PXA1928_ICU_INT_CONF_AP_MASK (0x55 << 6) |
| #define PXA1928_ICU_INT_CONF_PRIO(n) (n & 0xF) |
| |
| /* |
| * ICU Configuration Register Bit Definitions: |
| * IRQ SP routes to SP IRQ |
| * FIRQ1 routes to CA7-1 FIQ |
| * IRQ1 routes to CA7-1 IRQ |
| * FIRQ2 routes to CA7-2 FIQ |
| * IRQ2 routes to CA7-2 IRQ |
| */ |
| |
| #define ICU_INT_ROUTE_SP_IRQ (1 << 4) |
| #define ICU_INT_ROUTE_CA7_1_FIQ (1 << 5) |
| #define ICU_INT_ROUTE_CA7_1_IRQ (1 << 6) |
| #define ICU_INT_ROUTE_CA7_2_FIQ (1 << 7) |
| #define ICU_INT_ROUTE_CA7_2_IRQ (1 << 8) |
| #define ICU_INT_ROUTE_CA7_3_FIQ (1 << 9) |
| #define ICU_INT_ROUTE_CA7_3_IRQ (1 << 10) |
| #define ICU_INT_ROUTE_CA7_4_FIQ (1 << 11) |
| #define ICU_INT_ROUTE_CA7_4_IRQ (1 << 12) |
| |
| #define PXA1928_ICU_IRQ_SP_SEL_INT_NUM ICU_REG(0x100) |
| #define PXA1928_ICU_FIQ1_SEL_INT_NUM ICU_REG(0x104) |
| #define PXA1928_ICU_IRQ1_SEL_INT_NUM ICU_REG(0x108) |
| #define PXA1928_ICU_FIQ2_SEL_INT_NUM ICU_REG(0x18C) |
| #define PXA1928_ICU_IRQ2_SEL_INT_NUM ICU_REG(0x1d4) |
| |
| #define PXA1928_ICU_GBL_IRQ_SP_MSK ICU_REG(0x10C) |
| #define PXA1928_ICU_GBL_FIQ1_MSK ICU_REG(0x110) |
| #define PXA1928_ICU_GBL_IRQ1_MSK ICU_REG(0x114) |
| #define PXA1928_ICU_GBL_FIQ2_MSK ICU_REG(0x190) |
| #define PXA1928_ICU_GBL_IRQ2_MSK ICU_REG(0x1d8) |
| #define PXA1928_ICU_GBL_FIQ3_MSK ICU_REG(0x1f0) |
| #define PXA1928_ICU_GBL_IRQ3_MSK ICU_REG(0x208) |
| #define PXA1928_ICU_GBL_FIQ4_MSK ICU_REG(0x220) |
| #define PXA1928_ICU_GBL_IRQ4_MSK ICU_REG(0x238) |
| |
| #define PXA1928_ICU_CORE0_GBL_IRQ_MSK PXA1928_ICU_GBL_IRQ1_MSK |
| #define PXA1928_ICU_CORE1_GBL_IRQ_MSK PXA1928_ICU_GBL_IRQ2_MSK |
| #define PXA1928_ICU_CORE2_GBL_IRQ_MSK PXA1928_ICU_GBL_IRQ3_MSK |
| #define PXA1928_ICU_CORE3_GBL_IRQ_MSK PXA1928_ICU_GBL_IRQ4_MSK |
| #define PXA1928_ICU_CORE0_GBL_FIQ_MSK PXA1928_ICU_GBL_FIQ1_MSK |
| #define PXA1928_ICU_CORE1_GBL_FIQ_MSK PXA1928_ICU_GBL_FIQ2_MSK |
| #define PXA1928_ICU_CORE2_GBL_FIQ_MSK PXA1928_ICU_GBL_FIQ3_MSK |
| #define PXA1928_ICU_CORE3_GBL_FIQ_MSK PXA1928_ICU_GBL_FIQ4_MSK |
| |
| #define PXA1928_ICU_DMA_IRQ_SP_MASK ICU_REG(0x118) |
| #define PXA1928_ICU_DMA_FIQ1_MASK ICU_REG(0x11C) |
| #define PXA1928_ICU_DMA_IRQ1_MASK ICU_REG(0x120) |
| #define PXA1928_ICU_DMA_FIQ2_MASK ICU_REG(0x194) |
| #define PXA1928_ICU_DMA_IRQ2_MASK ICU_REG(0x1dc) |
| #define PXA1928_ICU_DMA_FIQ3_MASK ICU_REG(0x1f4) |
| #define PXA1928_ICU_DMA_IRQ3_MASK ICU_REG(0x20c) |
| #define PXA1928_ICU_DMA_FIQ4_MASK ICU_REG(0x224) |
| #define PXA1928_ICU_DMA_IRQ4_MASK ICU_REG(0x23c) |
| #define CORE0_CA7_GLB_IRQ_MASK 0x114 |
| #define CORE1_CA7_GLB_IRQ_MASK 0x1d8 |
| #define CORE2_CA7_GLB_IRQ_MASK 0x208 |
| #define CORE3_CA7_GLB_IRQ_MASK 0x238 |
| |
| #define CORE0_CA7_GLB_FIQ_MASK 0x110 |
| #define CORE1_CA7_GLB_FIQ_MASK 0x190 |
| #define CORE2_CA7_GLB_FIQ_MASK 0x1f0 |
| #define CORE3_CA7_GLB_FIQ_MASK 0x220 |
| |
| |
| #define PXA1928_ICU_DMA_IRQ_SP_STATUS ICU_REG(0x124) |
| #define PXA1928_ICU_DMA_FIQ1_STATUS ICU_REG(0x128) |
| #define PXA1928_ICU_DMA_IRQ1_STATUS ICU_REG(0x12C) |
| #define PXA1928_ICU_DMA_FIQ2_STATUS ICU_REG(0x198) |
| #define PXA1928_ICU_DMA_IRQ2_STATUS ICU_REG(0x1E0) |
| #define PXA1928_ICU_DMA_FIQ3_STATUS ICU_REG(0x1f8) |
| #define PXA1928_ICU_DMA_IRQ3_STATUS ICU_REG(0x210) |
| #define PXA1928_ICU_DMA_FIQ4_STATUS ICU_REG(0x228) |
| #define PXA1928_ICU_DMA_IRQ4_STATUS ICU_REG(0x240) |
| |
| #define PXA1928_ICU_IRQ_SP_STATUS_0 ICU_REG(0x130) |
| #define PXA1928_ICU_IRQ_SP_STATUS_1 ICU_REG(0x134) |
| #define PXA1928_ICU_FIQ1_STATUS_0 ICU_REG(0x138) |
| #define PXA1928_ICU_FIQ1_STATUS_1 ICU_REG(0x13C) |
| #define PXA1928_ICU_IRQ1_STATUS_0 ICU_REG(0x140) |
| #define PXA1928_ICU_IRQ1_STATUS_1 ICU_REG(0x144) |
| #define PXA1928_ICU_FIQ2_STATUS_0 ICU_REG(0x19C) |
| #define PXA1928_ICU_FIQ2_STATUS_1 ICU_REG(0x1A0) |
| #define PXA1928_ICU_IRQ2_STATUS_0 ICU_REG(0x1E4) |
| #define PXA1928_ICU_IRQ2_STATUS_1 ICU_REG(0x1E8) |
| |
| #define PXA1928_ICU_INT_4_STATUS ICU_REG(0x150) |
| #define PXA1928_ICU_INT_5_STATUS ICU_REG(0x154) |
| #define PXA1928_ICU_INT_6_STATUS ICU_REG(0x1BC) |
| #define PXA1928_ICU_INT_8_STATUS ICU_REG(0x1C0) |
| #define PXA1928_ICU_INT_17_STATUS ICU_REG(0x158) |
| #define PXA1928_ICU_INT_18_STATUS ICU_REG(0x1C4) |
| #define PXA1928_ICU_INT_30_STATUS ICU_REG(0x1C8) |
| #define PXA1928_ICU_INT_35_STATUS ICU_REG(0x15C) |
| #define PXA1928_ICU_INT_42_STATUS ICU_REG(0x1CC) |
| #define PXA1928_ICU_INT_51_STATUS ICU_REG(0x160) |
| #define PXA1928_ICU_INT_INVERT ICU_REG(0x164) |
| #define PXA1928_ICU_INT_55_STATUS ICU_REG(0x184) |
| #define PXA1928_ICU_INT_57_STATUS ICU_REG(0x188) |
| #define PXA1928_ICU_INT_58_STATUS ICU_REG(0x1D0) |
| |
| #define PXA1928_ICU_INT_4_MASK ICU_REG(0x168) |
| #define PXA1928_ICU_INT_5_MASK ICU_REG(0x16C) |
| #define PXA1928_ICU_INT_6_MASK ICU_REG(0x1A4) |
| #define PXA1928_ICU_INT_8_MASK ICU_REG(0x1A8) |
| #define PXA1928_ICU_INT_17_MASK ICU_REG(0x170) |
| #define PXA1928_ICU_INT_18_MASK ICU_REG(0x1AC) |
| #define PXA1928_ICU_INT_30_MASK ICU_REG(0x1B0) |
| #define PXA1928_ICU_INT_35_MASK ICU_REG(0x174) |
| #define PXA1928_ICU_INT_42_MASK ICU_REG(0x1B4) |
| #define PXA1928_ICU_INT_51_MASK ICU_REG(0x178) |
| #define PXA1928_ICU_INT_55_MASK ICU_REG(0x17C) |
| #define PXA1928_ICU_INT_57_MASK ICU_REG(0x180) |
| #define PXA1928_ICU_INT_58_MASK ICU_REG(0x1B8) |
| |
| #endif /* CONFIG_CPU_PXA1928 */ |
| |
| #endif /* __ASM_MACH_ICU_H */ |