| /****************************************************************************** |
| * |
| * (C)Copyright 2005 - 2011 Marvell. All Rights Reserved. |
| * |
| * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL. |
| * The copyright notice above does not evidence any actual or intended |
| * publication of such source code. |
| * This Module contains Proprietary Information of Marvell and should be |
| * treated as Confidential. |
| * The information in this file is provided for the exclusive use of the |
| * licensees of Marvell. |
| * Such users have the right to use, modify, and incorporate this code into |
| * products for purposes authorized by the license agreement provided they |
| * include this notice and the associated copyright notice with any such |
| * product. |
| * The information in this file is provided "AS IS" without warranty. |
| * |
| ******************************************************************************/ |
| |
| |
| #ifndef __SDHC2_CONTROLLER_H |
| #define __SDHC2_CONTROLLER_H |
| |
| #include "Typedef.h" |
| |
| // MMC controller registers definition |
| typedef struct |
| { |
| VUINT32_T mm4_sysaddr; // DMA system address 0x0 |
| VUINT32_T mm4_blk_cntl; // Block size control register 0x4 |
| VUINT32_T mm4_arg; // Command argument 0x8 |
| VUINT32_T mm4_cmd_xfrmd; // Command and transfer mode 0xC |
| VUINT32_T mm4_resp0; // cmd response 0 0x10 |
| VUINT32_T mm4_resp1; // cmd response 1 0x14 |
| VUINT32_T mm4_resp2; // cmd response 2 0x18 |
| VUINT32_T mm4_resp3; // cmd response 3 0x1C |
| VUINT32_T mm4_dp; // buffer data port 0x20 |
| VUINT32_T mm4_state; // mm4 state 0x24 |
| VUINT32_T mm4_cntl1; // host control 1 0x28 |
| VUINT32_T mm4_cntl2; // host control 2 0x2C |
| VUINT32_T mm4_i_stat; // status of current command 0x30 |
| VUINT32_T mm4_i_stat_en; // interrupt status enable 0x34 |
| VUINT32_T mm4_i_sig_en; // interrupt signal enable 0x38 |
| VUINT32_T mm4_acmd12_er; // auto cmd12 error status 0x3C |
| VUINT32_T mm4_cap1_2; // capabilities 1,2 0x40 |
| VUINT32_T mm4_cap3_4; // capabilities 3,4 0x44 |
| VUINT32_T mm4_sd_max_current1_2; // max current capabilities 0x48 |
| VUINT32_T mm4_sd_max_current3_4; // max current capabilities 0x4C |
| VUINT32_T mm4_force_event; // force event for AutoCMD12 Error Status 0x50 |
| VUINT32_T mm4_adma_err_stat; // ADMA Error Status 0x54 |
| VUINT32_T mm4_adma_system_address1; // ADMA Address 63:32 0x58 |
| VUINT32_T mm4_adma_system_address2; // ADMA Address 32:0 |
| VUINT32_T mm4_preset_value_for_init_ds; // 0x60 |
| VUINT32_T mm4_preset_value_for_hs_sdr12; // 0x64 |
| VUINT32_T mm4_preset_value_for_hs_sdr25_50; // 0x68 |
| VUINT32_T mm4_preset_value_for_hs_sdr104_50; // 0x6C |
| VUINT32_T reserved_X1[28]; // reserved fields 0x70 |
| VUINT32_T mm4_shared_bus_control; // Shared Bus Control Register 0xE0 |
| VUINT32_T reserved_X2[6]; // reserved 0xE4 |
| VUINT32_T mm4_sd_slot_int_stat_ctrl_ver; // SD Interrupt Line and Version Support 0xFC |
| VUINT32_T mm4_vid_pid; // SD HOST CTRL Vendor ID/Project ID/version ID Register 0x100 |
| VUINT32_T mm4_op_ctrl; // SDHC Opeartion Control register 0x104 |
| VUINT32_T mm4_op_ext_reg; // SDHC Operation extend CTRL Register 0x108 |
| VUINT32_T mm4_legacy_ctrl_reg; // SDHC LEGACY CTRL Parameters Register 0x10C |
| VUINT32_T mm4_legacy_ceata_reg; // SDHC LEGACY CTRL for CEATA Device Register 0x110 |
| VUINT32_T mm4_mmc_ctrl_reg; // SDHC MMC DEVICE CTRL Registers 0x114 |
| VUINT32_T mm4_sd_rx_cfg_reg; // Receive Timing Config 0x118 |
| VUINT32_T mm4_sd_tx_cfg_reg; // Transmit Timing Config 0x11C |
| VUINT32_T mm4_sd_hwtune_cfg_reg; // SDHC HW TUNING Configuration Register 0x120 |
| VUINT32_T mm4_sd_hwtune_cfg2_reg; // SDHC HW TUNING Configuration2 Register 0x124 |
| VUINT32_T mm4_sd_roundtrip_timing_reg; // SDHC ROUND TRIP(TRANSIMIT TO RECEIVE) TIMING PARAM Regsiter 0x128 |
| VUINT32_T mm4_sd_gpio_cfg_reg; // SDHC GPIO CFG Register 0x12C |
| VUINT32_T mm4_sd_dline_ctrl_reg; // SDHC DELAYLINE Control Register 0x130 |
| VUINT32_T mm4_sd_dline_cfg_reg; // SDHC DELAYLINE CFG Register 0x134 |
| } MM4_SDMMC_T, *P_MM4_SDMMC_T; |
| |
| /*************************** Register Masks ********************************/ |
| /**************************************************************************/ |
| // ******************** MM4_BLK_CNTL ********************************** |
| typedef struct |
| { |
| unsigned int xfr_blksz : 12; // Transfer Block Size |
| unsigned int dma_bufsz : 4; // Host DMA buffer size |
| unsigned int blk_cnt : 16; // Block Count for Current Transfer |
| } MM4_BLK_CNTL, *P_MM4_BLK_CNTL; |
| |
| #define MM4_512_HOST_DMA_BDRY 0x7 |
| |
| // ********************* MM4_CMD_XFRMD ******************************** |
| typedef struct |
| { |
| unsigned int dma_en : 1; // DMA enable 0 |
| unsigned int blkcnten : 1; // Block Count Enable 1 |
| unsigned int autocmd12 : 1; // AutoCMD12 2 |
| unsigned int autocmd23 : 1; // AutoCMD23 3 |
| unsigned int dxfrdir : 1; // Data Transfer Direction Select 4 |
| unsigned int ms_blksel : 1; // Multi Block Select 5 |
| unsigned int reserved2 : 10; // 6 |
| unsigned int res_type : 2; // Response Type 16 |
| unsigned int reserved3 : 1; // 18 |
| unsigned int crcchken : 1; // CRC check enable 19 |
| unsigned int idxchken : 1; // Command Index Check Enable 20 |
| unsigned int dpsel : 1; // Data present select 21 |
| unsigned int cmd_type : 2; // Cmd Type 22 |
| unsigned int cmd_idx : 6; // Cmd Index 24 |
| unsigned int reserved4 : 2; // 30 |
| } MM4_CMD_XFRMD, *P_MM4_CMD_XFRMD; |
| |
| typedef union |
| { |
| MM4_CMD_XFRMD mm4_cmd_xfrmd_bits; |
| UINT_T mm4_cmd_xfrmd_value; |
| } MM4_CMD_XFRMD_UNION, *P_MM4_CMD_XFRMD_UNION; |
| |
| #define NO_ARGUMENT 0x0 |
| #define MM4_CMD_TYPE_NORMAL 0 |
| #define MM4_CMD_TYPE_SUSPEND 1 |
| #define MM4_CMD_TYPE_RESUME 2 |
| #define MM4_CMD_TYPE_ABORT 3 |
| #define MM4_CMD_DATA 1 |
| #define MM4_CMD_NODATA 0 |
| #define MM4_NO_RES 0 |
| #define MM4_136_RES 1 |
| #define MM4_48_RES 2 |
| #define MM4_48_RES_WITH_BUSY 3 |
| |
| // this information will be included in the response type argument of relevant apis. |
| // it will occupy bits 15:8 of the RespType parameter. |
| #define MM4_RT_MASK 0x7f00 |
| #define MM4_RT_NONE 0x0000 |
| #define MM4_RT_R1 0x0100 |
| #define MM4_RT_R2 0x0200 |
| #define MM4_RT_R3 0x0300 |
| #define MM4_RT_R4 0x0400 |
| #define MM4_RT_R5 0x0500 |
| #define MM4_RT_R6 0x0600 |
| #define MM4_RT_R7 0x0700 // sd card interface condition |
| |
| #define MM4_RT_BUSYMASK 0x8000 |
| #define MM4_RT_BUSY 0x8000 |
| |
| |
| #define MM4_MULTI_BLOCK_TRAN 1 |
| #define MM4_SINGLE_BLOCK_TRAN 0 |
| #define MM4_HOST_TO_CARD_DATA 0 |
| #define MM4_CARD_TO_HOST_DATA 1 |
| |
| // ********************* MM4_STATE ******************************** |
| typedef struct |
| { |
| unsigned int ccmdinhbt : 1; |
| unsigned int dcmdinhbt : 1; |
| unsigned int datactv : 1; |
| unsigned int retuning_req : 1; |
| unsigned int reserved0 : 4; |
| unsigned int wractv : 1; |
| unsigned int rdactv : 1; |
| unsigned int bufwren : 1; |
| unsigned int bufrden : 1; |
| unsigned int reserved1 : 4; |
| unsigned int cdinstd : 1; |
| unsigned int cdstbl : 1; |
| unsigned int cddetlvl : 1; |
| unsigned int wpswlvl : 1; |
| unsigned int lwrdatlvl : 4; |
| unsigned int cmdlvl : 1; |
| unsigned int uprdatlvl : 4; |
| unsigned int reserved2 : 3; |
| } MM4_STATE, *P_MM4_STATE; |
| |
| typedef union |
| { |
| MM4_STATE mm4_state_bits; |
| UINT_T mm4_state_value; |
| } MM4_STATE_UNION, *P_MM4_STATE_UNION; |
| |
| // ********************* MM4_CNTL1 ******************************** |
| typedef struct |
| { |
| unsigned int ledcntl : 1; // 0 |
| unsigned int datawidth : 1; // 1 |
| unsigned int hispeed : 1; // 2 |
| unsigned int dma_sel : 2; // 3 |
| unsigned int ex_data_width : 1; // 5 |
| unsigned int card_det_l : 1; // 6 |
| unsigned int card_det_s : 1; // 7 |
| unsigned int buspwr : 1; // 8 |
| unsigned int vltgsel : 3; // 9 |
| unsigned int reserved2 : 4; // 12 |
| unsigned int bgreqstp : 1; // 16 |
| unsigned int contreq : 1; |
| unsigned int rdwcntl : 1; |
| unsigned int bgirqen : 1; |
| unsigned int reserved3 : 12; |
| } MM4_CNTL1, *P_MM4_CNTL1; |
| |
| typedef union |
| { |
| MM4_CNTL1 mm4_cntl1_bits; |
| UINT_T mm4_cntl1_value; |
| } MM4_CNTL1_UNION, *P_MM4_CNTL1_UNION; |
| |
| #define MM4_VLTGSEL_1_8 0x5 |
| #define MM4_VLTGSEL_3_0 0x6 |
| #define MM4_VLTGSEL_3_3 0x7 |
| |
| // ********************* MM4_CNTL2 ******************************** |
| typedef struct |
| { |
| unsigned int inter_clk_en : 1; // Internal Clock Enable |
| unsigned int inter_clk_stable : 1; // Internal Clock Stable |
| unsigned int mm4clken : 1; // Clock Enable |
| unsigned int reserved1 : 2; // bits 3,4 |
| unsigned int clk_gen_sel : 1; // bit 5 |
| unsigned int sd_freq_sel_hi : 2; // 6 |
| unsigned int sd_freq_sel_lo : 8; // 8 |
| unsigned int dtocntr : 4; // bit 0 Data Timeout Counter Value |
| unsigned int reserved2 : 4; // |
| unsigned int mswrst : 1; // bit 8 Software Reset for All |
| unsigned int cmdswrst : 1; // bit 9 Software Reset for MM4CMD Line |
| unsigned int datswrst : 1; // bit 10 Software Reset for MM4DATx Lines |
| unsigned int reserved3 : 5; // bits 11-15 |
| } MM4_CNTL2, *P_MM4_CNTL2; |
| |
| // ********************* MM4_HOST_CNTL2 ******************************** |
| typedef struct |
| { |
| unsigned int reserved : 16; // bit 0~15 |
| unsigned int uhs_mode_sel : 3; // bit 16-18: UHS Mode Select |
| unsigned int v1_8_sig_en : 1; // 1.8V Signaling Enable |
| unsigned int dri_strength_sel : 2; // Driver Strength Select |
| unsigned int execute_tunning : 1; // Execute Tuning |
| unsigned int samp_clk_sel : 1; // Sampling Clock Select |
| unsigned int reserved1 : 6; // bits 8~13 |
| unsigned int async_int_en : 1; // Asynchronous Interrupt Enable |
| unsigned int preset_val_en : 1; // Preset Value Enable |
| } MM4_HOST_CNTL2, *P_MM4_HOST_CNTL2; |
| |
| #define SDH_BUS_SPEED_DEFAULT (1<<0) |
| #define SDH_BUS_SPEED_SDR_CLK_50M (1<<1) |
| #define SDH_BUS_SPEED_SDR_CLK_100M (1<<2) |
| #define SDH_BUS_SPEED_SDR_CLK_208M (1<<3) |
| #define SDH_BUS_SPEED_DDR_CLK_50M (1<<4) |
| |
| #define CLOCK_27_MULT 0xE |
| |
| #if BASE_CLOCK_208MHZ |
| //Clock divider settings for 208Mhz bus clock |
| #define MM4CLOCK200KHZRATE 0x1FF // Set also additional SD_FREQ_HI bit. So SD_FREQ_SEL = 0x1FF = 511 * 2 = 1022 (clock divider) |
| #define MM4CLOCK50MHZRATE 2 |
| #define MM4CLOCK25MHZRATE 4 |
| #define MM4CLOCK12_5MHZRATE 8 |
| #define MM4CLOCK6MHZRATE 16 |
| #else |
| //Clock divider settings for 104Mhz bus clock |
| #define MM4CLOCK200KHZRATE 0xFF // Set also additional SD_FREQ_HI bit. So SD_FREQ_SEL = 0x1FF = 511 * 2 = 1022 (clock divider) |
| #define MM4CLOCK50MHZRATE 1 |
| #define MM4CLOCK25MHZRATE 2 |
| #define MM4CLOCK12_5MHZRATE 4 |
| #define MM4CLOCK6MHZRATE 8 |
| #endif |
| |
| typedef union |
| { |
| //Coverity - declare struct volatile to eliminate infinite loop defect |
| volatile MM4_CNTL2 mm4_cntl2_bits; |
| VUINT_T mm4_cntl2_value; |
| } MM4_CNTL2_UNION, *P_MM4_CNTL2_UNION; |
| |
| typedef union |
| { |
| //Coverity - declare struct volatile to eliminate infinite loop defect |
| volatile MM4_HOST_CNTL2 mm4_host_cntl2_bits; |
| VUINT_T mm4_host_cntl2_value; |
| } MM4_HOST_CNTL2_UNION, *P_MM4_HOST_CNTL2_UNION; |
| |
| // ********************* MM4_I_STAT, MM4_I_STAT_EN, MM4_I_SIGN_EN ************ |
| typedef struct |
| { |
| unsigned int cmdcomp : 1; //0 |
| unsigned int xfrcomp : 1; //1 |
| unsigned int bgevnt : 1; //2 |
| unsigned int dmaint : 1; //3 |
| unsigned int bufwrrdy : 1; //4 |
| unsigned int bufrdrdy : 1; //5 |
| unsigned int cdins : 1; //6 |
| unsigned int cdrem : 1; //7 |
| unsigned int cdint : 1; //8 |
| unsigned int int_a : 1; //9 |
| unsigned int int_b : 1; //10 |
| unsigned int int_c : 1; //11 |
| unsigned int retuninig_int : 1; //12 |
| unsigned int reserved0 : 2; //13 |
| unsigned int errint : 1; //15 |
| unsigned int ctoerr : 1; //16 |
| unsigned int ccrcerr : 1; //17 |
| unsigned int cenderr : 1; //18 |
| unsigned int cidxerr : 1; //19 |
| unsigned int dtoerr : 1; //20 |
| unsigned int dcrcerr : 1; //21 |
| unsigned int denderr : 1; //22 |
| unsigned int ilmterr : 1; //23 |
| unsigned int ac12err : 1; //24 |
| unsigned int admaerr : 1; //25 |
| unsigned int tune_err : 1; //26 |
| unsigned int reserved1 : 1; //27 |
| unsigned int spierr : 1; //28 |
| unsigned int axi_resp_err : 1; //29 |
| unsigned int cpl_tout_err : 1; //30 |
| unsigned int crc_stat_err : 1; //31 |
| } MM4_I_STAT, *P_MM4_I_STAT, MM4_I_STAT_EN, *P_MM4_I_STAT_EN, MM4_I_SIGN_EN, *P_MM4_I_SIGN_EN; |
| |
| #define DISABLE_INTS 0 |
| #define ENABLE_INTS 1 |
| |
| typedef union |
| { |
| MM4_I_STAT mm4_i_stat_bits; |
| UINT_T mm4_i_stat_value; |
| } MM4_I_STAT_UNION, *P_MM4_I_STAT_UNION; |
| //#define CLEAR_INTS_MASK 0xFFFF7FFD |
| #define CLEAR_INTS_MASK 0xFFFF7FCD |
| |
| |
| // ********************* MM4_ACMD12_ER ******************************************* |
| typedef struct |
| { |
| unsigned int ac12nexe : 1; // 0 |
| unsigned int ac12toer : 1; // 1 |
| unsigned int ac12crcer : 1; // 2 |
| unsigned int ac12ender : 1; // 3 |
| unsigned int ac12idxer : 1; // 4 |
| unsigned int reserved0 : 2; // 5 |
| unsigned int cmdnisud : 1; // 7 |
| unsigned int reserved1 : 8; // 8 |
| unsigned int uhs_mode_sel : 3; // 16 |
| unsigned int sgh_v18_en : 1; // 19 |
| unsigned int drv_strength_sel : 2; // 20 |
| unsigned int exe_tuning : 1; // 22 |
| unsigned int sampling_clk_sel : 1; // 23 |
| unsigned int reserved2 : 6; // 24 |
| unsigned int async_int_en : 1; // 30 |
| unsigned int pre_val_en : 1; // 31 |
| } MM4_ACMD12_ER, *P_MM4_ACMD12_ER; |
| |
| // ********************* MM4_CAP0 ******************************************* |
| typedef struct |
| { |
| unsigned int toclkfreq : 6; |
| unsigned int reserved0 : 1; |
| unsigned int toclkunit : 1; |
| unsigned int bsclkfreq : 8; |
| unsigned int max_blk_len : 2; |
| unsigned int ex_data_width_support : 1; |
| unsigned int reserved1 : 1; |
| unsigned int adma2_support : 1; |
| unsigned int adma1_support : 1; |
| unsigned int hi_speed_support : 1; |
| unsigned int sdma_support : 1; |
| unsigned int sus_res_support : 1; |
| unsigned int vlg_33_support : 1; |
| unsigned int vlg_30_support : 1; |
| unsigned int vlg_18_support : 1; |
| unsigned int reserved2 : 1; |
| unsigned int sys_bus_64_support : 1; |
| unsigned int async_int_support : 1; |
| unsigned int cfg_slot_type : 1; |
| } MM4_CAP1_2, *P_MM4_CAP1_2; |
| |
| typedef union |
| { |
| MM4_CAP1_2 mm4_cap1_2_bits; |
| UINT_T mm4_cap1_2_value; |
| } MM4_CAP1_2_UNION, *P_MM4_CAP1_2_UNION; |
| |
| // ********************* MM4_SD_MAX_CURRENT1_2 ******************************************* |
| typedef struct |
| { |
| unsigned int v3_3vmaxi : 8; |
| unsigned int v3_0vmaxi : 8; |
| unsigned int v1_8vmaxi : 8; |
| unsigned int reserved0 : 8; |
| } MM4_SD_MAX_CURRENT1_2, *P_MM4_SD_MAX_CURRENT1_2; |
| |
| typedef union |
| { |
| MM4_SD_MAX_CURRENT1_2 mm4_sd_max_current1_2_bits; |
| UINT_T mm4_sd_max_current1_2_value; |
| } MM4_SD_MAX_CURRENT1_2_UNION, *P_MM4_SD_MAX_CURRENT1_2_UNION; |
| |
| // ********************* MM4_SD_LEGACY_CTRL_REG ******************************************* |
| typedef struct |
| { |
| UINT pio_rdfc : 1; // Bit 0 |
| UINT async_io_en : 1; // Bit 1 |
| UINT inand_sel : 1; // Bit 2 |
| UINT boot_ack : 1; // Bit 3 |
| UINT squ_empty_check : 1; // Bit 4 |
| UINT squ_full_check : 1; // Bit 5 |
| UINT gen_pad_clk_on : 1; // Bit 6 |
| UINT reserved0 : 1; // Bit 7 |
| UINT spi_en : 1; // Bit 8 |
| UINT spi_error_token : 5; // Bits 9-13 |
| UINT reserved1 : 10; // Bits 14-23 |
| UINT gen_pad_clk_cnt : 8; // Bits 24-31 |
| } MM4_SD_LEGACY_CTRL_REG, *P_MM4_SD_LEGACY_CTRL_REG; |
| |
| typedef union |
| { |
| MM4_SD_LEGACY_CTRL_REG MM4_SD_LEGACY_CTRL_REG_bits; |
| UINT_T MM4_SD_LEGACY_CTRL_REG_value; |
| } MM4_SD_LEGACY_CTRL_REG_UNION, *P_MM4_SD_LEGACY_CTRL_REG_UNION; |
| |
| #define DISABLE_PAD_SD_CLOCK_GATING_BIT (1 << 10) // 1 means disable dynamic clock gating. |
| #define ENABLE_DYNAMIC_CLOCK_GATING_MASK (~(DISABLE_PAD_SD_CLOCK_GATING_BIT)) |
| |
| // ********************* MM4_CTRL_REG ******************************************* |
| typedef struct |
| { |
| UINT misc_int_int_en : 1; // Bit 0 |
| UINT misc_int_en : 1; // Bit 1 |
| UINT misc_int : 1; // Bit 2 |
| UINT reserved1 : 1; // Bit 3 |
| UINT cpl_complete_int_en : 1; // Bit 4 |
| UINT cpl_complete_en : 1; // Bit 5 |
| UINT cpl_complete : 1; // Bit 6 |
| UINT reserved2 : 1; // Bit 7 |
| UINT enhance_strobe_en : 1; // Bit 8 |
| UINT mmc_hs400 : 1; // Bit 9 |
| UINT mmc_hs200 : 1; // Bit 10 |
| UINT mmc_resetn : 1; // Bit 11 |
| UINT mmc_card : 1; // Bit 12 |
| UINT reserved3 : 11; // Bit 13 |
| UINT data_level : 8; // Bit 24 |
| } MM4_CTRL_REG, *P_MM4_CTRL_REG; |
| |
| typedef union |
| { |
| MM4_CTRL_REG MM4_CTRL_REG_bits; |
| UINT_T MM4_CTRL_REG_value; |
| } MM4_CTRL_REG_UNION, *PMM4_CTRL_REG_UNION; |
| |
| typedef struct |
| { |
| unsigned int adma_state : 2; |
| unsigned int adma_len_err : 1; |
| unsigned int Rsvd : 29; |
| } MM4_ADMA_ERROR_STAT, *P_MM4_ADMA_ERROR_STAT; |
| |
| typedef struct |
| { |
| UINT txholddly0 : 10; //Bits 0-9 |
| UINT rsvd : 6; //Bits 10-15 |
| UINT txholddly1 : 10; //Bits 16-25 |
| UINT rsvd1 : 3; //Bits 26-28 |
| UINT tx_dline_src_sel : 1; //Bit 29 |
| UINT tx_int_clk : 1; //Bit 30 |
| UINT tx_mux_sel : 1; //Bit 31 |
| }MM4_TX_CFG, *P_MM4_TX_CFG; |
| |
| #define DDR_TX_DELAY 0x55 |
| #define TX_MUX_SEL (0x1<<31) |
| #define TX_SEL_BUS_CLK (0x1<<30) |
| #define TX_DELAY1_SHIFT 24 |
| #define TX_DELAY_MASK 0xFF |
| |
| typedef union |
| { |
| MM4_TX_CFG MM4_TX_CFG_bits; |
| UINT_T MM4_TX_CFG_value; |
| }MM4_TX_CFG_UNION, *P_MM4_TX_CFG_UNION; |
| |
| #define DDR_RX_DELAY 0x55 |
| #define RX_SDCLK_DELAY_SHIFT 16 |
| #define RX_SDCLK_DELAY_MASK 0xFF |
| #define RX_SDCLK_SEL1_MASK 0x3 |
| #define RX_SDCLK_SEL1_SHIFT 2 |
| |
| typedef struct |
| { |
| unsigned int rsvd2 : 4; |
| unsigned int tuning_dly_inc: 10; |
| unsigned int sdclk_delay : 10; |
| unsigned int rsvd1 : 4; |
| unsigned int sdclk_sel1 : 2; |
| unsigned int sdclk_sel0 : 2; |
| }MM4_RX_CFG, *P_MM4_RX_CFG; |
| |
| typedef union |
| { |
| MM4_RX_CFG MM4_RX_CFG_bits; |
| UINT_T MM4_RX_CFG_value; |
| }MM4_RX_CFG_UNION, *P_MM4_RX_CFG_UNION; |
| |
| typedef struct |
| { |
| unsigned int dline_pu : 1; |
| unsigned int rsvd1 : 15; |
| unsigned int rx_dline_code : 8; |
| unsigned int tx_dline_code : 8; |
| }MM4_SD_DLINE_CTRL, *P_MM4_SD_DLINE_CTRL; |
| |
| typedef union |
| { |
| MM4_SD_DLINE_CTRL MM4_SD_DLINE_CTRL_bits; |
| UINT_T MM4_SD_DLINE_CTRL_value; |
| }MM4_SD_DLINE_CTRL_UNION, *P_MM4_SD_DLINE_CTRL_UNION; |
| |
| typedef struct |
| { |
| unsigned int rx_dline_reg : 8; |
| unsigned int rx_dline_gain : 1; |
| unsigned int rsvd1 : 7; |
| unsigned int tx_dline_reg : 8; |
| unsigned int tx_dline_gain : 1; |
| unsigned int rsvd2 : 7; |
| }MM4_SD_DLINE_CFG, *P_MM4_SD_DLINE_CFG; |
| |
| typedef union |
| { |
| MM4_SD_DLINE_CFG MM4_SD_DLINE_CFG_bits; |
| UINT_T MM4_SD_DLINE_CFG_value; |
| }MM4_SD_DLINE_CFG_UNION, *P_MM4_SD_DLINE_CFG_UNION; |
| |
| /*********** End MM4 Register Def's **************************************/ |
| // response types |
| enum { |
| MMC_RESPONSE_NONE = 1L<<8, |
| MMC_RESPONSE_R1 = 2L<<8, |
| MMC_RESPONSE_R1B = 3L<<8, |
| MMC_RESPONSE_R2 = 4L<<8, |
| MMC_RESPONSE_R3 = 5L<<8, |
| MMC_RESPONSE_R4 = 6L<<8, |
| MMC_RESPONSE_R5 = 7L<<8, |
| MMC_RESPONSE_R5B = 8L<<8, |
| MMC_RESPONSE_R6 = 9L<<8, |
| MMC_RESPONSE_R7 = 0xAL<<8, |
| MMC_RESPONSE_MASK = 0x0000FF00 |
| }; |
| |
| #define SD_OCR_VOLTAGE_3_3_TO_3_6 0xE00000 |
| #define SD_OCR_VOLTAGE_1_8_TO_3_3 0x1F8000 |
| #define SD_OCR_VOLTAGE_1_8 0x80 |
| #define MMC_OCR_VOLTAGE_ALL 0xFF8000 |
| #define MM4FIFOWORDSIZE 0x80 |
| #define MMC_RESPONSE_R1B_TIMEOUT 0x100 |
| |
| // device context for MMC API, containing anything needed to operate on |
| // this API. It is always first parameter for all APIs. |
| typedef struct |
| { |
| P_MM4_SDMMC_T pMMC4Reg; // MMC1 register base |
| } MM4_SDMMC_CONTEXT_T, *P_MM4_SDMMC_CONTEXT_T; |
| |
| //////////////////////ADMA DESCRIPTOR related//////////////////////////////// |
| //max no. of blocks transferrable by an ADMA descriptor |
| #define MAX_TRANS_BLKS_ADMA_DESC 127 |
| |
| //Max no of ADMA descriptors that define the max size of chunk of an image |
| #define NO_ADMA_TX_DESCS 260 // 16MB / 127 / 512B = 258 |
| |
| |
| typedef enum |
| { |
| INVALID_DESC = 0, |
| VALID_DESC = 1, |
| }DESC_VAL_INVAL; |
| |
| typedef enum |
| { |
| NOT_LAST_DESC = 0, |
| LAST_DESC = 1, |
| }END_DESC; |
| |
| typedef enum |
| { |
| NO_DMA_INT = 0, |
| DMA_INT = 1, |
| }DMA_INT_EN; |
| |
| typedef enum |
| { |
| NO_OP = 0, |
| RSVD = 1, |
| TRANSFER = 2, |
| LINK = 3, |
| }ATTRIBUTES; |
| |
| typedef struct |
| { |
| unsigned int desc_val_inval :1; |
| unsigned int end_desc :1; |
| unsigned int dma_int_en :1; |
| unsigned int Rsvd0 :1; |
| unsigned int attr :2; |
| unsigned int Rsvd :10; |
| unsigned int Length :16; |
| unsigned int Address :32; |
| } ADMA_DESCRIPTOR, *P_ADMA_DESCRIPTOR; |
| //////////////////////////////ADMA//////////////////////////////// |
| |
| #define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ |
| #define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ |
| #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ |
| /* DDR mode @1.8V or 3V I/O */ |
| #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ |
| /* DDR mode @1.2V I/O */ |
| #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V | EXT_CSD_CARD_TYPE_DDR_1_2V) |
| #define EXT_CSD_CARD_TYPE_SDR_200_1_8V (1<<4) /* Card can run at 200MHz */ |
| /* SDR mode @1.8V I/O */ |
| #define EXT_CSD_CARD_TYPE_SDR_200_1_2V (1<<5) /* Card can run at 200MHz */ |
| /* SDR mode @1.2V I/O */ |
| |
| typedef enum |
| { |
| SDR_1 = 0, // 1 bit data bus |
| SDR_4 = 1, // 4 bit data bus |
| SDR_8 = 2, // 8 bit data bus |
| DDR_4 = 5, // 4 bit data bus (dual data rate) |
| DDR_8 = 6, // 8 bit data bus (dual data rate) |
| }BUS_Width; |
| |
| //Function Prototypes |
| void MMC4StopInternalBusClock(P_MM4_SDMMC_CONTEXT_T pContext); |
| void MMC4StartInternalBusClock(P_MM4_SDMMC_CONTEXT_T pContext); |
| void MMC4StartBusClock(P_MM4_SDMMC_CONTEXT_T pContext); |
| void MMC4StopBusClock (P_MM4_SDMMC_CONTEXT_T pContext); |
| void MMC4SetBusRate(P_MM4_SDMMC_CONTEXT_T pContext, UINT_T rate); |
| void MMC4SelectUHSMode(P_MM4_SDMMC_CONTEXT_T pContext, UINT8_T mode); |
| void MMC4SetTXIntCLKEnable(P_MM4_SDMMC_CONTEXT_T pContext); |
| void MMC4SetTXConfig(P_MM4_SDMMC_CONTEXT_T pContext); |
| void MMC4SetRXConfig(P_MM4_SDMMC_CONTEXT_T pContext); |
| void MMC4EnableDisableIntSources(P_MM4_SDMMC_CONTEXT_T pContext, UINT8_T Desire); |
| void MMC4SetDataTimeout(P_MM4_SDMMC_CONTEXT_T pContext, UINT8_T CounterValue); |
| void MMC4CMDSWReset(P_MM4_SDMMC_CONTEXT_T pContext); |
| void MMC4DataSWReset(P_MM4_SDMMC_CONTEXT_T pContext); |
| void MMC4FullSWReset(P_MM4_SDMMC_CONTEXT_T pContext); |
| void MMC4SendDataCommand(P_MM4_SDMMC_CONTEXT_T pContext, |
| UINT_T Cmd, |
| UINT_T Argument, |
| UINT_T BlockType, |
| UINT_T DataDirection, |
| UINT_T ResType, |
| UINT_T DMAMode, |
| UINT_T AutoCmd23En); |
| |
| void MMC4SendDataCommandNoAuto12(P_MM4_SDMMC_CONTEXT_T pContext, |
| UINT_T Cmd, |
| UINT_T Argument, |
| UINT_T BlockType, |
| UINT_T DataDirection, |
| UINT_T ResType, |
| UINT_T DMAMode, |
| UINT_T Blk_Cnt_Enable); |
| |
| void MMC4SendSetupCommand(P_MM4_SDMMC_CONTEXT_T pContext, |
| UINT_T Cmd, |
| UINT_T CmdType, |
| UINT_T Argument, |
| UINT_T ResType); |
| #endif |