| /****************************************************************************** |
| * |
| * (C)Copyright 2005 - 2008 Marvell. All Rights Reserved. |
| * |
| * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL. |
| * The copyright notice above does not evidence any actual or intended |
| * publication of such source code. |
| * This Module contains Proprietary Information of Marvell and should be |
| * treated as Confidential. |
| * The information in this file is provided for the exclusive use of the |
| * licensees of Marvell. |
| * Such users have the right to use, modify, and incorporate this code into |
| * products for purposes authorized by the license agreement provided they |
| * include this notice and the associated copyright notice with any such |
| * product. |
| * The information in this file is provided "AS IS" without warranty. |
| * |
| ******************************************************************************/ |
| |
| /*********************************************************** |
| * SPIFlash.h |
| * This is the header file for the SPIFlash driver. |
| * |
| * Revision History: |
| * 5/2/07 - initial draft |
| ************************************************************/ |
| #ifndef __SPI_NAND_H__ |
| #define __SPI_NAND_H__ |
| |
| |
| |
| #include "Typedef.h" |
| #include "Flash.h" |
| #include "SSP.h" |
| #include "predefines.h" |
| #include "platform_interrupts.h" |
| #include "xllp_dmac.h" |
| |
| /* |
| * SPI Command Set |
| */ |
| #define SN_WRITE_ENABLE 0x06 |
| #define SN_WRITE_DISABLE 0x04 |
| #define SN_GET_FEATURES 0x0F |
| #define SN_SET_FEATURES 0x1F |
| #define SN_CACHE_LOAD 0x13 |
| #define SN_CACHE_READ 0x03 |
| #define SN_READ_ID 0x9F |
| #define SN_PROGRAM_LOAD 0x02 |
| #define SN_PROGRAM_EXECUTE 0x10 |
| #define SN_BLOCK_ERASE 0xD8 |
| #define SN_RESET 0xFF |
| |
| /* |
| * SPI NAND Feature Types |
| */ |
| |
| typedef enum |
| { |
| SN_PROTECTION = 0xA0, |
| SN_FEATURE = 0xB0, |
| SN_STATUS = 0xC0 |
| } SN_Feature_E; |
| |
| // |
| // GigaDevice GD5F1GQ4RAYIG: protection register 0xa0 |
| // |
| // 7 6 5 4 3 2 1 0 |
| // +------+------+------+------+------+------+------+------+ |
| // | BRWD | Rerd | BP2 | BP1 | BP0 | INV | CMP |Rerd | |
| // +------+------+------+------+------+------+------+------+ |
| |
| #define GIGA_SPINAND_PROTECTION_Rerd1 BIT_0 // Rserved |
| #define GIGA_SPINAND_PROTECTION_CMP BIT_1 // level of protected blcok |
| #define GIGA_SPINAND_PROTECTION_INV BIT_2 // level of protected blcok |
| #define GIGA_SPINAND_PROTECTION_BP0 BIT_3 // level of protected blcok |
| #define GIGA_SPINAND_PROTECTION_BP1 BIT_4 // level of protected blcok |
| #define GIGA_SPINAND_PROTECTION_BP2 BIT_5 // level of protected blcok |
| #define GIGA_SPINAND_PROTECTION_Rerd BIT_6 // lRserved |
| #define GIGA_SPINAND_PROTECTION_BRWD BIT_7 // block protection lock |
| |
| // |
| // GigaDevice GD5F1GQ4RAYIG: feature register 0xb0 |
| // |
| // 7 6 5 4 3 2 1 0 |
| // +-------+------+------+------+------+------+------+------+ |
| // |OTP_PRT|OTP_EN| Rerd |ECC_EN| Rerd | Rerd | Rerd | QE | |
| // +-------+------+------+------+------+------+------+------+ |
| |
| #define GIGA_SPINAND_FEATURE_QE BIT_0 // quad enable |
| #define GIGA_SPINAND_FEATURE_Rerd3 BIT_1 // reserved |
| #define GIGA_SPINAND_FEATURE_Rerd2 BIT_2 // reserved |
| #define GIGA_SPINAND_FEATURE_Rerd1 BIT_3 // reserved |
| #define GIGA_SPINAND_FEATURE_ECC_EN BIT_4 // ecc enable |
| #define GIGA_SPINAND_FEATURE_Rerd BIT_5 // reserved |
| #define GIGA_SPINAND_FEATURE_OTP_EN BIT_6 // one-time program |
| #define GIGA_SPINAND_FEATURE_OTP_PRT BIT_7 // one-time program |
| |
| // |
| // GigaDevice GD5F1GQ4RAYIG: status register 0xc0 |
| // |
| // 7 6 5 4 3 2 1 0 |
| // +-----+------+------+------+------+------+------+------+ |
| // | Rerd| Rerd |ECCS1 |ECCS0 |P_FAIL|E_FAIL| WEL | OIP | |
| // +-----+------+------+------+------+------+------+------+ |
| |
| #define GIGA_SPINAND_STATUS_OIP BIT_0 // operation in progress |
| #define GIGA_SPINAND_STATUS_WEL BIT_1 // write enable latch |
| #define GIGA_SPINAND_STATUS_E_FAIL BIT_2 // erase fail |
| #define GIGA_SPINAND_STATUS_P_FAIL BIT_3 // program fail |
| #define GIGA_SPINAND_STATUS_ECCS0 BIT_4 // ecc status |
| #define GIGA_SPINAND_STATUS_ECCS1 BIT_5 // ecc status |
| #define GIGA_SPINAND_STATUS_Rerd BIT_6 // reserved |
| #define GIGA_SPINAND_STATUS_Rerd1 BIT_7 // reserved |
| |
| /* |
| * SPI NAND Timeouts (all in MICRO seconds!!) |
| * NOTE: I roughly doubled all the values listed in the specification, as the |
| * core will be running slowly in BootROM and I wanted to avoid any situation |
| * where the operation finished at the edge of the timeout value, but the |
| * slow running core captures the timer value just after timeout |
| */ |
| |
| #define SN_READ_TIMEOUT 0x100 //maximum time to load a page into the cache field |
| #define SN_ERASE_TIMEOUT 0x800 //maximum time for the erase operation |
| #define SN_PROGRAM_TIMEOUT 0x5000 //maximum time for the program operation |
| |
| #define SSP_READ_TIME_OUT 0x80000 //timeout for reading data from cache to internal memory |
| //this is dependent on CPU and DMA clock speeds, NOT the SPI device! |
| |
| /* |
| * SPI NAND: other values |
| */ |
| |
| #define SN_PAGE_SIZE 0x800 //SPI NAND pages are 2KB |
| #define SN_BLOCK_SIZE 0x20000 //SPI NAND blocks are 128KB |
| |
| |
| struct SN_ADDRESS_FIELDS |
| { |
| unsigned int CA :11; // 11 bits of column. there are 12 bits of column, but the highest bit is always 0 |
| unsigned int RA :16; // RA[0:5] - this is the Page address |
| // RA[6:15] - this is the Block Number |
| unsigned int no :5; // unused upper 4 bits |
| }; |
| |
| typedef union |
| { |
| unsigned int value; |
| struct SN_ADDRESS_FIELDS fields; |
| } SN_ADDRESS_FIELD_T; |
| |
| |
| //function definitions |
| UINT_T InitializeSPINAND(UINT8_T FlashNum, FlashBootType_T FlashBootType, UINT8_T* P_DefaultPartitionNum); |
| void SPINAND_ReadID(unsigned char *mid, unsigned char *did); |
| unsigned int SPINAND_Read(unsigned int FlashOffset, unsigned int Buffer, unsigned int Size); |
| void SPINAND_CacheLoad(unsigned int Address); |
| unsigned char SPINAND_GetFeatures(SN_Feature_E feature_type); |
| unsigned char SPINAND_SetFeatures(SN_Feature_E feature_type, unsigned char feature); |
| unsigned int SPINAND_CacheRead_4Bytes(unsigned int Offset, unsigned int Buffer, unsigned int Size); |
| unsigned int SPINAND_CacheRead_1Byte(unsigned int Offset, unsigned int Buffer, unsigned int Size); |
| |
| |
| unsigned int SPINAND_Write(unsigned int FlashOffset, unsigned int Buffer, unsigned int Size); |
| unsigned int SPINAND_ProgramLoad_1Byte(unsigned int Address, unsigned int Buffer, unsigned int Size); |
| unsigned int SPINAND_ProgramLoad_4Bytes(unsigned int Address, unsigned int Buffer, unsigned int Size); |
| void SPINAND_WriteEnable(void); |
| void SPINAND_ProgramExecute(unsigned int Address); |
| unsigned int SPINAND_Erase(unsigned int FlashOffset, unsigned int Size); |
| void SPINAND_BlockErase(unsigned int Address); |
| unsigned int SPINAND_Reset(FlashBootType_T fbt); |
| void SPINAND_UnProtectBlocks(void); |
| UINT_T SPINAND_CheckReady(void); |
| |
| #endif |
| |