marvell/obm/Common/Flash/SPI/NZA3/spi.h

/******************************************************************************
 *
 *  (C)Copyright 2005 - 2012 Marvell. All Rights Reserved.
 *
 *  THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL.
 *  The copyright notice above does not evidence any actual or intended
 *  publication of such source code.
 *  This Module contains Proprietary Information of Marvell and should be
 *  treated as Confidential.
 *  The information in this file is provided for the exclusive use of the
 *  licensees of Marvell.
 *  Such users have the right to use, modify, and incorporate this code into
 *  products for purposes authorized by the license agreement provided they
 *  include this notice and the associated copyright notice with any such
 *  product.
 *  The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/
#ifndef __SPI_H__
#define __SPI_H__

#include "Typedef.h"
#include "Flash.h"
#include "SSP.h"
#include "predefines.h"
#include "GPIO.h"
#include "PlatformConfig.h"

#define DEFAULT_TIMEOUT   			3000
#define DEFAULT_WAIT_TIME 			1000

#define WRITE_SIZE (256)
#define SIZE_4KB	(0x1000)

/*
* SSP Register locations.
*
* Note:  SSP_BASE_FOR_SPI set in platform_config.h
*/

#define SSP_CR0	((volatile int *) (SSP_BASE_FOR_SPI+SSP_SSCR0))	// SSP Control Register 0
#define SSP_CR1	((volatile int *) (SSP_BASE_FOR_SPI+SSP_SSCR1))	// SSP Control Register 1
#define SSP_SR	((volatile int *) (SSP_BASE_FOR_SPI+SSP_SSSR))	// SSP Status Register
#define SSP_DR	((volatile int *) (SSP_BASE_FOR_SPI+SSP_SSDR))	// SSP Data Write/Read Register
#define SSP_TO	((volatile int *) (SSP_BASE_FOR_SPI+SSP_SSTO))	// SSP time out register
#define SSP_SP	((volatile int *) (SSP_BASE_FOR_SPI+SSP_SSPSP))	// SSP Serial Protocol Register

//Control Register special values
#define SSP_CR0_INITIAL 	(0x7)
#define SSP_CR0_SSE			SSP_SSCR0_SSE
#define SSP_CR0_FPCKE		SSP_SSCR0_FPCKE
#define SSP_CR0_DSS_32		SSP_SSCR0_EDSS | 0xF
#define SSP_CR0_DSS_24		SSP_SSCR0_EDSS | 0x7
#define SSP_CR0_DSS_16		0x0000000F
#define SSP_CR0_DSS_8		0x00000007

#define SSP_CR1_INITIAL 	SSP_SSCR1_TTELP | SSP_SSCR1_TTE
#define SSP_CR1_RWOT		SSP_SSCR1_RWOT

#define SSP_SSSR_TFL			0xF00       // BIT 11:8 --Transmit FIFO Level, when it's 0x0, TXFIFO is emptry or full.

//limited for timing and stack concerns (see SPI_page_write routine)
#define SSP_READ_TIME_OUT_MILLI		0x2000
#define SSP_READ_DMA_DESC			0x10	//total RX descriptors
#define SSP_READ_DMA_SIZE			0x1ff8	//bytes per descriptor
#define SSP_MAX_TX_SIZE_WORDS		64
#define SSP_MAX_TX_SIZE_BYTES		SSP_MAX_TX_SIZE_WORDS << 2


#define GPIO_CS_BIT   25 /* SPI_CS: using GPIO025, 25%32=25 */
#define	pGPIO_LR  	(volatile int *)(GPIO0_BASE + GPIO_PLR)  //Pin level. set 0
#define	pGPIO_DR  	(volatile int *)(GPIO0_BASE + GPIO_PDR)  //Direction. set 0
#define	pGPIO_SR  	(volatile int *)(GPIO0_BASE + GPIO_PSR)  //Set. set 0
#define	pGPIO_CR  	(volatile int *)(GPIO0_BASE + GPIO_PCR)  //Clear. set 0
#define	pGPIO_SDR 	(volatile int *)(GPIO0_BASE + GPIO_SDR)  //Bit set. set 0

#define GPIO_CS_SET    (1<< GPIO_CS_BIT)
#define GPIO_CS_CLEAR  (!GPIO_CS_BIT)


void Assert_CS(void);
void Deassert_CS(void);
void ROW_DELAY(UINT_T x);
void SPI_DisableSSP(void);
void SPI_WaitSSPComplete(void);
void SPI_Write_Read(unsigned char *cmd, unsigned char *data, unsigned char len);
void SPI_GetSSPDMAReqNum(UINT_T *tx, UINT_T *rx);

#endif