| /****************************************************************************** |
| * |
| * Name: MCU.h |
| * Project: Aspen ( PXAxxx ) |
| * note: this file derived from the morona equivalent... |
| * Purpose: Testing |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * (C)Copyright 2005 - 2011 Marvell. All Rights Reserved. |
| * |
| * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL. |
| * The copyright notice above does not evidence any actual or intended |
| * publication of such source code. |
| * This Module contains Proprietary Information of Marvell and should be |
| * treated as Confidential. |
| * The information in this file is provided for the exclusive use of the |
| * licensees of Marvell. |
| * Such users have the right to use, modify, and incorporate this code into |
| * products for purposes authorized by the license agreement provided they |
| * include this notice and the associated copyright notice with any such |
| * product. |
| * The information in this file is provided "AS IS" without warranty. |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * This file was automatically generated by reg.pl using * MCU.csv |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * History: |
| * |
| ********* PLEASE INSERT THE CVS HISTORY OF THE PREVIOUS VERSION HERE. ********* |
| *******************************************************************************/ |
| |
| #ifndef __INC_MCU_H |
| #define __INC_MCU_H |
| |
| |
| /* |
| * |
| * THE BASE ADDRESSES |
| * |
| */ |
| |
| /* |
| * |
| * THE REGISTER DEFINES |
| * |
| */ |
| #define MCU_CPU_ID_REV 0x0000 /* 32 bit Memory Controller ID |
| * and Revision Register |
| */ |
| #define MCU_CONFIG_REG_DECODE_ADDR 0x0010 /* 32 bit Configuration Register |
| * Decode Address |
| * Register |
| */ |
| #define MCU_SDRAM_CONFIG_0 0x0020 /* 32 bit SDRAM Configuration |
| * Register 0 |
| */ |
| #define MCU_SDRAM_CONFIG_1 0x0030 /* 32 bit SDRAM Configuration |
| * Register 1 |
| */ |
| #define MCU_SDRAM_TIMING_1 0x0050 /* 32 bit SDRAM Timing Register 1 */ |
| #define MCU_SDRAM_TIMING_2 0x0060 /* 32 bit SDRAM Timing Register 2 */ |
| #define MCU_SDRAM_CONTROL_1 0x0080 /* 32 bit SDRAM Control Register 1 */ |
| #define MCU_SDRAM_CONTROL_2 0x0090 /* 32 bit SDRAM Control Register 2 */ |
| #define MCU_SDRAM_CONTROL_3 0x00F0 /* 32 bit SDRAM Control Register 3 */ |
| #define MCU_MMAP0 0x0200 /* 32 bit Memory Address Map |
| * Register 0 |
| */ |
| #define MCU_MMAP1 0x0110 /* 32 bit Memory Address Map |
| * Register 1 |
| */ |
| #define MCU_USER_INITIATED_COMMAND 0x0120 /* 32 bit User Initiated Command |
| * Register |
| */ |
| #define MCU_PHY_CONTROL_3 0x0140 /* 17 bit PHY Control Register 3 */ |
| #define MCU_SDRAM_TIMING_3 0x0190 /* 32 bit SDRAM Timing Register 3 */ |
| #define MCU_SDRAM_CONTROL_4 0x01A0 /* 32 bit SDRAM Control Register 4 */ |
| #define MCU_DRAM_STATUS 0x01B0 /* 32 bit DRAM Status Register */ |
| #define MCU_SDRAM_TIMING_4 0x01C0 /* 32 bit SDRAM Timing Register 4 */ |
| #define MCU_PHY_CONTROL_7 0x01D0 /* 32 bit PHY Control Register 7 */ |
| #define MCU_PHY_CONTROL_8 0x01E0 /* 32 bit PHY Control Register 8 */ |
| #define MCU_PHY_CONTROL_9 0x01F0 /* 32 bit PHY Control Register 9 */ |
| //#define MCU_PHY_CONTROL_10 0x0200 /* 32 bit PHY Control Register 10 */ |
| #define MCU_PHY_CONTROL_13 0x0230 /* 32 bit PHY Control Register 13 */ |
| #define MCU_PHY_CONTROL_14 0x0240 /* 32 bit PHY Control Register 14 */ |
| #define MCU_SDRAM_CONTROL_5 0x0280 /* 32 bit SDRAM Control Register 5 */ |
| #define MCU_MCB_CONTROL_1 0x0510 /* 32 bit MCB Control Register 1 */ |
| #define MCU_MCB_CONTROL_2 0x0520 /* 32 bit MCB Control Register 2 */ |
| #define MCU_MCB_CONTROL_4 0x0540 /* 32 bit MCB Control Register 4 |
| * Register |
| */ |
| #define MCU_SDRAM_TIMING_5 0x0650 /* 32 bit SDRAM Timing Register 5 */ |
| #define MCU_PHY_DLL_CONTROL_1 0x0E10 /* 32 bit PHY DLL Control |
| * Register 1 |
| */ |
| // not in aspen? #define MCU_MMAP2 0x0130 /* 32 bit Memory Address Map Register 2 */ |
| // not in aspen? #define MCU_PHY_DLL_CONTROL_2 0x0E20 /* 32 bit PHY DLL Control Register 2 */ |
| // not in aspen? #define MCU_PHY_DLL_CONTROL_3 0x0E30 /* 32 bit PHY DLL Control Register 3 */ |
| |
| /* |
| * |
| * THE BIT DEFINES |
| * |
| */ |
| /* MCU_CPU_ID_REV 0x0000 Memory Controller ID and Revision |
| * Register |
| */ |
| /* Bit(s) MCU_CPU_ID_REV_RSRV_31_16 reserved */ |
| /* Architecture Version */ |
| #define MCU_CPU_ID_REV_ARCHITECTURE_VERSION_MSK SHIFT12(0xf) |
| #define MCU_CPU_ID_REV_ARCHITECTURE_VERSION_BASE 12 |
| /* Architecture Variant */ |
| #define MCU_CPU_ID_REV_ARCHITECTURE_VARIANT_MSK SHIFT8(0xf) |
| #define MCU_CPU_ID_REV_ARCHITECTURE_VARIANT_BASE 8 |
| /* Revision Number */ |
| #define MCU_CPU_ID_REV_REVISION_NUMBER_MSK SHIFT0(0xff) |
| #define MCU_CPU_ID_REV_REVISION_NUMBER_BASE 0 |
| |
| /* MCU_CONFIG_REG_DECODE_ADDR 0x0010 Configuration Register Decode Address |
| * Register |
| */ |
| /* Config Addr */ |
| #define MCU_CONFIG_REG_DECODE_ADDR_CONFIG_ADDR_MSK SHIFT16(0xffff) |
| #define MCU_CONFIG_REG_DECODE_ADDR_CONFIG_ADDR_BASE 16 |
| /* Signature */ |
| #define MCU_CONFIG_REG_DECODE_ADDR_SIGNATURE_MSK SHIFT0(0xffff) |
| #define MCU_CONFIG_REG_DECODE_ADDR_SIGNATURE_BASE 0 |
| |
| /* MCU_SDRAM_CONFIG_0 0x0020 SDRAM Configuration Register 0 */ |
| /* Bit(s) MCU_SDRAM_CONFIG_0_RSRV_31 reserved */ |
| /* Partial Array Self Refresh for CS0 */ |
| #define MCU_SDRAM_CONFIG_0_PASR0_MSK SHIFT28(0x7) |
| #define MCU_SDRAM_CONFIG_0_PASR0_BASE 28 |
| /* Output Driver Strength of CS0 */ |
| #define MCU_SDRAM_CONFIG_0_ODS0_MSK SHIFT14(0x3) |
| #define MCU_SDRAM_CONFIG_0_ODS0_BASE 14 |
| /* CS0 Bank Number */ |
| #define MCU_SDRAM_CONFIG_0_CS0_BANK_NUMBER_MSK SHIFT12(0x3) |
| #define MCU_SDRAM_CONFIG_0_CS0_BANK_NUMBER_BASE 12 |
| /* CS0 No. of Row */ |
| #define MCU_SDRAM_CONFIG_0_CS0_NO_OF_ROW_MSK SHIFT8(0xf) |
| #define MCU_SDRAM_CONFIG_0_CS0_NO_OF_ROW_BASE 8 |
| /* CS0 No. of Col */ |
| #define MCU_SDRAM_CONFIG_0_CS0_NO_OF_COL_MSK SHIFT4(0xf) |
| #define MCU_SDRAM_CONFIG_0_CS0_NO_OF_COL_BASE 4 |
| /* Bit(s) MCU_SDRAM_CONFIG_0_RSRV_3_0 reserved */ |
| |
| /* MCU_SDRAM_CONFIG_1 0x0030 SDRAM Configuration Register 1 */ |
| /* Bit(s) MCU_SDRAM_CONFIG_1_RSRV_31 reserved */ |
| /* Partial Array Self Refresh for CS1 */ |
| #define MCU_SDRAM_CONFIG_1_PASR1_MSK SHIFT28(0x7) |
| #define MCU_SDRAM_CONFIG_1_PASR1_BASE 28 |
| /* Output Driver Strength of CS1 */ |
| #define MCU_SDRAM_CONFIG_1_ODS1_MSK SHIFT14(0x3) |
| #define MCU_SDRAM_CONFIG_1_ODS1_BASE 14 |
| /* CS1 Bank Number */ |
| #define MCU_SDRAM_CONFIG_1_CS1_BANK_NUMBER_MSK SHIFT12(0x3) |
| #define MCU_SDRAM_CONFIG_1_CS1_BANK_NUMBER_BASE 12 |
| /* CS1 No. of Row */ |
| #define MCU_SDRAM_CONFIG_1_CS1_NO_OF_ROW_MSK SHIFT8(0xf) |
| #define MCU_SDRAM_CONFIG_1_CS1_NO_OF_ROW_BASE 8 |
| /* CS1 No. of Col */ |
| #define MCU_SDRAM_CONFIG_1_CS1_NO_OF_COL_MSK SHIFT4(0xf) |
| #define MCU_SDRAM_CONFIG_1_CS1_NO_OF_COL_BASE 4 |
| /* Bit(s) MCU_SDRAM_CONFIG_1_RSRV_3_0 reserved */ |
| |
| /* MCU_SDRAM_CONFIG_2 0x0040 SDRAM Configuration Register 2 */ |
| |
| /* MCU_SDRAM_TIMING_1 0x0050 SDRAM Timing Register 1 */ |
| /* CASn to CASn Command Delay */ |
| #define MCU_SDRAM_TIMING_1_TCCD_MSK SHIFT29(0x7) |
| #define MCU_SDRAM_TIMING_1_TCCD_BASE 29 |
| /* Internal Read-to-PRECHARGE Delay */ |
| #define MCU_SDRAM_TIMING_1_TRTP_MSK SHIFT26(0x7) |
| #define MCU_SDRAM_TIMING_1_TRTP_BASE 26 |
| /* Internal Write-to-READ Command Delay */ |
| #define MCU_SDRAM_TIMING_1_TWTR_MSK SHIFT22(0xf) |
| #define MCU_SDRAM_TIMING_1_TWTR_BASE 22 |
| /* Active-to-Active (Same Bank) Command */ |
| #define MCU_SDRAM_TIMING_1_TRC_MSK SHIFT16(0x3f) |
| #define MCU_SDRAM_TIMING_1_TRC_BASE 16 |
| /* Auto-Refresh Interval Counter */ |
| #define MCU_SDRAM_TIMING_1_TREFI_MSK SHIFT0(0xffff) |
| #define MCU_SDRAM_TIMING_1_TREFI_BASE 0 |
| |
| /* MCU_SDRAM_TIMING_2 0x0060 SDRAM Timing Register 2 */ |
| /* PRECHARGE Command Period */ |
| #define MCU_SDRAM_TIMING_2_TRP_MSK SHIFT28(0xf) |
| #define MCU_SDRAM_TIMING_2_TRP_BASE 28 |
| /* Active Bank A to Active Bank B Command */ |
| #define MCU_SDRAM_TIMING_2_TRRD_MSK SHIFT24(0xf) |
| #define MCU_SDRAM_TIMING_2_TRRD_BASE 24 |
| /* ACTIVE-to-READ or WRITE Delay */ |
| #define MCU_SDRAM_TIMING_2_TRCD_MSK SHIFT20(0xf) |
| #define MCU_SDRAM_TIMING_2_TRCD_BASE 20 |
| /* Bit(s) MCU_SDRAM_TIMING_2_RSRV_15_13 reserved */ |
| /* REFRESH-to-ACTIVE or REFRESH-to-REFRESH Interval */ |
| #define MCU_SDRAM_TIMING_2_TRFC_MSK SHIFT4(0x1ff) |
| #define MCU_SDRAM_TIMING_2_TRFC_BASE 4 |
| /* Bit(s) MCU_SDRAM_TIMING_2_RSRV_3 reserved */ |
| /* Load Mode Command Cycle */ |
| #define MCU_SDRAM_TIMING_2_TMRD_MSK SHIFT0(0x7) |
| #define MCU_SDRAM_TIMING_2_TMRD_BASE 0 |
| |
| /* MCU_SDRAM_CONTROL_1 0x0080 SDRAM Control Register 1 */ |
| /* Auto-power-saving Enable */ |
| #define MCU_SDRAM_CONTROL_1_APS_EN BIT_31 |
| /* Auto-power-saving Type */ |
| #define MCU_SDRAM_CONTROL_1_APS_TYPE_MSK SHIFT28(0x7) |
| #define MCU_SDRAM_CONTROL_1_APS_TYPE_BASE 28 |
| /* Auto-power-saving Value */ |
| #define MCU_SDRAM_CONTROL_1_APS_VALUE_MSK SHIFT16(0xfff) |
| #define MCU_SDRAM_CONTROL_1_APS_VALUE_BASE 16 |
| /* Bit(s) MCU_SDRAM_CONTROL_1_RSRV_15 reserved */ |
| /* Auto-clock-stop Exit Delay */ |
| #define MCU_SDRAM_CONTROL_1_ACS_EXIT_DLY_MSK SHIFT12(0x7) |
| #define MCU_SDRAM_CONTROL_1_ACS_EXIT_DLY_BASE 12 |
| #define MCU_SDRAM_CONTROL_1_DLL_RESET BIT_6 /* DLL Reset */ |
| /* Bit(s) MCU_SDRAM_CONTROL_1_RSRV_5 reserved */ |
| /* Output Enable in DRAM Mode Register */ |
| #define MCU_SDRAM_CONTROL_1_OUTEN BIT_3 |
| /* Bit(s) MCU_SDRAM_CONTROL_1_RSRV_2 reserved */ |
| |
| /* MCU_SDRAM_CONTROL_2 0x0090 SDRAM Control Register 2 */ |
| /* Bit(s) MCU_SDRAM_CONTROL_2_RSRV_31_28 reserved */ |
| /* Auto-refresh Post Enable */ |
| #define MCU_SDRAM_CONTROL_2_REF_POSTED_EN BIT_27 |
| /* Auto-refresh Post Maximum */ |
| #define MCU_SDRAM_CONTROL_2_REF_POSTED_MAX_MSK SHIFT24(0x7) |
| #define MCU_SDRAM_CONTROL_2_REF_POSTED_MAX_BASE 24 |
| /* Bit(s) MCU_SDRAM_CONTROL_2_RSRV_23_21 reserved */ |
| /* RDIMM Mode */ |
| #define MCU_SDRAM_CONTROL_2_RDIMM_MODE BIT_5 |
| /* Auto-precharge Enable */ |
| #define MCU_SDRAM_CONTROL_2_APRECHARGE BIT_4 |
| /* Bit(s) MCU_SDRAM_CONTROL_2_RSRV_3_2 reserved */ |
| /* Test Mode */ |
| #define MCU_SDRAM_CONTROL_2_TEST_MODE BIT_0 |
| |
| /* MCU_SDRAM_PAD_CALIBRATION 0x00A0 SDRAM Pad Calibration Register */ |
| |
| /* MCU_MASTER_OUT_OF_RANGE 0x00D0 Master Out of Range Register */ |
| |
| /* MCU_SDRAM_CONTROL_3 0x00F0 SDRAM Control Register 3 */ |
| /* Early Command Enable */ |
| #define MCU_SDRAM_CONTROL_3_DC_EARLY_CMD_EN BIT_31 |
| /* Flop Request Enable */ |
| #define MCU_SDRAM_CONTROL_3_DC_MC_FLOP_REQ_EN BIT_30 |
| /* Bit(s) MCU_SDRAM_CONTROL_3_RSRV_29_20 reserved */ |
| /* Master 3 Early Write Enable */ |
| #define MCU_SDRAM_CONTROL_3_MASTR3_EARLY_WRITE_EN BIT_19 |
| /* Master 2 Early Write Enable */ |
| #define MCU_SDRAM_CONTROL_3_MSTR2_EARLY_WRITE_EN BIT_18 |
| /* Master 3 Fast Write Enable */ |
| #define MCU_SDRAM_CONTROL_3_MSTR3_FAST_WRITE_EN BIT_17 |
| /* Master 2 Fast Write Enable */ |
| #define MCU_SDRAM_CONTROL_3_MSTR2_FAST_WRITE_EN BIT_16 |
| /* Bit(s) MCU_SDRAM_CONTROL_3_RSRV_15_12 reserved */ |
| /* Sideband Early Write User Value */ |
| #define MCU_SDRAM_CONTROL_3_SB_EARLY_WRITE_USERVALUE_MSK SHIFT9(0x7) |
| #define MCU_SDRAM_CONTROL_3_SB_EARLY_WRITE_USERVALUE_BASE 9 |
| /* CPU Early Write User Value */ |
| #define MCU_SDRAM_CONTROL_3_CPU_EARLY_WRITE_USERVALUE_MSK SHIFT6(0x7) |
| #define MCU_SDRAM_CONTROL_3_CPU_EARLY_WRITE_USERVALUE_BASE 6 |
| /* Sideband Early Write User */ |
| #define MCU_SDRAM_CONTROL_3_SB_EARLY_WRITE_USER BIT_5 |
| /* CPU Early Write User */ |
| #define MCU_SDRAM_CONTROL_3_CPU_EARLY_WRITE_USER BIT_4 |
| /* Sideband Fast Write Enable */ |
| #define MCU_SDRAM_CONTROL_3_SB_FAST_WRITE_EN BIT_1 |
| /* CPU Fast Write Enable */ |
| #define MCU_SDRAM_CONTROL_3_CPU_FAST_WRITE_EN BIT_0 |
| |
| /* MMU_MMAP0 0x0100 Memory Address Map Register 0 */ |
| #define MMU_MMAP0_START_ADDRESS_MSK SHIFT23(0x1ff) /* Start Address */ |
| #define MMU_MMAP0_START_ADDRESS_BASE 23 |
| /* Bit(s) MMU_MMAP0_RSRV_22_20 reserved */ |
| #define MMU_MMAP0_AREA_LENGTH_MSK SHIFT16(0xf) /* Area Length */ |
| #define MMU_MMAP0_AREA_LENGTH_BASE 16 |
| #define MMU_MMAP0_ADDRESS_MASK_MSK SHIFT7(0x1ff) /* Address Mask */ |
| #define MMU_MMAP0_ADDRESS_MASK_BASE 7 |
| /* Bit(s) MMU_MMAP0_RSRV_6_1 reserved */ |
| #define MMU_MMAP0_VALID BIT_0 /* Valid */ |
| |
| /* MMU_MMAP1 0x0110 Memory Address Map Register 1 */ |
| #define MMU_MMAP1_START_ADDRESS_MSK SHIFT23(0x1ff) /* Start Address */ |
| #define MMU_MMAP1_START_ADDRESS_BASE 23 |
| /* Bit(s) MMU_MMAP1_RSRV_22_20 reserved */ |
| #define MMU_MMAP1_AREA_LENGTH_MSK SHIFT16(0xf) /* Area Length */ |
| #define MMU_MMAP1_AREA_LENGTH_BASE 16 |
| #define MMU_MMAP1_ADDRESS_MASK_MSK SHIFT7(0x1ff) /* Address Mask */ |
| #define MMU_MMAP1_ADDRESS_MASK_BASE 7 |
| /* Bit(s) MMU_MMAP1_RSRV_6_1 reserved */ |
| #define MMU_MMAP1_VALID BIT_0 /* Valid */ |
| |
| /* MCU_USER_INITIATED_COMMAND 0x0120 User Initiated Command Register */ |
| /* Bit(s) MCU_USER_INITIATED_COMMAND_RSRV_31 reserved */ |
| /* Bit(s) MCU_USER_INITIATED_COMMAND_RSRV_30 reserved */ |
| /* Bit(s) MCU_USER_INITIATED_COMMAND_RSRV_27 reserved */ |
| /* Chip Select 2 */ |
| #define MCU_USER_INITIATED_COMMAND_CHIP_SELECT_2 BIT_26 |
| /* Chip Select 1 */ |
| #define MCU_USER_INITIATED_COMMAND_CHIP_SELECT_1 BIT_25 |
| /* Chip Select 0 */ |
| #define MCU_USER_INITIATED_COMMAND_CHIP_SELECT_0 BIT_24 |
| /* Load Mode 3 */ |
| #define MCU_USER_INITIATED_COMMAND_USER_LMR3_REQ BIT_11 |
| /* Load Mode 2 */ |
| #define MCU_USER_INITIATED_COMMAND_USER_LMR2_REQ BIT_10 |
| /* Load Mode 1 */ |
| #define MCU_USER_INITIATED_COMMAND_USER_LMR1_REQ BIT_9 |
| /* Load Mode 0 */ |
| #define MCU_USER_INITIATED_COMMAND_USER_LMR0_REQ BIT_8 |
| /* Self Refresh */ |
| #define MCU_USER_INITIATED_COMMAND_USER_SR_REQ_MSK SHIFT6(0x3) |
| #define MCU_USER_INITIATED_COMMAND_USER_SR_REQ_BASE 6 |
| /* Precharge Power Down State */ |
| #define MCU_USER_INITIATED_COMMAND_USER_PRE_PS_REQ BIT_5 |
| /* Active Power-Down State */ |
| #define MCU_USER_INITIATED_COMMAND_USER_ACT_PS_REQ BIT_4 |
| /* Start SDRAM Initialization */ |
| #define MCU_USER_INITIATED_COMMAND_SDRAM_INIT_REQ BIT_0 |
| |
| /* MCU_MMAP2 0x0130 Memory Address Map Register 2 */ |
| /* MCB2 Request Queue 4 Enable */ |
| #define MCU_MMAP2_MCB2_REQ_QU4_EN BIT_6 |
| /* MCB1 Request Queue 4 Enable */ |
| #define MCU_MMAP2_MCB1_REQ_QU4_EN BIT_5 |
| /* Software-Controlled DL Update Enable Pulse */ |
| #define MCU_MMAP2_SW_DL_UPDATE_ENABLE BIT_4 |
| |
| /* MCU_PHY_CONTROL_3 0x0140 PHY Control Register 3 */ |
| /* Bit(s) MCU_PHY_CONTROL_3_RSRV_16 reserved */ |
| |
| /* MCU_SDRAM_TIMING_3 0x0190 SDRAM Timing Register 3 */ |
| /* Bit(s) MCU_SDRAM_TIMING_3_RSRV_27 reserved */ |
| #define MCU_SDRAM_TIMING_3_TXSNR_8 BIT_26 /* tXSNR_8 */ |
| /* Bit(s) MCU_SDRAM_TIMING_3_RSRV_4_3 reserved */ |
| |
| /* MCU_SDRAM_CONTROL_4 0x01A0 SDRAM Control Register 4 */ |
| #define MCU_SDRAM_CONTROL_4_FAST_BANK BIT_29 /* Fast Bank */ |
| /* Bit(s) MCU_SDRAM_CONTROL_4_RSRV_28_25 reserved */ |
| #define MCU_SDRAM_CONTROL_4_RDQS_EN BIT_17 /* RDQS Enable */ |
| /* DDR Data Bus Width */ |
| #define MCU_SDRAM_CONTROL_4_DATA_WIDTH_MSK SHIFT0(0x3) |
| #define MCU_SDRAM_CONTROL_4_DATA_WIDTH_BASE 0 |
| |
| /* MCU_DRAM_STATUS 0x01B0 DRAM Status Register */ |
| /* Initialization Done */ |
| #define MCU_DRAM_STATUS_INIT_DONE BIT_0 |
| |
| /* MCU_SDRAM_TIMING_4 0x01C0 SDRAM Timing Register 4 */ |
| /* Bit(s) MCU_SDRAM_TIMING_4_RSRV_31 reserved */ |
| #define MCU_SDRAM_TIMING_4_TCKE_MSK SHIFT28(0x7) /* tCKE */ |
| #define MCU_SDRAM_TIMING_4_TCKE_BASE 28 |
| /* Read Command to Write Command Delay */ |
| #define MCU_SDRAM_TIMING_4_TRWD_EXT_DLY_MSK SHIFT17(0x7) |
| #define MCU_SDRAM_TIMING_4_TRWD_EXT_DLY_BASE 17 |
| |
| /* MCU_PHY_CONTROL_7 0x01D0 PHY Control Register 7 */ |
| /* Bit(s) MCU_PHY_CONTROL_7_RSRV_31_30 reserved */ |
| /* PHY QS Vref Select */ |
| #define MCU_PHY_CONTROL_7_PHY_QS_VREF_SEL_MSK SHIFT28(0x3) |
| #define MCU_PHY_CONTROL_7_PHY_QS_VREF_SEL_BASE 28 |
| #define MCU_PHY_CONTROL_7_PHY_DQ_ZPTRM_MSK SHIFT16(0xf) /* PHY DQ ZPTRM */ |
| #define MCU_PHY_CONTROL_7_PHY_DQ_ZPTRM_BASE 16 |
| #define MCU_PHY_CONTROL_7_PHY_DQ_ZNTRM_MSK SHIFT12(0xf) /* PHY DQ ZNTRM */ |
| #define MCU_PHY_CONTROL_7_PHY_DQ_ZNTRM_BASE 12 |
| #define MCU_PHY_CONTROL_7_PHY_DQ_ZNR_MSK SHIFT8(0xf) /* PHY DQ ZNR */ |
| #define MCU_PHY_CONTROL_7_PHY_DQ_ZNR_BASE 8 |
| #define MCU_PHY_CONTROL_7_PHY_DQ_ZPR_MSK SHIFT4(0xf) /* PHY DQ ZPR */ |
| #define MCU_PHY_CONTROL_7_PHY_DQ_ZPR_BASE 4 |
| /* PHY DQ Vref Select */ |
| #define MCU_PHY_CONTROL_7_PHY_DQ_VREF_SEL_MSK SHIFT2(0x3) |
| #define MCU_PHY_CONTROL_7_PHY_DQ_VREF_SEL_BASE 2 |
| #define MCU_PHY_CONTROL_7_PHY_DQ_ZD BIT_1 /* PHY DQ ZD */ |
| |
| /* MCU_PHY_CONTROL_8 0x01E0 PHY Control Register 8 */ |
| /* Bit(s) MCU_PHY_CONTROL_8_RSRV_31_28 reserved */ |
| /* PHY ADCM ZPTRM */ |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_ZPTRM_MSK SHIFT16(0xf) |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_ZPTRM_BASE 16 |
| /* PHY ADCM ZNTRM */ |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_ZNTRM_MSK SHIFT12(0xf) |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_ZNTRM_BASE 12 |
| /* PHY ADCM ZNR */ |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_ZNR_MSK SHIFT8(0xf) |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_ZNR_BASE 8 |
| /* PHY ADCM ZPR */ |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_ZPR_MSK SHIFT4(0xf) |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_ZPR_BASE 4 |
| /* PHY ADCM VREF Select */ |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_VREF_SEL_MSK SHIFT2(0x3) |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_VREF_SEL_BASE 2 |
| /* PHY ADCM ZD */ |
| #define MCU_PHY_CONTROL_8_PHY_ADCM_ZD BIT_1 |
| |
| /* MCU_PHY_CONTROL_9 0x01F0 PHY Control Register 9 */ |
| /* PHY DQ Receiver Type */ |
| #define MCU_PHY_CONTROL_9_PHY_DQ_RCVTYPE BIT_31 |
| /* PHY QS Receiver Type */ |
| #define MCU_PHY_CONTROL_9_PHY_QS_RCVTYPE BIT_30 |
| #define MCU_PHY_CONTROL_9_PHY_DQ_RCVEP_MSK SHIFT27(0x7) /* PHY DQ RCVEP */ |
| #define MCU_PHY_CONTROL_9_PHY_DQ_RCVEP_BASE 27 |
| #define MCU_PHY_CONTROL_9_PHY_DQ_RCVEN_MSK SHIFT24(0x7) /* PHY DQ RCVEN */ |
| #define MCU_PHY_CONTROL_9_PHY_DQ_RCVEN_BASE 24 |
| /* Bit(s) MCU_PHY_CONTROL_9_RSRV_23_22 reserved */ |
| #define MCU_PHY_CONTROL_9_PHY_CK_ZD BIT_21 /* PHY CK ZD */ |
| /* Bit(s) MCU_PHY_CONTROL_9_RSRV_20 reserved */ |
| /* PHY WCK DQ DLY */ |
| #define MCU_PHY_CONTROL_9_PHY_WCK_DQ_DLY_MSK SHIFT17(0x7) |
| #define MCU_PHY_CONTROL_9_PHY_WCK_DQ_DLY_BASE 17 |
| /* PHY WCK QS DLY */ |
| #define MCU_PHY_CONTROL_9_PHY_WCK_QS_DLY_MSK SHIFT14(0x7) |
| #define MCU_PHY_CONTROL_9_PHY_WCK_QS_DLY_BASE 14 |
| /* PHY WCK AC DLY */ |
| #define MCU_PHY_CONTROL_9_PHY_WCK_AC_DLY_MSK SHIFT11(0x7) |
| #define MCU_PHY_CONTROL_9_PHY_WCK_AC_DLY_BASE 11 |
| /* PHY WCK CK DLY */ |
| #define MCU_PHY_CONTROL_9_PHY_WCK_CK_DLY_MSK SHIFT8(0x7) |
| #define MCU_PHY_CONTROL_9_PHY_WCK_CK_DLY_BASE 8 |
| #define MCU_PHY_CONTROL_9_PHY_CK_ZNR_MSK SHIFT4(0xf) /* PHY CK ZNR */ |
| #define MCU_PHY_CONTROL_9_PHY_CK_ZNR_BASE 4 |
| #define MCU_PHY_CONTROL_9_PHY_CK_ZPR_MSK SHIFT0(0xf) /* PHY CK ZPR */ |
| #define MCU_PHY_CONTROL_9_PHY_CK_ZPR_BASE 0 |
| |
| /* MCU_PHY_CONTROL_10 0x0200 PHY Control Register 10 */ |
| /* Bit(s) MCU_PHY_CONTROL_10_RSRV_31_22 reserved */ |
| /* Calibration Interval */ |
| #define MCU_PHY_CONTROL_10_PAD_CAL_INTERVAL_MSK SHIFT20(0x3) |
| #define MCU_PHY_CONTROL_10_PAD_CAL_INTERVAL_BASE 20 |
| /* Calibration Auto Select */ |
| #define MCU_PHY_CONTROL_10_PAD_CAL_AUTO_SEL_MSK SHIFT17(0x7) |
| #define MCU_PHY_CONTROL_10_PAD_CAL_AUTO_SEL_BASE 17 |
| /* Pad Calibration Auto */ |
| #define MCU_PHY_CONTROL_10_PAD_CAL_AUTO BIT_16 |
| /* Bit(s) MCU_PHY_CONTROL_10_RSRV_15_14 reserved */ |
| /* Read FIFO Depth */ |
| #define MCU_PHY_CONTROL_10_READ_FIFO_DEPTH_MSK SHIFT12(0x3) |
| #define MCU_PHY_CONTROL_10_READ_FIFO_DEPTH_BASE 12 |
| /* Bit(s) MCU_PHY_CONTROL_10_RSRV_11 reserved */ |
| /* Write DQSB One */ |
| #define MCU_PHY_CONTROL_10_WRITE_DQSB_ONE BIT_10 |
| /* External Request PHY Sync Disable */ |
| #define MCU_PHY_CONTROL_10_EXT_REQ_PHY_SYNC_DIS BIT_9 |
| /* Write DQSB Enable */ |
| #define MCU_PHY_CONTROL_10_WRITE_DQSB_ENABLE BIT_8 |
| /* Memory Controller Internal PHY QSP Pulldown */ |
| #define MCU_PHY_CONTROL_10_MC_QSP_PD BIT_3 |
| /* Memory Controller Internal PHY DQ Pulldown */ |
| #define MCU_PHY_CONTROL_10_MC_DQ_PD BIT_2 |
| /* Memory Controller Internal PHY Clock Pulldown */ |
| #define MCU_PHY_CONTROL_10_MC_CK_PD BIT_1 |
| /* Memory Controller Internal PHY Address/Command Pulldown */ |
| #define MCU_PHY_CONTROL_10_MC_AC_PD BIT_0 |
| |
| /* MCU_PHY_CONTROL_13 0x0230 PHY Control Register 13 */ |
| /* DLL Reset Timer */ |
| #define MCU_PHY_CONTROL_13_DLL_RESET_TIMER_MSK SHIFT28(0xf) |
| #define MCU_PHY_CONTROL_13_DLL_RESET_TIMER_BASE 28 |
| /* DLL Update Stall Memory Controller Disable */ |
| #define MCU_PHY_CONTROL_13_DLL_UPDATE_STALL_MC_DIS BIT_27 |
| /* Bit(s) MCU_PHY_CONTROL_13_RSRV_26_25 reserved */ |
| /* DLL Delay Test */ |
| #define MCU_PHY_CONTROL_13_DLL_DELAY_TEST_MSK SHIFT16(0x1ff) |
| #define MCU_PHY_CONTROL_13_DLL_DELAY_TEST_BASE 16 |
| /* Bit(s) MCU_PHY_CONTROL_13_RSRV_15 reserved */ |
| /* DLL Phase Select Bypass */ |
| #define MCU_PHY_CONTROL_13_DLL_PHSEL_BYASS_MSK SHIFT10(0x1f) |
| #define MCU_PHY_CONTROL_13_DLL_PHSEL_BYASS_BASE 10 |
| /* Bit(s) MCU_PHY_CONTROL_13_RSRV_9 reserved */ |
| /* DLL Phase Select */ |
| #define MCU_PHY_CONTROL_13_DLL_PHSEL_MSK SHIFT4(0x1f) |
| #define MCU_PHY_CONTROL_13_DLL_PHSEL_BASE 4 |
| /* Bit(s) MCU_PHY_CONTROL_13_RSRV_3 reserved */ |
| /* DLL Auto Update Enable */ |
| #define MCU_PHY_CONTROL_13_DLL_AUTO_UPDATE_EN BIT_2 |
| /* DLL Test Mode Enable */ |
| #define MCU_PHY_CONTROL_13_DLL_TEST_EN BIT_1 |
| /* DLL Bypass Enable */ |
| #define MCU_PHY_CONTROL_13_DLL_BYPASS_EN BIT_0 |
| |
| /* MCU_PHY_CONTROL_14 0x0240 PHY Control Register 14 */ |
| /* DLL Update Enable */ |
| #define MCU_PHY_CONTROL_14_DLL_UPDATE_EN BIT_30 |
| /* DLL Reset Start */ |
| #define MCU_PHY_CONTROL_14_DLL_RST_START BIT_29 |
| /* Bit(s) MCU_PHY_CONTROL_14_RSRV_28_24 reserved */ |
| #define MCU_PHY_CONTROL_14_PHY_CAL_ZPR_MSK SHIFT20(0xf) /* PHY Cal ZPR */ |
| #define MCU_PHY_CONTROL_14_PHY_CAL_ZPR_BASE 20 |
| #define MCU_PHY_CONTROL_14_PHY_CAL_ZNR_MSK SHIFT16(0xf) /* PHY Cal ZNR */ |
| #define MCU_PHY_CONTROL_14_PHY_CAL_ZNR_BASE 16 |
| /* DLL Delay Out */ |
| #define MCU_PHY_CONTROL_14_DLL_DELAY_OUT_MSK SHIFT8(0xff) |
| #define MCU_PHY_CONTROL_14_DLL_DELAY_OUT_BASE 8 |
| /* Bit(s) MCU_PHY_CONTROL_14_RSRV_7_6 reserved */ |
| /* DLL Clock Test */ |
| #define MCU_PHY_CONTROL_14_DLL_CLK_TST BIT_5 |
| /* Bit(s) MCU_PHY_CONTROL_14_RSRV_4_2 reserved */ |
| #define MCU_PHY_CONTROL_14_PLL_PIN_TST BIT_1 /* PLL Pin Test */ |
| /* PLL Lock Signal */ |
| #define MCU_PHY_CONTROL_14_PLL_PLL_LOCK BIT_0 |
| |
| /* MCU_SDRAM_CONTROL_5 0x0280 SDRAM Control Register 5 */ |
| /* Bit(s) MCU_SDRAM_CONTROL_5_RSRV_31_28 reserved */ |
| /* Master 3 Weight */ |
| #define MCU_SDRAM_CONTROL_5_MASTER_3_WEIGHT_MSK SHIFT24(0xf) |
| #define MCU_SDRAM_CONTROL_5_MASTER_3_WEIGHT_BASE 24 |
| /* Bit(s) MCU_SDRAM_CONTROL_5_RSRV_23_20 reserved */ |
| /* Master 2 Weight */ |
| #define MCU_SDRAM_CONTROL_5_MASTER_2_WEIGHT_MSK SHIFT16(0xf) |
| #define MCU_SDRAM_CONTROL_5_MASTER_2_WEIGHT_BASE 16 |
| /* Bit(s) MCU_SDRAM_CONTROL_5_RSRV_15_12 reserved */ |
| /* Master 1 Weight */ |
| #define MCU_SDRAM_CONTROL_5_MASTER_1_WEIGHT_MSK SHIFT8(0xf) |
| #define MCU_SDRAM_CONTROL_5_MASTER_1_WEIGHT_BASE 8 |
| /* Bit(s) MCU_SDRAM_CONTROL_5_RSRV_7_4 reserved */ |
| /* Master 0 Weight */ |
| #define MCU_SDRAM_CONTROL_5_MASTER_0_WEIGHT_MSK SHIFT0(0xf) |
| #define MCU_SDRAM_CONTROL_5_MASTER_0_WEIGHT_BASE 0 |
| |
| /* MCU_SMR1 0x0310 Shadow Memory Repair Register 1 */ |
| |
| /* MCU_SMR2 0x0320 Shadow Memory Repair Register 2 */ |
| |
| /* MCU_SMR 0x04C0 Shadow Memory Repair Test Mode |
| * Register 0 |
| */ |
| |
| /* MCU_SMR 0x04D0 Shadow Memory Repair Test Mode |
| * Register 1 |
| */ |
| |
| /* MCU_MCB_CONTROL_1 0x0510 MCB Control Register 1 */ |
| /* Bit(s) MCU_MCB_CONTROL_1_RSRV_31_28 reserved */ |
| /* MCB Master 3 Weight */ |
| #define MCU_MCB_CONTROL_1_MCB_MASTER_3_WEIGHT_MSK SHIFT24(0xf) |
| #define MCU_MCB_CONTROL_1_MCB_MASTER_3_WEIGHT_BASE 24 |
| /* Bit(s) MCU_MCB_CONTROL_1_RSRV_23_20 reserved */ |
| /* MCB Master 2 Weight */ |
| #define MCU_MCB_CONTROL_1_MCB_MASTER_2_WEIGHT_MSK SHIFT16(0xf) |
| #define MCU_MCB_CONTROL_1_MCB_MASTER_2_WEIGHT_BASE 16 |
| /* Bit(s) MCU_MCB_CONTROL_1_RSRV_15_12 reserved */ |
| /* MCB Master 1 Weight */ |
| #define MCU_MCB_CONTROL_1_MCB_MASTER_1_WEIGHT_MSK SHIFT8(0xf) |
| #define MCU_MCB_CONTROL_1_MCB_MASTER_1_WEIGHT_BASE 8 |
| /* Bit(s) MCU_MCB_CONTROL_1_RSRV_7_4 reserved */ |
| /* MCB Master 0 Weight */ |
| #define MCU_MCB_CONTROL_1_MCB_MASTER_0_WEIGHT_MSK SHIFT0(0xf) |
| #define MCU_MCB_CONTROL_1_MCB_MASTER_0_WEIGHT_BASE 0 |
| |
| /* MCU_MCB_CONTROL_2 0x0520 MCB Control Register 2 */ |
| /* Bit(s) MCU_MCB_CONTROL_2_RSRV_31_28 reserved */ |
| /* MCB Master 3 Weight */ |
| #define MCU_MCB_CONTROL_2_MCB_MASTER_3_WEIGHT_MSK SHIFT24(0xf) |
| #define MCU_MCB_CONTROL_2_MCB_MASTER_3_WEIGHT_BASE 24 |
| /* Bit(s) MCU_MCB_CONTROL_2_RSRV_23_20 reserved */ |
| /* MCB Master 2 Weight */ |
| #define MCU_MCB_CONTROL_2_MCB_MASTER_2_WEIGHT_MSK SHIFT16(0xf) |
| #define MCU_MCB_CONTROL_2_MCB_MASTER_2_WEIGHT_BASE 16 |
| /* Bit(s) MCU_MCB_CONTROL_2_RSRV_15_12 reserved */ |
| /* MCB Master 1 Weight */ |
| #define MCU_MCB_CONTROL_2_MCB_MASTER_1_WEIGHT_MSK SHIFT8(0xf) |
| #define MCU_MCB_CONTROL_2_MCB_MASTER_1_WEIGHT_BASE 8 |
| /* Bit(s) MCU_MCB_CONTROL_2_RSRV_7_4 reserved */ |
| /* MCB Master 0 Weight */ |
| #define MCU_MCB_CONTROL_2_MCB_MASTER_0_WEIGHT_MSK SHIFT0(0xf) |
| #define MCU_MCB_CONTROL_2_MCB_MASTER_0_WEIGHT_BASE 0 |
| |
| /* MCU_MCB_CONTROL_3 0x0530 MCB Control Register 3 */ |
| |
| /* MCU_MCB_CONTROL_4 0x0540 MCB Control Register 4 Register */ |
| /* Bit(s) MCU_MCB_CONTROL_4_RSRV_31_28 reserved */ |
| /* MCBX Wrap Burst Enable */ |
| #define MCU_MCB_CONTROL_4_MCBX_WRAP_BURST_EN_MSK SHIFT25(0x7) |
| #define MCU_MCB_CONTROL_4_MCBX_WRAP_BURST_EN_BASE 25 |
| /* Bit(s) MCU_MCB_CONTROL_4_RSRV_24 reserved */ |
| /* MCBX Tag Enable */ |
| #define MCU_MCB_CONTROL_4_MCBX_TAG_ENABLE_MSK SHIFT21(0x7) |
| #define MCU_MCB_CONTROL_4_MCBX_TAG_ENABLE_BASE 21 |
| /* Bit(s) MCU_MCB_CONTROL_4_RSRV_20 reserved */ |
| /* MCBX Range Error Enable */ |
| #define MCU_MCB_CONTROL_4_MCBX_RGERR_ENABLE_MSK SHIFT17(0x7) |
| #define MCU_MCB_CONTROL_4_MCBX_RGERR_ENABLE_BASE 17 |
| /* Bit(s) MCU_MCB_CONTROL_4_RSRV_16 reserved */ |
| /* MCBX Page Enable */ |
| #define MCU_MCB_CONTROL_4_MCBX_PAGE_EN_MSK SHIFT13(0x7) |
| #define MCU_MCB_CONTROL_4_MCBX_PAGE_EN_BASE 13 |
| /* Bit(s) MCU_MCB_CONTROL_4_RSRV_12 reserved */ |
| /* MCBX Weighted-Round-Robin Arbitration Enable */ |
| #define MCU_MCB_CONTROL_4_MCBX_WRR_EN_MSK SHIFT9(0x7) |
| #define MCU_MCB_CONTROL_4_MCBX_WRR_EN_BASE 9 |
| /* Bit(s) MCU_MCB_CONTROL_4_RSRV_8 reserved */ |
| /* MCBX Read Enable */ |
| #define MCU_MCB_CONTROL_4_MCBX_RD_EN_MSK SHIFT5(0x7) |
| #define MCU_MCB_CONTROL_4_MCBX_RD_EN_BASE 5 |
| /* Bit(s) MCU_MCB_CONTROL_4_RSRV_4 reserved */ |
| /* MCBX Write Enable */ |
| #define MCU_MCB_CONTROL_4_MCBX_WR_EN_MSK SHIFT1(0x7) |
| #define MCU_MCB_CONTROL_4_MCBX_WR_EN_BASE 1 |
| /* Bit(s) MCU_MCB_CONTROL_4_RSRV_0 reserved */ |
| |
| /* MCU_SDRAM_TIMING_5 0x0650 SDRAM Timing Register 5 */ |
| /* Bit(s) MCU_SDRAM_TIMING_5_RSRV_31_22 reserved */ |
| #define MCU_SDRAM_TIMING_5_TRAS_MSK SHIFT16(0x3f) /* tRAS */ |
| #define MCU_SDRAM_TIMING_5_TRAS_BASE 16 |
| /* Bit(s) MCU_SDRAM_TIMING_5_RSRV_15_10 reserved */ |
| /* Bit(s) MCU_SDRAM_TIMING_5_RSRV_3 reserved */ |
| |
| /* MCU_SDRAM_CONTROL_14 0x07E0 SDRAM Control Register 14 */ |
| |
| /* MCU_PHY_DLL_CONTROL_1 0x0E10 PHY DLL Control Register 1 */ |
| /* Bit(s) MCU_PHY_DLL_CONTROL_1_RSRV_31_25 reserved */ |
| /* DLL 1 Delay Test */ |
| #define MCU_PHY_DLL_CONTROL_1_DLL1_DELAY_TEST_MSK SHIFT16(0x1ff) |
| #define MCU_PHY_DLL_CONTROL_1_DLL1_DELAY_TEST_BASE 16 |
| /* Bit(s) MCU_PHY_DLL_CONTROL_1_RSRV_15 reserved */ |
| /* DLL 1 Phase Select Bypass */ |
| #define MCU_PHY_DLL_CONTROL_1_DLL1_PHSEL_BYASS_MSK SHIFT10(0x1f) |
| #define MCU_PHY_DLL_CONTROL_1_DLL1_PHSEL_BYASS_BASE 10 |
| /* Bit(s) MCU_PHY_DLL_CONTROL_1_RSRV_9 reserved */ |
| /* DLL 1 Phase Select */ |
| #define MCU_PHY_DLL_CONTROL_1_DLL1_PHSEL_MSK SHIFT4(0x1f) |
| #define MCU_PHY_DLL_CONTROL_1_DLL1_PHSEL_BASE 4 |
| /* Bit(s) MCU_PHY_DLL_CONTROL_1_RSRV_3 reserved */ |
| /* DLL 1 Auto Update Enable */ |
| #define MCU_PHY_DLL_CONTROL_1_DLL1_AUTO_UPDATE_EN BIT_2 |
| /* DLL 1 Test Mode Enable */ |
| #define MCU_PHY_DLL_CONTROL_1_DLL1_TEST_EN BIT_1 |
| /* DLL 1 Bypass Enable */ |
| #define MCU_PHY_DLL_CONTROL_1_DLL1_BYPASS_EN BIT_0 |
| |
| /* MCU_PHY_DLL_CONTROL_2 0x0E20 PHY DLL Control Register 2 */ |
| /* Bit(s) MCU_PHY_DLL_CONTROL_2_RSRV_31_25 reserved */ |
| /* DLL 2 Delay Test */ |
| #define MCU_PHY_DLL_CONTROL_2_DLL2_DELAY_TEST_MSK SHIFT16(0x1ff) |
| #define MCU_PHY_DLL_CONTROL_2_DLL2_DELAY_TEST_BASE 16 |
| /* Bit(s) MCU_PHY_DLL_CONTROL_2_RSRV_15 reserved */ |
| /* DLL 2 Phase Select Bypass */ |
| #define MCU_PHY_DLL_CONTROL_2_DLL2_PHSEL_BYASS_MSK SHIFT10(0x1f) |
| #define MCU_PHY_DLL_CONTROL_2_DLL2_PHSEL_BYASS_BASE 10 |
| /* Bit(s) MCU_PHY_DLL_CONTROL_2_RSRV_9 reserved */ |
| /* DLL 2 Phase Select */ |
| #define MCU_PHY_DLL_CONTROL_2_DLL2_PHSEL_MSK SHIFT4(0x1f) |
| #define MCU_PHY_DLL_CONTROL_2_DLL2_PHSEL_BASE 4 |
| /* Bit(s) MCU_PHY_DLL_CONTROL_2_RSRV_3 reserved */ |
| /* DLL 2 Auto Update Enable */ |
| #define MCU_PHY_DLL_CONTROL_2_DLL2_AUTO_UPDATE_EN BIT_2 |
| /* DLL 2 Test Mode Enable */ |
| #define MCU_PHY_DLL_CONTROL_2_DLL2_TEST_EN BIT_1 |
| /* DLL 2 Bypass Enable */ |
| #define MCU_PHY_DLL_CONTROL_2_DLL2_BYPASS_EN BIT_0 |
| |
| /* MCU_PHY_DLL_CONTROL_3 0x0E30 PHY DLL Control Register 3 */ |
| /* Bit(s) MCU_PHY_DLL_CONTROL_3_RSRV_31_25 reserved */ |
| /* DLL 3 Delay Test */ |
| #define MCU_PHY_DLL_CONTROL_3_DLL3_DELAY_TEST_MSK SHIFT16(0x1ff) |
| #define MCU_PHY_DLL_CONTROL_3_DLL3_DELAY_TEST_BASE 16 |
| /* Bit(s) MCU_PHY_DLL_CONTROL_3_RSRV_15 reserved */ |
| /* DLL 3 Phase Select Bypass */ |
| #define MCU_PHY_DLL_CONTROL_3_DLL3_PHSEL_BYASS_MSK SHIFT10(0x1f) |
| #define MCU_PHY_DLL_CONTROL_3_DLL3_PHSEL_BYASS_BASE 10 |
| /* Bit(s) MCU_PHY_DLL_CONTROL_3_RSRV_9 reserved */ |
| /* DLL 3 Phase Select */ |
| #define MCU_PHY_DLL_CONTROL_3_DLL3_PHSEL_MSK SHIFT4(0x1f) |
| #define MCU_PHY_DLL_CONTROL_3_DLL3_PHSEL_BASE 4 |
| /* Bit(s) MCU_PHY_DLL_CONTROL_3_RSRV_3 reserved */ |
| /* DLL 3 Auto Update Enable */ |
| #define MCU_PHY_DLL_CONTROL_3_DLL3_AUTO_UPDATE_EN BIT_2 |
| /* DLL 3 Test Mode Enable */ |
| #define MCU_PHY_DLL_CONTROL_3_DLL3_TEST_EN BIT_1 |
| /* DLL 3 Bypass Enable */ |
| #define MCU_PHY_DLL_CONTROL_3_DLL3_BYPASS_EN BIT_0 |
| |
| |
| |
| /* -------------------- */ |
| |
| |
| #endif /* __INC_MCU_H */ |