| /****************************************************************************** |
| * |
| * Name: SD.h |
| * Project: Hermon-2 |
| * Purpose: Testing |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * (C)Copyright 2005 - 2011 Marvell. All Rights Reserved. |
| * |
| * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL. |
| * The copyright notice above does not evidence any actual or intended |
| * publication of such source code. |
| * This Module contains Proprietary Information of Marvell and should be |
| * treated as Confidential. |
| * The information in this file is provided for the exclusive use of the |
| * licensees of Marvell. |
| * Such users have the right to use, modify, and incorporate this code into |
| * products for purposes authorized by the license agreement provided they |
| * include this notice and the associated copyright notice with any such |
| * product. |
| * The information in this file is provided "AS IS" without warranty. |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * This file was automatically generated by reg.pl using * SD.csv |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * History: |
| * |
| ********* PLEASE INSERT THE CVS HISTORY OF THE PREVIOUS VERSION HERE. ********* |
| *******************************************************************************/ |
| |
| #ifndef __INC_SD_H |
| #define __INC_SD_H |
| |
| #include "predefines.h" |
| |
| /* |
| * |
| * THE BASE ADDRESSES |
| * |
| */ |
| #define SDHC0_1_BASE 0xD4280000 |
| #define SDHC0_2_BASE 0xD4281000 |
| #define SDHC1_1_BASE 0xD427E000 |
| #define SDHC1_2_BASE 0xD427F000 |
| |
| |
| /* |
| * |
| * THE REGISTER DEFINES |
| * |
| */ |
| #define SD_SYS_ADDR_LOW (0x0000) /* 16 bit System |
| * Address |
| * Low |
| * Register |
| */ |
| #define SD_SYS_ADDR_HIGH (0x0002) /* 16 bit System |
| * Address |
| * High |
| * Register |
| */ |
| #define SD_BLOCK_SIZE (0x0004) /* 16 bit Block |
| * Size |
| * Register |
| */ |
| #define SD_BLOCK_COUNT (0x0006) /* 16 bit Block |
| * Count |
| * Register |
| */ |
| #define SD_ARG_LOW (0x0008) /* 16 bit |
| * Argument |
| * Low |
| * Register |
| */ |
| #define SD_ARG_HIGH (0x000A) /* 16 bit |
| * Argument |
| * High |
| * Register |
| */ |
| #define SD_TRANSFER_MODE (0x000C) /* 16 bit |
| * Transfer |
| * Mode |
| * Register |
| */ |
| #define SD_CMD (0x000E) /* 16 bit Command |
| * Register |
| */ |
| #define SD_RESP_0 (0x0010) /* 16 bit |
| * Response |
| * Register |
| * 0 |
| */ |
| #define SD_RESP_1 (0x0012) /* 16 bit |
| * Response |
| * Register |
| * 1 |
| */ |
| #define SD_RESP_2 (0x0014) /* 16 bit |
| * Response |
| * Register |
| * 2 |
| */ |
| #define SD_RESP_3 (0x0016) /* 16 bit |
| * Response |
| * Register |
| * 3 |
| */ |
| #define SD_RESP_4 (0x0018) /* 16 bit |
| * Response |
| * Register |
| * 4 |
| */ |
| #define SD_RESP_5 (0x001A) /* 16 bit |
| * Response |
| * Register |
| * 5 |
| */ |
| #define SD_RESP_6 (0x001C) /* 16 bit |
| * Response |
| * Register |
| * 6 |
| */ |
| #define SD_RESP_7 (0x001E) /* 16 bit |
| * Response |
| * Register |
| * 7 |
| */ |
| #define SD_BUFFER_DATA_PORT_0 (0x0020) /* 16 bit Buffer |
| * Data |
| * Port |
| * 0 |
| * Register |
| */ |
| #define SD_BUFFER_DATA_PORT_1 (0x0022) /* 16 bit Buffer |
| * Data |
| * Port |
| * 1 |
| * Register |
| */ |
| #define SD_PRESENT_STATE_1 (0x0024) /* 16 bit Present |
| * State |
| * Register |
| * 1 |
| */ |
| #define SD_PRESENT_STATE_2 (0x0026) /* 16 bit Present |
| * State |
| * Register |
| * 2 |
| */ |
| #define SD_HOST_CTRL (0x0028) /* 16 bit Host |
| * Control |
| * Register |
| */ |
| #define SD_BLOCK_GAP_CTRL (0x002A) /* 16 bit Block |
| * Gap |
| * Control |
| * Register |
| */ |
| #define SD_CLOCK_CTRL (0x002C) /* 16 bit Clock |
| * Control |
| * Register |
| */ |
| #define SD_TIMEOUT_CTRL_SW_RESET (0x002E) /* 16 bit Timeout |
| * Control/Software |
| * Reset |
| * Register |
| */ |
| #define SD_NORMAL_INT_STATUS (0x0030) /* 16 bit Normal |
| * Interrupt |
| * Status |
| * Register |
| */ |
| #define SD_ERROR_INT_STATUS (0x0032) /* 16 bit Error |
| * Interrupt |
| * Status |
| * Register |
| */ |
| #define SD_NORMAL_INT_STATUS_EN (0x0034) /* 16 bit Normal |
| * Interrupt |
| * Status |
| * Enable |
| * Register |
| */ |
| #define SD_ERROR_INT_STATUS_EN (0x0036) /* 16 bit Error |
| * Interrupt |
| * Status |
| * Enable |
| * Register |
| */ |
| #define SD_NORMAL_INT_STATUS_INT_EN (0x0038) /* 16 bit Normal |
| * Interrupt |
| * Status |
| * Interrupt |
| * Enable |
| * Register |
| */ |
| #define SD_ERROR_INT_STATUS_INT_EN (0x003A) /* 16 bit Error |
| * Interrupt |
| * Status |
| * Interrupt |
| * Enable |
| * Register |
| */ |
| #define SD_AUTO_CMD12_ERROR_STATUS (0x003C) /* 16 bit Auto |
| * CMD12 |
| * Error |
| * Status |
| * Register |
| */ |
| #define SD_CAPABILITIES_1 (0x0040) /* 16 bit |
| * Capabilities |
| * Register |
| * 1 |
| */ |
| #define SD_CAPABILITIES_3 (0x0044) /* 16 bit |
| * Capabilities |
| * Register |
| * 3 |
| */ |
| #define SD_CAPABILITIES_4 (0x0046) /* 16 bit |
| * Capabilities |
| * Register |
| * 4 |
| */ |
| #define SD_MAX_CURRENT_1 (0x0048) /* 16 bit Maximum |
| * Current |
| * Register |
| * 1 |
| */ |
| #define SD_MAX_CURRENT_2 (0x004A) /* 16 bit Maximum |
| * Current |
| * Register |
| * 2 |
| */ |
| #define SD_MAX_CURRENT_3 (0x004C) /* 16 bit Maximum |
| * Current |
| * Register |
| * 3 |
| */ |
| #define SD_MAX_CURRENT_4 (0x004E) /* 16 bit Maximum |
| * Current |
| * Register |
| * 4 |
| */ |
| #define SD_FORCE_EVENT_AUTO_CMD12_ERROR (0x0050) /* 16 bit Force |
| * Event |
| * Auto |
| * cmd12 |
| * Error |
| * Register |
| */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS (0x0052) /* 16 bit Force |
| * Event |
| * for |
| * Error |
| * Status |
| * Register |
| */ |
| #define SD_ADMA_ERROR_STATUS (0x0054) /* 16 bit ADMA |
| * Error |
| * Status |
| * Register |
| */ |
| #define SD_ADMA_SYS_ADDR_1 (0x0058) /* 16 bit ADMA |
| * System |
| * Address |
| * Register |
| * 1 |
| */ |
| #define SD_ADMA_SYS_ADDR_2 (0x005A) /* 16 bit ADMA |
| * System |
| * Address |
| * Register |
| * 2 |
| */ |
| #define SD_ADMA_SYS_ADDR_3 (0x005C) /* 16 bit ADMA |
| * System |
| * Address |
| * Register |
| * 3 |
| */ |
| #define SD_ADMA_SYS_ADDR_4 (0x005E) /* 16 bit ADMA |
| * System |
| * Address |
| * Register |
| * 4 |
| */ |
| #define SD_FIFO_PARAM (0x00E0) /* 16 bit FIFO |
| * Parameters |
| * Register |
| */ |
| #define SD_SPI_MODE (0x00E4) /* 16 bit SPI |
| * Mode |
| * Register |
| */ |
| #define SD_CLOCK_AND_BURST_SIZE_SETUP (0x00E6) /* 16 bit Clock |
| * and |
| * Burst |
| * Size |
| * Setup |
| * Register |
| */ |
| #define SD_CE_ATA_1 (0x00E8) /* 16 bit CE-ATA |
| * Register |
| * 1 |
| */ |
| #define SD_CE_ATA_2 (0x00EA) /* 16 bit CE-ATA |
| * Register |
| * 2 |
| */ |
| #define SD_PAD_IO_SETUP (0x00EC) /* 16 bit PAD I/O |
| * Setup |
| * Register |
| */ |
| #define SD_SLOT_INT_STATUS (0x00FC) /* 16 bit Slot |
| * Interrupt |
| * Status |
| * Register |
| */ |
| #define SD_HOST_CTRL_VER (0x00FE) /* 16 bit Host |
| * Control |
| * Version |
| * Register |
| */ |
| #define SD_RX_CFG_REG (0x0114) /* 32 bit Host |
| * RX |
| * Configuration |
| * Register |
| */ |
| #define SD_TX_CFG_REG (0x0118) /* 32 bit Host |
| * TX |
| * Configuration |
| * Register |
| */ |
| |
| /* |
| * |
| * THE BIT DEFINES |
| * |
| */ |
| /* SD_SYS_ADDR_LOW 0x0000 System Address Low Register */ |
| #define SD_SYS_ADDR_LOW_DMA_ADDR_L_MSK SHIFT0(0xffff) /* DMA Address Low */ |
| #define SD_SYS_ADDR_LOW_DMA_ADDR_L_BASE 0 |
| |
| /* SD_SYS_ADDR_HIGH 0x0002 System Address High Register */ |
| #define SD_SYS_ADDR_HIGH_DMA_ADDR_H_MSK SHIFT0(0xffff) /* DMA Address High */ |
| #define SD_SYS_ADDR_HIGH_DMA_ADDR_H_BASE 0 |
| |
| /* SD_BLOCK_SIZE 0x0004 Block Size Register */ |
| /* Bit(s) SD_BLOCK_SIZE_RSRV_15 reserved */ |
| /* Host DMA Buffer Boundary */ |
| #define SD_BLOCK_SIZE_HOST_DMA_BDRY_MSK SHIFT12(0x7) |
| #define SD_BLOCK_SIZE_HOST_DMA_BDRY_BASE 12 |
| #define SD_BLOCK_SIZE_BLOCK_SIZE_MSK SHIFT0(0xfff) /* Block Size */ |
| #define SD_BLOCK_SIZE_BLOCK_SIZE_BASE 0 |
| |
| /* SD_BLOCK_COUNT 0x0006 Block Count Register */ |
| #define SD_BLOCK_COUNT_BLOCK_COUNT_MSK SHIFT0(0xffff) /* Block Count */ |
| #define SD_BLOCK_COUNT_BLOCK_COUNT_BASE 0 |
| |
| /* SD_ARG_LOW 0x0008 Argument Low Register */ |
| #define SD_ARG_LOW_ARG_L_MSK SHIFT0(0xffff) /* Argument Low */ |
| #define SD_ARG_LOW_ARG_L_BASE 0 |
| |
| /* SD_ARG_HIGH 0x000A Argument High Register */ |
| #define SD_ARG_HIGH_ARG_H_MSK SHIFT0(0xffff) /* Argument High */ |
| #define SD_ARG_HIGH_ARG_H_BASE 0 |
| |
| /* SD_TRANSFER_MODE 0x000C Transfer Mode Register */ |
| /* Bit(s) SD_TRANSFER_MODE_RSRV_15_6 reserved */ |
| /* Multiple Block Select */ |
| #define SD_TRANSFER_MODE_MULTI_BLK_SEL BIT_5 |
| /* Data Transfer Direction Select */ |
| #define SD_TRANSFER_MODE_TO_HOST_DIR BIT_4 |
| /* Bit(s) SD_TRANSFER_MODE_RSRV_3 reserved */ |
| #define SD_TRANSFER_MODE_AUTO_CMD12_EN BIT_2 /* Auto CMD12 Enable */ |
| #define SD_TRANSFER_MODE_BLK_CNT_EN BIT_1 /* Block Count Enable */ |
| #define SD_TRANSFER_MODE_DMA_EN BIT_0 /* DMA Enable */ |
| |
| /* SD_CMD 0x000E Command Register */ |
| /* Bit(s) SD_CMD_RSRV_15_14 reserved */ |
| #define SD_CMD_CMD_INDEX_MSK SHIFT8(0x3f) /* Command Index */ |
| #define SD_CMD_CMD_INDEX_BASE 8 |
| #define SD_CMD_CMD_TYPE_MSK SHIFT6(0x3) /* Command Type */ |
| #define SD_CMD_CMD_TYPE_BASE 6 |
| #define SD_CMD_DATA_PRESENT BIT_5 /* Data Present */ |
| #define SD_CMD_CMD_INDEX_CHK_EN BIT_4 /* Command Index Check Enable */ |
| #define SD_CMD_CMD_CRC_CHK_EN BIT_3 /* Command CRC Check Enable */ |
| /* Bit(s) SD_CMD_RSRV_2 reserved */ |
| /* Response Type Select for SD Mode */ |
| #define SD_CMD_RESP_TYPE_MSK SHIFT0(0x3) |
| #define SD_CMD_RESP_TYPE_BASE 0 |
| |
| /* SD_RESP_0 0x0010 Response Register 0 */ |
| #define SD_RESP_0_RESP0_MSK SHIFT0(0xffff) /* Response 0 */ |
| #define SD_RESP_0_RESP0_BASE 0 |
| |
| /* SD_RESP_1 0x0012 Response Register 1 */ |
| #define SD_RESP_1_RESP1_MSK SHIFT0(0xffff) /* Response 1 */ |
| #define SD_RESP_1_RESP1_BASE 0 |
| |
| /* SD_RESP_2 0x0014 Response Register 2 */ |
| #define SD_RESP_2_RESP2_MSK SHIFT0(0xffff) /* Response 2 */ |
| #define SD_RESP_2_RESP2_BASE 0 |
| |
| /* SD_RESP_3 0x0016 Response Register 3 */ |
| #define SD_RESP_3_RESP3_MSK SHIFT0(0xffff) /* Response 3 */ |
| #define SD_RESP_3_RESP3_BASE 0 |
| |
| /* SD_RESP_4 0x0018 Response Register 4 */ |
| #define SD_RESP_4_RESP4_MSK SHIFT0(0xffff) /* Response 4 */ |
| #define SD_RESP_4_RESP4_BASE 0 |
| |
| /* SD_RESP_5 0x001A Response Register 5 */ |
| #define SD_RESP_5_RESP5_MSK SHIFT0(0xffff) /* Response 5 */ |
| #define SD_RESP_5_RESP5_BASE 0 |
| |
| /* SD_RESP_6 0x001C Response Register 6 */ |
| #define SD_RESP_6_RESP6_MSK SHIFT0(0xffff) /* Response 6 */ |
| #define SD_RESP_6_RESP6_BASE 0 |
| |
| /* SD_RESP_7 0x001E Response Register 7 */ |
| #define SD_RESP_7_RESP7_MSK SHIFT0(0xffff) /* Response 7 */ |
| #define SD_RESP_7_RESP7_BASE 0 |
| |
| /* SD_BUFFER_DATA_PORT_0 0x0020 Buffer Data Port 0 Register */ |
| #define SD_BUFFER_DATA_PORT_0_CPU_DATA0_MSK SHIFT0(0xffff) /* CPU Data 0 */ |
| #define SD_BUFFER_DATA_PORT_0_CPU_DATA0_BASE 0 |
| |
| /* SD_BUFFER_DATA_PORT_1 0x0022 Buffer Data Port 1 Register */ |
| #define SD_BUFFER_DATA_PORT_1_CPU_DATA1_MSK SHIFT0(0xffff) /* CPU Data 1 */ |
| #define SD_BUFFER_DATA_PORT_1_CPU_DATA1_BASE 0 |
| |
| /* SD_PRESENT_STATE_1 0x0024 Present State Register 1 */ |
| /* Bit(s) SD_PRESENT_STATE_1_RSRV_15_12 reserved */ |
| /* Buffer Read Enable */ |
| #define SD_PRESENT_STATE_1_BUFFER_RD_EN BIT_11 |
| /* Buffer Write Enable */ |
| #define SD_PRESENT_STATE_1_BUFFER_WR_EN BIT_10 |
| #define SD_PRESENT_STATE_1_RX_ACTIVE BIT_9 /* Rx Active */ |
| #define SD_PRESENT_STATE_1_TX_ACTIVE BIT_8 /* Tx Active */ |
| /* Bit(s) SD_PRESENT_STATE_1_RSRV_7_3 reserved */ |
| #define SD_PRESENT_STATE_1__DAT_ACTIVE BIT_2 /* Data Line Active */ |
| /* Command Inhibit Data */ |
| #define SD_PRESENT_STATE_1_CMD_INHIBIT_DAT BIT_1 |
| /* Command Inhibit Command */ |
| #define SD_PRESENT_STATE_1_CMD_INHIBIT_CMD BIT_0 |
| |
| /* SD_PRESENT_STATE_2 0x0026 Present State Register 2 */ |
| /* Bit(s) SD_PRESENT_STATE_2_RSRV_15_9 reserved */ |
| /* SDCMD Line Signal Level */ |
| #define SD_PRESENT_STATE_2_CMD_LEVEL BIT_8 |
| /* SDDATA[3:0] Line Signal Level */ |
| #define SD_PRESENT_STATE_2_DAT_LEVEL_MSK SHIFT4(0xf) |
| #define SD_PRESENT_STATE_2_DAT_LEVEL_BASE 4 |
| #define SD_PRESENT_STATE_2_WRITE_PROT BIT_3 /* Write Protect */ |
| #define SD_PRESENT_STATE_2_CARD_DET BIT_2 /* Card Detect */ |
| #define SD_PRESENT_STATE_2_CARD_STABLE BIT_1 /* Card Stable */ |
| #define SD_PRESENT_STATE_2_CARD_INSERTED BIT_0 /* Card Inserted */ |
| |
| /* SD_HOST_CTRL 0x0028 Host Control Register */ |
| /* Bit(s) SD_HOST_CTRL_RSRV_15_12 reserved */ |
| #define SD_HOST_CTRL_SD_BUS_VLT_MSK SHIFT9(0x7) /* SD Bus Voltage */ |
| #define SD_HOST_CTRL_SD_BUS_VLT_BASE 9 |
| #define SD_HOST_CTRL_SD_BUS_POWER BIT_8 /* SD Bus Power */ |
| /* Card Detect Signal Selection */ |
| #define SD_HOST_CTRL_CARD_DET_S BIT_7 |
| /* Card Detect Test Level */ |
| #define SD_HOST_CTRL_CARD_DET_L BIT_6 |
| /* Bit(s) SD_HOST_CTRL_RSRV_5 reserved */ |
| #define SD_HOST_CTRL_DMA_SEL_MSK SHIFT3(0x3) /* DMA Select */ |
| #define SD_HOST_CTRL_DMA_SEL_BASE 3 |
| /* Extend Data Output Enable */ |
| #define SD_HOST_CTRL_HI_SPEED_EN BIT_2 |
| #define SD_HOST_CTRL_DATA_WIDTH BIT_1 /* Data Width */ |
| #define SD_HOST_CTRL_LED_CTRL BIT_0 /* LED Control */ |
| |
| /* SD_BLOCK_GAP_CTRL 0x002A Block Gap Control Register */ |
| /* Bit(s) SD_BLOCK_GAP_CTRL_RSRV_15_11 reserved */ |
| /* Wakeup on Card Removal */ |
| #define SD_BLOCK_GAP_CTRL_W_REMOVAL BIT_10 |
| /* Wakeup on Card Insertion */ |
| #define SD_BLOCK_GAP_CTRL_W_INSERTION BIT_9 |
| /* Wakeup on Card Interrupt */ |
| #define SD_BLOCK_GAP_CTRL_W_CARD_INT BIT_8 |
| /* Bit(s) SD_BLOCK_GAP_CTRL_RSRV_7_4 reserved */ |
| /* Block Gap Interrupt */ |
| #define SD_BLOCK_GAP_CTRL_INT_BLK_GAP BIT_3 |
| /* Read Wait Control */ |
| #define SD_BLOCK_GAP_CTRL_RD_WAIT_CTL BIT_2 |
| /* Continue Request */ |
| #define SD_BLOCK_GAP_CTRL_CONT_REQ BIT_1 |
| /* Stop At Block Gap Request */ |
| #define SD_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_REQ BIT_0 |
| |
| /* SD_CLOCK_CTRL 0x002C Clock Control Register */ |
| /* SDCLK Frequency Select */ |
| #define SD_CLOCK_CTRL_SD_FREQ_SEL_MSK SHIFT8(0xff) |
| #define SD_CLOCK_CTRL_SD_FREQ_SEL_BASE 8 |
| /* Bit(s) SD_CLOCK_CTRL_RSRV_7_3 reserved */ |
| #define SD_CLOCK_CTRL_SD_CLK_EN BIT_2 /* SDCLK Clock Enable */ |
| /* Internal Clock Stable */ |
| #define SD_CLOCK_CTRL_INT_CLK_STABLE BIT_1 |
| /* Internal Clock Enable */ |
| #define SD_CLOCK_CTRL_INT_CLK_EN BIT_0 |
| |
| /* SD_TIMEOUT_CTRL_SW_RESET 0x002E Timeout Control/Software Reset |
| * Register |
| */ |
| /* Bit(s) SD_TIMEOUT_CTRL_SW_RESET_RSRV_15_11 reserved */ |
| /* Soft Reset for Data Port of Logic */ |
| #define SD_TIMEOUT_CTRL_SW_RESET_SW_RST_DAT BIT_10 |
| /* Soft Reset for Command Part of Logic */ |
| #define SD_TIMEOUT_CTRL_SW_RESET_SW_RST_CMD BIT_9 |
| /* Software Reset for All */ |
| #define SD_TIMEOUT_CTRL_SW_RESET_SW_RST_ALL BIT_8 |
| /* Bit(s) SD_TIMEOUT_CTRL_SW_RESET_RSRV_7_4 reserved */ |
| /* Timeout Value */ |
| #define SD_TIMEOUT_CTRL_SW_RESET_TIMEOUT_VALUE_MSK SHIFT0(0xf) |
| #define SD_TIMEOUT_CTRL_SW_RESET_TIMEOUT_VALUE_BASE 0 |
| |
| /* SD_NORMAL_INT_STATUS 0x0030 Normal Interrupt Status Register */ |
| #define SD_NORMAL_INT_STATUS_ERR_INT BIT_15 /* Error Interrupt */ |
| /* Bit(s) SD_NORMAL_INT_STATUS_RSRV_14_9 reserved */ |
| #define SD_NORMAL_INT_STATUS_CARD_INT BIT_8 /* Card Interrupt */ |
| /* Card Removal Interrupt */ |
| #define SD_NORMAL_INT_STATUS_CARD_REM_INT BIT_7 |
| /* Card Insertion Interrupt */ |
| #define SD_NORMAL_INT_STATUS_CARD_INS_INT BIT_6 |
| #define SD_NORMAL_INT_STATUS_RX_RDY BIT_5 /* Rx Ready */ |
| #define SD_NORMAL_INT_STATUS__TX_RDY BIT_4 /* Tx Ready */ |
| #define SD_NORMAL_INT_STATUS_DMA_INT BIT_3 /* DMA Interrupt */ |
| #define SD_NORMAL_INT_STATUS_BLOCK_GAP_EVT BIT_2 /* Block Gap Event */ |
| /* Transfer Complete */ |
| #define SD_NORMAL_INT_STATUS_XFER_COMPLETE BIT_1 |
| #define SD_NORMAL_INT_STATUS_CMD_COMPLETE BIT_0 /* Command Complete */ |
| |
| /* SD_ERROR_INT_STATUS 0x0032 Error Interrupt Status Register */ |
| /* CRC Status Error */ |
| #define SD_ERROR_INT_STATUS_CRC_STATUS_ERR BIT_15 |
| /* Command Completion Signal Timeout Error */ |
| #define SD_ERROR_INT_STATUS_CPL_TIMEOUT_ERR BIT_14 |
| /* AXI Bus Response Error */ |
| #define SD_ERROR_INT_STATUS_AXI_RESP_ERR BIT_13 |
| /* SPI Mode Error */ |
| #define SD_ERROR_INT_STATUS_SPI_ERR BIT_12 |
| #define SD_ERROR_INT_STATUS_TUNE_ERR BIT_10 |
| |
| /* Bit(s) SD_ERROR_INT_STATUS_RSRV_11_10 reserved */ |
| #define SD_ERROR_INT_STATUS_ADMA_ERR BIT_9 /* ADMA Error */ |
| /* Auto CMD12 Error */ |
| #define SD_ERROR_INT_STATUS_AUTO_CMD12_ERR BIT_8 |
| /* Current Limit Error */ |
| #define SD_ERROR_INT_STATUS_CUR_LIMIT_ERR BIT_7 |
| /* ReadDataEnd Bit Error */ |
| #define SD_ERROR_INT_STATUS_RD_DATA_END_BIT_ERR BIT_6 |
| /* Read Data CRC Error */ |
| #define SD_ERROR_INT_STATUS_RD_DATA_CRC_ERR BIT_5 |
| /* Data Timeout Error */ |
| #define SD_ERROR_INT_STATUS_DATA_TIMEOUT_ERR BIT_4 |
| /* Command Index Error */ |
| #define SD_ERROR_INT_STATUS_CMD_INDEX_ERR BIT_3 |
| /* Command End Bit Error */ |
| #define SD_ERROR_INT_STATUS_CMD_END_BIT_ERR BIT_2 |
| /* Command CRC Error */ |
| #define SD_ERROR_INT_STATUS_CMD_CRC_ERR BIT_1 |
| /* Command Timeout Error */ |
| #define SD_ERROR_INT_STATUS_CMD_TIMEOUT_ERR BIT_0 |
| |
| /* SD_NORMAL_INT_STATUS_EN 0x0034 Normal Interrupt Status Enable |
| * Register |
| */ |
| /* Bit(s) SD_NORMAL_INT_STATUS_EN_RSRV_15_9 reserved */ |
| /* Card Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_EN_CARD_INT_EN BIT_8 |
| /* Card Removal Status Enable */ |
| #define SD_NORMAL_INT_STATUS_EN_CARD_REM_EN BIT_7 |
| /* Card Insertion Status Enable */ |
| #define SD_NORMAL_INT_STATUS_EN_CARD_INS_EN BIT_6 |
| /* Buffer Read Ready Enable */ |
| #define SD_NORMAL_INT_STATUS_EN_RD_RDY_EN BIT_5 |
| /* Buffer Write Ready Enable */ |
| #define SD_NORMAL_INT_STATUS_EN_TX_RDY_EN BIT_4 |
| /* DMA Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_EN_DMA_INT_EN BIT_3 |
| /* Block Gap Event Enable */ |
| #define SD_NORMAL_INT_STATUS_EN_BLOCK_GAP_EVT_EN BIT_2 |
| /* Transfer Complete Enable */ |
| #define SD_NORMAL_INT_STATUS_EN_XFER_COMPLETE_EN BIT_1 |
| /* Command Complete Enable */ |
| #define SD_NORMAL_INT_STATUS_EN_CMD_COMPLETE_EN BIT_0 |
| |
| /* SD_ERROR_INT_STATUS_EN 0x0036 Error Interrupt Status Enable |
| * Register |
| */ |
| /* CRC Status Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_CRC_STATUS_ERR_EN BIT_15 |
| /* CPL Timeout Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_CPL_TIMEOUT_ERR_EN BIT_14 |
| /* AXI Response Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_AXI_RESP_ERR_EN BIT_13 |
| /* SPI Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_SPI_ERR_EN BIT_12 |
| /* Bit(s) SD_ERROR_INT_STATUS_EN_RSRV_11_10 reserved */ |
| /* ADMA Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_ADMA_ERR_EN BIT_9 |
| /* Auto CMD12 Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_AUTO_CMD12_ERR_EN BIT_8 |
| /* Current Limit Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_CUR_LIM_ERR_EN BIT_7 |
| /* Data End Bit Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_RD_DATA_END_BIT_ERR_EN BIT_6 |
| /* Data CRC Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_RD_DATA_CRC_ERR_EN BIT_5 |
| /* Data Timeout Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_DATA_TIMEOUT_ERR_EN BIT_4 |
| /* Command Index Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_CMD_INDEX_ERR_EN BIT_3 |
| /* Command End Bit Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_CMD_END_BIT_ERR_EN BIT_2 |
| /* Command CRC Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_CMD_CRC_ERR_EN BIT_1 |
| /* Command Timeout Error Enable */ |
| #define SD_ERROR_INT_STATUS_EN_CMD_TIMEOUT_ERR_EN BIT_0 |
| |
| /* SD_NORMAL_INT_STATUS_INT_EN 0x0038 Normal Interrupt Status Interrupt |
| * Enable Register |
| */ |
| /* Bit(s) SD_NORMAL_INT_STATUS_INT_EN_RSRV_15_9 reserved */ |
| /* Card Interrupt Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_INT_EN_CARD_INT_INT_EN BIT_8 |
| /* Card Removal Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_INT_EN_CARD_REM_INT_EN BIT_7 |
| /* Card Insertion Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_INT_EN_CARD_INS_INT_EN BIT_6 |
| /* Buffer Read Ready Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_INT_EN_RX_RDY_INT_EN BIT_5 |
| /* Buffer Write Ready Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_INT_EN_TX_RDY_INT_EN BIT_4 |
| /* DMA Interrupt Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_INT_EN_DMA_INT_INT_EN BIT_3 |
| /* Block Gap Event Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_INT_EN_BLOCK_GAP_EVT_INT_EN BIT_2 |
| /* Transfer Complete Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_INT_EN_XFER_COMPLETE_INT_EN BIT_1 |
| /* Command Complete Interrupt Enable */ |
| #define SD_NORMAL_INT_STATUS_INT_EN_CMD_COMPLETE_INT_EN BIT_0 |
| |
| /* SD_ERROR_INT_STATUS_INT_EN 0x003A Error Interrupt Status Interrupt |
| * Enable Register |
| */ |
| /* CRC Status Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_CRC_STATUS_ERR_INT_EN BIT_15 |
| /* CPL Timeout Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_CPL_TIMEOUT_ERR_INT_EN BIT_14 |
| /* AXI Response Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_AXI_RESP_ERR_INT_EN BIT_13 |
| /* SPI Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_SPI_ERR_INT_EN BIT_12 |
| /* Bit(s) SD_ERROR_INT_STATUS_INT_EN_RSRV_11_10 reserved */ |
| /* ADMA Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_ADMA_ERR_INT_EN BIT_9 |
| /* Auto CMD12 Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_AUTO_CMD12_ERR_INT_EN BIT_8 |
| /* Current Limit Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_CUR_LIM_ERR_INT_EN BIT_7 |
| /* Data End Bit Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_RD_DATA_END_BIT_ERR_INT_EN BIT_6 |
| /* Data CRC Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_RD_DATA_CRC_ERR_INT_EN BIT_5 |
| /* Data Timeout Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_DATA_TIMEOUT_ERR_INT_EN BIT_4 |
| /* Command Index Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_CMD_INDEX_ERR_INT_EN BIT_3 |
| /* Command End Bit Interrupt Error Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_CMD_END_BIT_ERR_INT_EN BIT_2 |
| /* Command CRC Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_CMD_CRC_ERR_INT_EN BIT_1 |
| /* Command Timeout Error Interrupt Enable */ |
| #define SD_ERROR_INT_STATUS_INT_EN_CMD_TIMEOUT_ERR_INT_EN BIT_0 |
| |
| /* SD_AUTO_CMD12_ERROR_STATUS 0x003C Auto CMD12 Error Status Register */ |
| /* Bit(s) SD_AUTO_CMD12_ERROR_STATUS_RSRV_15_8 reserved */ |
| /* Command Not Issued Due to auto_cmd12 Error */ |
| #define SD_AUTO_CMD12_ERROR_STATUS_CMD_NOT_ISSUED BIT_7 |
| /* Bit(s) SD_AUTO_CMD12_ERROR_STATUS_RSRV_6_5 reserved */ |
| /* Auto CMD12 Error */ |
| #define SD_AUTO_CMD12_ERROR_STATUS_AUTO_CMD12_INDEX_ERR BIT_4 |
| /* Auto CMD12 End Bit Error */ |
| #define SD_AUTO_CMD12_ERROR_STATUS_AUTO_CMD12_END_BIT_ERR BIT_3 |
| /* Auto CMD12 CRC Error */ |
| #define SD_AUTO_CMD12_ERROR_STATUS_AUTO_CMD12_CRC_ERR BIT_2 |
| /* Auto CMD12 Timeout Error */ |
| #define SD_AUTO_CMD12_ERROR_STATUS_AUTO_CMD12_TIMEOUT_ERR BIT_1 |
| /* Auto CMD12 Not Executed */ |
| #define SD_AUTO_CMD12_ERROR_STATUS_AUTO_CMD12_NOT_EXE BIT_0 |
| |
| /* SD_CAPABILITIES_1 0x0040 Capabilities Register 1 */ |
| /* Bit(s) SD_CAPABILITIES_1_RSRV_15_14 reserved */ |
| #define SD_CAPABILITIES_1_BASE_FREQ_MSK SHIFT8(0x3f) /* Base Frequency */ |
| #define SD_CAPABILITIES_1_BASE_FREQ_BASE 8 |
| #define SD_CAPABILITIES_1_TIMEOUT_UNIT BIT_7 /* Timeout Unit */ |
| /* Bit(s) SD_CAPABILITIES_1_RSRV_6 reserved */ |
| /* Timeout Frequency */ |
| #define SD_CAPABILITIES_1_TIMEOUT_FREQ_MSK SHIFT0(0x3f) |
| #define SD_CAPABILITIES_1_TIMEOUT_FREQ_BASE 0 |
| |
| /* SD_CAPABILITIES_3 0x0044 Capabilities Register 3 */ |
| /* Bit(s) SD_CAPABILITIES_3_RSRV_15_0 reserved */ |
| |
| /* SD_CAPABILITIES_4 0x0046 Capabilities Register 4 */ |
| /* Bit(s) SD_CAPABILITIES_4_RSRV_15_0 reserved */ |
| |
| /* SD_MAX_CURRENT_1 0x0048 Maximum Current Register 1 */ |
| /* Maximum Current for 3.0V */ |
| #define SD_MAX_CURRENT_1_MAX_CUR_30_MSK SHIFT8(0xff) |
| #define SD_MAX_CURRENT_1_MAX_CUR_30_BASE 8 |
| /* Maximum Current for 3.3V */ |
| #define SD_MAX_CURRENT_1_MAX_CUR_33_MSK SHIFT0(0xff) |
| #define SD_MAX_CURRENT_1_MAX_CUR_33_BASE 0 |
| |
| /* SD_MAX_CURRENT_2 0x004A Maximum Current Register 2 */ |
| /* Bit(s) SD_MAX_CURRENT_2_RSRV_15_8 reserved */ |
| /* Maximum Current for 1.8V */ |
| #define SD_MAX_CURRENT_2_MAX_CUR_18_MSK SHIFT0(0xff) |
| #define SD_MAX_CURRENT_2_MAX_CUR_18_BASE 0 |
| |
| /* SD_MAX_CURRENT_3 0x004C Maximum Current Register 3 */ |
| /* Bit(s) SD_MAX_CURRENT_3_RSRV_15_0 reserved */ |
| |
| /* SD_MAX_CURRENT_4 0x004E Maximum Current Register 4 */ |
| /* Bit(s) SD_MAX_CURRENT_4_RSRV_15_0 reserved */ |
| |
| /* SD_FORCE_EVENT_AUTO_CMD12_ERROR 0x0050 Force Event Auto cmd12 Error |
| * Register |
| */ |
| /* Bit(s) SD_FORCE_EVENT_AUTO_CMD12_ERROR_RSRV_15_8 reserved */ |
| /* Force Event for Command not Issued by Auto Cmd12 Error */ |
| #define SD_FORCE_EVENT_AUTO_CMD12_ERROR_F_ACMD12_ISSUE_ERR BIT_7 |
| /* Bit(s) SD_FORCE_EVENT_AUTO_CMD12_ERROR_RSRV_6_5 reserved */ |
| /* Force Event for Auto Cmd12 Index Error */ |
| #define SD_FORCE_EVENT_AUTO_CMD12_ERROR_F_ACMD12_INDEX_ERR BIT_4 |
| /* Force Event for Auto Cmd12 End Bit Error */ |
| #define SD_FORCE_EVENT_AUTO_CMD12_ERROR_F__ACMD12_EBIT_ERR BIT_3 |
| /* Force Event for Auto Cmd12 CRC Error */ |
| #define SD_FORCE_EVENT_AUTO_CMD12_ERROR_F_ACMD12_CRC_ERR BIT_2 |
| /* Force Event for Auto Cmd12 Timeout Error */ |
| #define SD_FORCE_EVENT_AUTO_CMD12_ERROR_F_ACMD12_TO_ERR BIT_1 |
| /* Force Event for Auto Cmd12 Not Executed Error */ |
| #define SD_FORCE_EVENT_AUTO_CMD12_ERROR_F_ACMD12_NEXE_ERR BIT_0 |
| |
| /* SD_FORCE_EVENT_FOR_ERROR_STATUS 0x0052 Force Event for Error Status |
| * Register |
| */ |
| /* Force Event for CRC Status Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_CRC_STATUS_ERR BIT_15 |
| /* Force Event for CPL Timeout Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_CPL_TIMEOUT_ERR BIT_14 |
| /* Force Event for AXI Response Bit Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_AXI_RESP_ERR BIT_13 |
| /* Force Event for SPI Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_SPI_ERR BIT_12 |
| /* Bit(s) SD_FORCE_EVENT_FOR_ERROR_STATUS_RSRV_11_10 reserved */ |
| /* Force Event for ADMA Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_ADMA_ERR BIT_9 |
| /* Force Event for Auto Cmd12 Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_ACMD12_ERR BIT_8 |
| /* Force Event for Current Limit Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_CURRENT_ERR BIT_7 |
| /* Force Event for Data End Bit Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_DAT_END_BIT_ERR BIT_6 |
| /* Force Event for Data CRC Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_DAT_CRC_ERR BIT_5 |
| /* Force Event for Data Timeout Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_DAT_TO_ERR BIT_4 |
| /* Force Event for Command Index Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_CMD_INDEX_ERR BIT_3 |
| /* Force Event for Command End Bit Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_CMD_END_BIT_ERR BIT_2 |
| /* Force Event for Command CRC Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_CMD_CRC_ERR BIT_1 |
| /* Force Event for Command Timeout Error */ |
| #define SD_FORCE_EVENT_FOR_ERROR_STATUS_F_CMD_TO_ERR BIT_0 |
| |
| /* SD_ADMA_ERROR_STATUS 0x0054 ADMA Error Status Register */ |
| /* Bit(s) SD_ADMA_ERROR_STATUS_RSRV_15_3 reserved */ |
| /* ADMA Length Mismatch Error */ |
| #define SD_ADMA_ERROR_STATUS_ADMA_LEN_ERR BIT_2 |
| /* ADMA Error State */ |
| #define SD_ADMA_ERROR_STATUS_ADMA_STATE_MSK SHIFT0(0x3) |
| #define SD_ADMA_ERROR_STATUS_ADMA_STATE_BASE 0 |
| |
| /* SD_ADMA_SYS_ADDR_1 0x0058 ADMA System Address Register 1 */ |
| /* ADMA System Address */ |
| #define SD_ADMA_SYS_ADDR_1_ADMA_SYS_ADDR_MSK SHIFT0(0xffff) |
| #define SD_ADMA_SYS_ADDR_1_ADMA_SYS_ADDR_BASE 0 |
| |
| /* SD_ADMA_SYS_ADDR_2 0x005A ADMA System Address Register 2 */ |
| /* ADMA System Address */ |
| #define SD_ADMA_SYS_ADDR_2_ADMA_SYS_ADDR_MSK SHIFT0(0xffff) |
| #define SD_ADMA_SYS_ADDR_2_ADMA_SYS_ADDR_BASE 0 |
| |
| /* SD_ADMA_SYS_ADDR_3 0x005C ADMA System Address Register 3 */ |
| /* ADMA System Address */ |
| #define SD_ADMA_SYS_ADDR_3_ADMA_SYS_ADDR_MSK SHIFT0(0xffff) |
| #define SD_ADMA_SYS_ADDR_3_ADMA_SYS_ADDR_BASE 0 |
| |
| /* SD_ADMA_SYS_ADDR_4 0x005E ADMA System Address Register 4 */ |
| /* ADMA System Address */ |
| #define SD_ADMA_SYS_ADDR_4_ADMA_SYS_ADDR_MSK SHIFT0(0xffff) |
| #define SD_ADMA_SYS_ADDR_4_ADMA_SYS_ADDR_BASE 0 |
| |
| /* SD_FIFO_PARAM 0x00E0 FIFO Parameters Register */ |
| /* Bit(s) SD_FIFO_PARAM_RSRV_15_11 reserved */ |
| /* Disable PAD SD Clock Gating */ |
| #define SD_FIFO_PARAM_DIS_PAD_SD_CLK_GATE BIT_10 |
| #define SD_FIFO_PARAM_CLK_GATE_ON BIT_9 /* Clock Gate On */ |
| #define SD_FIFO_PARAM_PDWN BIT_7 /* Power Down */ |
| #define SD_FIFO_PARAM_FIFO_CS BIT_6 /* FIFO CS */ |
| #define SD_FIFO_PARAM_FIFO_CLK BIT_5 /* FIFO Clock */ |
| #define SD_FIFO_PARAM_WTC_MSK SHIFT3(0x3) /* WTC */ |
| #define SD_FIFO_PARAM_WTC_BASE 3 |
| #define SD_FIFO_PARAM_RTC_MSK SHIFT0(0x7) /* RTC */ |
| #define SD_FIFO_PARAM_RTC_BASE 0 |
| |
| /* SD_SPI_MODE 0x00E4 SPI Mode Register */ |
| /* Bit(s) SD_SPI_MODE_RSRV_15_13 reserved */ |
| #define SD_SPI_MODE_SPI_ERR_TOKEN_MSK SHIFT8(0x1f) /* SPI Error Token */ |
| #define SD_SPI_MODE_SPI_ERR_TOKEN_BASE 8 |
| /* Bit(s) SD_SPI_MODE_RSRV_7_1 reserved */ |
| #define SD_SPI_MODE_SPI_EN BIT_0 /* Enable SPI Mode */ |
| |
| /* SD_CLOCK_AND_BURST_SIZE_SETUP 0x00E6 Clock and Burst Size Setup Register */ |
| /* Bit(s) SD_CLOCK_AND_BURST_SIZE_SETUP_RSRV_15_14 reserved */ |
| /* sd_clk Delay Value */ |
| #define SD_CLOCK_AND_BURST_SIZE_SETUP_SDCLK_DELAY_MSK SHIFT10(0xf) |
| #define SD_CLOCK_AND_BURST_SIZE_SETUP_SDCLK_DELAY_BASE 10 |
| /* sd_clk Select */ |
| #define SD_CLOCK_AND_BURST_SIZE_SETUP_SDCLK_SEL_MSK SHIFT8(0x3) |
| #define SD_CLOCK_AND_BURST_SIZE_SETUP_SDCLK_SEL_BASE 8 |
| /* Bit(s) SD_CLOCK_AND_BURST_SIZE_SETUP_RSRV_7_1 reserved */ |
| /* DMA Burst Size on the AXI fabric */ |
| #define SD_CLOCK_AND_BURST_SIZE_SETUP_BRST_SIZE BIT_0 |
| |
| /* SD_CE_ATA_1 0x00E8 CE-ATA Register 1 */ |
| /* Bit(s) SD_CE_ATA_1_RSRV_15_14 reserved */ |
| /* Command Completion Signal Timeout Value */ |
| #define SD_CE_ATA_1_CPL_TIMEOUT_MSK SHIFT0(0x3fff) |
| #define SD_CE_ATA_1_CPL_TIMEOUT_BASE 0 |
| |
| /* SD_CE_ATA_2 0x00EA CE-ATA Register 2 */ |
| /* Check Command Completion Signal */ |
| #define SD_CE_ATA_2_CHK_CPL BIT_15 |
| /* Send Command Completion Disable Signal */ |
| #define SD_CE_ATA_2_SND_CPL BIT_14 |
| #define SD_CE_ATA_2_CEATA_CARD BIT_13 /* CE-ATA Card */ |
| #define SD_CE_ATA_2_MMC_CARD BIT_12 /* MMC Card */ |
| /* Bit(s) SD_CE_ATA_2_RSRV_11_9 reserved */ |
| #define SD_CE_ATA_2_MMC_WIDTH BIT_8 /* MMC Width */ |
| /* Bit(s) SD_CE_ATA_2_RSRV_7 reserved */ |
| #define SD_CE_ATA_2_CPL_COMPLETE BIT_6 /* cpl_complete */ |
| /* cpl_complete Interrupt Enable */ |
| #define SD_CE_ATA_2_CPL_COMPLETE_EN BIT_5 |
| /* cpu_complete Interrupt Enable */ |
| #define SD_CE_ATA_2_CPL_COMPLETE_INT_EN BIT_4 |
| /* Bit(s) SD_CE_ATA_2_RSRV_3_0 reserved */ |
| |
| /* SD_PAD_IO_SETUP 0x00EC PAD I/O Setup Register */ |
| /* Bit(s) SD_PAD_IO_SETUP_RSRV_15_2 reserved */ |
| #define SD_PAD_IO_SETUP_INAND_SEL BIT_1 /* SD Socket 0 Select */ |
| /* SD Voltage Configuration */ |
| #define SD_PAD_IO_SETUP_SDH_V18_EN BIT_0 |
| |
| /* SD_SLOT_INT_STATUS 0x00FC Slot Interrupt Status Register */ |
| /* Bit(s) SD_SLOT_INT_STATUS_RSRV_15_2 reserved */ |
| /* Interrupt Line for Slot 1 */ |
| #define SD_SLOT_INT_STATUS_SLOT_INT1 BIT_1 |
| /* Interrupt Line for Slot 0 */ |
| #define SD_SLOT_INT_STATUS_SLOT_INT0 BIT_0 |
| |
| /* SD_HOST_CTRL_VER 0x00FE Host Control Version Register */ |
| /* Marvell Version Number */ |
| #define SD_HOST_CTRL_VER_VENDOR_VER_MSK SHIFT8(0xff) |
| #define SD_HOST_CTRL_VER_VENDOR_VER_BASE 8 |
| /* SD Host Specification Number */ |
| #define SD_HOST_CTRL_VER_SD_VER_MSK SHIFT0(0xff) |
| #define SD_HOST_CTRL_VER_SD_VER_BASE 0 |
| |
| /* SD_TX_CFG_REG 0x0118 TX Configuration Register */ |
| #define SD_TX_CFG_REG_TX_INT_CLK_SEL BIT_30 |
| |
| /* -------------------- */ |
| |
| |
| #endif /* __INC_SD_H */ |