| /****************************************************************************** |
| * |
| * Name: SSP.h |
| * Project: Hermon-2 |
| * Purpose: Testing |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * (C)Copyright 2005 - 2011 Marvell. All Rights Reserved. |
| * |
| * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL. |
| * The copyright notice above does not evidence any actual or intended |
| * publication of such source code. |
| * This Module contains Proprietary Information of Marvell and should be |
| * treated as Confidential. |
| * The information in this file is provided for the exclusive use of the |
| * licensees of Marvell. |
| * Such users have the right to use, modify, and incorporate this code into |
| * products for purposes authorized by the license agreement provided they |
| * include this notice and the associated copyright notice with any such |
| * product. |
| * The information in this file is provided "AS IS" without warranty. |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * This file was automatically generated by reg.pl using * SSP.csv |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * History: |
| * |
| ********* PLEASE INSERT THE CVS HISTORY OF THE PREVIOUS VERSION HERE. ********* |
| *******************************************************************************/ |
| |
| #ifndef __INC_SSP_H |
| #define __INC_SSP_H |
| |
| /* |
| * |
| * THE BASE ADDRESSES |
| * |
| */ |
| #define SSP1_BASE 0xD401B000 |
| #define SSP3_BASE 0xD401C000 |
| #define SSP2_BASE 0xD42A0C00 |
| |
| /* |
| * |
| * THE REGISTER DEFINES |
| * |
| */ |
| #define SSP_TOP_CTRL (0x0000) |
| #define SSP_FIFO_CTRL (0x0004) |
| #define SSP_INT_EN (0x0008) |
| #define SSP_TO (0x000C) |
| #define SSP_DATAR (0x0010) /* 32 bit SSP Data Register */ |
| #define SSP_STATUS (0x0014) |
| |
| /* |
| * |
| * SSP Top Control Register |
| * |
| */ |
| |
| /* TXD Three-state Enable On Last Phase */ |
| #define SSP_TCR_TTELP BIT_18 |
| |
| /* TXD Three-State Enable */ |
| #define SSP_TCR_TTE BIT_17 |
| |
| /* Slave Clock Free Running */ |
| #define SSP_TCR_SCFR BIT_16 |
| |
| /* Invert Frame Signal */ |
| #define SSP_TCR_IFS BIT_15 |
| |
| /* Hold Frame Low Control */ |
| #define SSP_TCR_HFL BIT_14 |
| |
| /* Trailing Byte */ |
| #define SSP_TCR_TRIAL BIT_13 |
| |
| /* Loopback Mode */ |
| #define SSP_TCR_LBM BIT_12 |
| |
| /* Motorola SPI SSPSCLK phase setting */ |
| #define SSP_TCR_SPH BIT_11 |
| |
| /* Motorola SPI SSPSCLK Polarity Setting */ |
| #define SSP_TCR_SPO BIT_10 |
| |
| /* Data Size Select */ |
| #define SSP_TCR_DSS_MASK SHIFT5(0x1f) |
| #define SSP_TCR_DSS32 SHIFT5(0x1f) |
| #define SSP_TCR_DSS24 SHIFT5(0x17) |
| #define SSP_TCR_DSS16 SHIFT5(0xf) |
| #define SSP_TCR_DSS8 SHIFT5(0x7) |
| |
| /* SSP Frame (SSPSFRMx) Direction */ |
| #define SSP_TCR_SFRMDIR BIT_4 |
| |
| /* SSP Serial Bit Rate Clock (SSPSCLKx) Direction */ |
| #define SSP_TCR_SCLKDIR BIT_3 |
| #define SSP_TCR_FRF_MASK SHIFT1(0x3) |
| |
| /* Synchronous Serial Port Enable */ |
| #define SSP_TCR_SSE BIT_0 |
| |
| /* |
| * |
| * SSP FIFO Control Register |
| * |
| */ |
| |
| /* Rx FIFO Auto Full Control */ |
| #define SSP_FCR_RAFC BIT_17 |
| |
| /* apb_pwdata Write to Tx FIFO Endian */ |
| #define SSP_FCR_TWE_MASK SHIFT14(0x3) |
| #define SSP_FCR_TWE(x) (x << 14) |
| |
| /* apb_prdata Read from Rx FIFO Endian */ |
| #define SSP_FCR_RRE_MASK SHIFT12(0x3) |
| #define SSP_FCR_RRE(x) (x << 12) |
| |
| /* Receive Service Request Enable */ |
| #define SSP_FCR_RSRE BIT_11 |
| |
| /* Transmit Service Request Enable */ |
| #define SSP_FCR_TSRE BIT_10 |
| |
| /* RXFIFO Trigger Threshold */ |
| /* MaxBurstSize(DMA)/Data Size Select(SSP) - 1 */ |
| #define SSP_FCR_RFT_MASK SHIFT5(0x1f) |
| #define SSP_FCR_RFT(x) (x << 5) |
| |
| /* TXFIFO Trigger Threshold */ |
| /* MaxBurstSize(DMA)/Data Size Select(SSP) - 1 */ |
| #define SSP_FCR_TFT_MASK SHIFT0(0x1f) |
| #define SSP_FCR_TFT(x) (x << 0) |
| |
| /* |
| * |
| * SSP Interrupt Enable Register |
| * |
| */ |
| |
| /* Transmit FIFO Underrun Interrupt Mask */ |
| #define SSP_IER_TIM BIT_5 |
| |
| /* Receive FIFO Overrun Interrupt Mask */ |
| #define SSP_IER_RIM BIT_4 |
| |
| /* Transmit FIFO Interrupt Enable */ |
| #define SSP_IER_TIE BIT_3 |
| |
| /* Receive FIFO Interrupt Enable */ |
| #define SSP_IER_RIE BIT_2 |
| |
| /* Receiver Time-out Interrupt Enable */ |
| #define SSP_IER_RTOIE BIT_1 |
| |
| |
| /* -------------------- */ |
| |
| |
| #endif /* __INC_SSP_H */ |