| /****************************************************************************** |
| * |
| * Name: NFC.h |
| * Project: Hermon-2 |
| * Purpose: Testing |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * (C)Copyright 2005 - 2011 Marvell. All Rights Reserved. |
| * |
| * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL. |
| * The copyright notice above does not evidence any actual or intended |
| * publication of such source code. |
| * This Module contains Proprietary Information of Marvell and should be |
| * treated as Confidential. |
| * The information in this file is provided for the exclusive use of the |
| * licensees of Marvell. |
| * Such users have the right to use, modify, and incorporate this code into |
| * products for purposes authorized by the license agreement provided they |
| * include this notice and the associated copyright notice with any such |
| * product. |
| * The information in this file is provided "AS IS" without warranty. |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * This file was automatically generated by reg.pl using * NFC.csv |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * History: |
| * |
| ********* PLEASE INSERT THE CVS HISTORY OF THE PREVIOUS VERSION HERE. ********* |
| *******************************************************************************/ |
| |
| #ifndef __INC_NFC_H |
| #define __INC_NFC_H |
| |
| |
| /* |
| * |
| * THE BASE ADDRESSES |
| * |
| */ |
| #define NFU_BASE 0xD4283000 |
| |
| /* |
| * |
| * THE REGISTER DEFINES |
| * |
| */ |
| #define NFU_DCR (NFU_BASE+0x0000) /* 32 bit Data Flash Control |
| * Register |
| */ |
| #define NFU_DTR0CS0 (NFU_BASE+0x0004) /* 32 bit Data Controller Timing |
| * Parameter 0 Register |
| * for ND_nCS0 |
| */ |
| #define NFU_DTR1CS0 (NFU_BASE+0x000C) /* 32 bit Data Controller Timing |
| * Parameter 1 Register |
| * for ND_nCS0 |
| */ |
| #define NFU_DSR (NFU_BASE+0x0014) /* 32 bit Data Controller Status |
| * Register |
| */ |
| #define NFU_DPCR (NFU_BASE+0x0018) /* 32 bit Data Controller Page |
| * Count Register |
| */ |
| #define NFU_DBBRX (NFU_BASE+0x001C) /* Data Controller Bad Block |
| * Registers 0 and 1 |
| * Start |
| */ |
| #define NFU_DREDEL (NFU_BASE+0x0024) /* 32 bit Read Enable Return |
| * Delay Register |
| */ |
| #define NFU_DECCCTRL (NFU_BASE+0x0028) /* 32 bit ECC Control Register */ |
| #define NFU_DBZCNT (NFU_BASE+0x002C) /* 32 bit Timer for ND_RnB0 and |
| * ND_RnB1 |
| */ |
| #define NFU_DMUTEX (NFU_BASE+0x0030) /* 32 bit NAND Controller MUTEX |
| * Lock Register |
| */ |
| #define NFU_DCMDMAT (NFU_BASE+0x0034) /* Partition Command Match Registers Start */ |
| #define NFU_DDB (NFU_BASE+0x0040) /* 32 bit Data Controller Data |
| * Buffer Register |
| */ |
| #define NFU_DCB0 (NFU_BASE+0x0048) /* 32 bit Data Controller Command |
| * Buffer 0 |
| */ |
| #define NDCB1 (NFU_BASE+0x004C) /* 32 bit Data Controller Command |
| * Buffer 1 |
| */ |
| #define NDCB2 (NFU_BASE+0x0050) /* 32 bit Data Controller Command |
| * Buffer 2 |
| */ |
| #define NDCB3 (NFU_BASE+0x0054) /* 32 bit Data Controller Command |
| * Buffer 3 |
| */ |
| #define NDARBCR (NFU_BASE+0x005C) /* 32 bit NAND DFI Arbitration |
| * Control Register |
| */ |
| #define NDPTXCSX (NFU_BASE+0x0060) /* Partition Region Control |
| * Registers for CS0 and |
| * CS1 Start |
| */ |
| |
| /* |
| * |
| * THE BIT DEFINES |
| * |
| */ |
| /* NFU_DCR 0x0000 Data Flash Control Register */ |
| #define NFU_DCR_SPARE_EN BIT_31 /* Spare Area Enable */ |
| #define NFU_DCR_ECC_EN BIT_30 /* ECC Enable */ |
| #define NFU_DCR_DMA_EN BIT_29 /* DMA Request Enable */ |
| #define NFU_DCR_ND_RUN BIT_28 /* NAND Controller Run Mode */ |
| /* Data Bus Width of the NAND Flash Controller */ |
| #define NFU_DCR_DWIDTH_C BIT_27 |
| /* Data Bus Width of the NAND Flash Memory */ |
| #define NFU_DCR_DWIDTH_M BIT_26 |
| /* Page Size of the Flash device */ |
| #define NFU_DCR_PAGE_SZ_MSK SHIFT24(0x3) |
| #define NFU_DCR_PAGE_SZ_BASE 24 |
| #define NFU_DCR_SEQ_DIS BIT_23 /* Sequential page read disable */ |
| /* NAND Flash Controller Clean Stop */ |
| #define NFU_DCR_ND_STOP BIT_22 |
| /* Force chip select false on busy */ |
| #define NFU_DCR_FORCE_CSX BIT_21 |
| #define NFU_DCR_CLR_PG_CNT BIT_20 /* Clear Page Count */ |
| #define NFU_DCR_STOP_ON_UNCOR BIT_19 /* Stop On Uncorrectable Error */ |
| #define NFU_DCR_RD_ID_CNT_MSK SHIFT16(0x7) /* Read ID Byte Count */ |
| #define NFU_DCR_RD_ID_CNT_BASE 16 |
| #define NFU_DCR_RA_START BIT_15 /* Row Address Start Position */ |
| #define NFU_DCR_PG_PER_BLK_MSK SHIFT13(0x3) /* Pages Per Block */ |
| #define NFU_DCR_PG_PER_BLK_BASE 13 |
| /* Data Flash Bus Arbiter Enable */ |
| #define NFU_DCR_ND_ARB_EN BIT_12 |
| /* Flash Device Ready Interrupt Mask */ |
| #define NFU_DCR_RDYM BIT_11 |
| /* ND_nCS0 Page Done Interrupt Mask */ |
| #define NFU_DCR_CS0_PAGEDM BIT_10 |
| /* ND_nCS1 Page Done Interrupt Mask */ |
| #define NFU_DCR_CS1_PAGEDM BIT_9 |
| /* ND_nCS0 Command Done Interrupt Mask */ |
| #define NFU_DCR_CS0_CMDDM BIT_8 |
| /* ND_nCS1 Command Done Interrupt Mask */ |
| #define NFU_DCR_CS1_CMDDM BIT_7 |
| /* ND_nCS0 Bad Block Detect Interrupt Mask */ |
| #define NFU_DCR_CS0_BBDM BIT_6 |
| /* ND_nCS1 Bad Block Detect Interrupt Mask */ |
| #define NFU_DCR_CS1_BBDM BIT_5 |
| /* ECC Failure Error Interrupt Mask */ |
| #define NFU_DCR_UNCERRM BIT_4 |
| /* Correctable Error Interrupt Mask */ |
| #define NFU_DCR_CORERRM BIT_3 |
| /* Write Data Request Interrupt Mask */ |
| #define NFU_DCR_WRDREQM BIT_2 |
| /* Read Data Request Interrupt Mask */ |
| #define NFU_DCR_RDDREQM BIT_1 |
| /* Write Command Request Interrupt Mask */ |
| #define NFU_DCR_WRCMDREQM BIT_0 |
| |
| /* NFU_DTR0CS0 0x0004 Data Controller Timing Parameter 0 Register for |
| * ND_nCS0 |
| */ |
| /* Bit(s) NFU_DTR0CS0_RSRV_31_27 reserved */ |
| #define NFU_DTR0CS0_SELCNTR BIT_26 /* Select Read Counter */ |
| #define NFU_DTR0CS0_RD_CNT_DEL_MSK SHIFT22(0xf) /* Read Strobe Count Delay */ |
| #define NFU_DTR0CS0_RD_CNT_DEL_BASE 22 |
| #define NFU_DTR0CS0_TCH_MSK SHIFT19(0x7) /* Enable Signal Hold Time */ |
| #define NFU_DTR0CS0_TCH_BASE 19 |
| #define NFU_DTR0CS0_TCS_MSK SHIFT16(0x7) /* Enable Signal Setup Time */ |
| #define NFU_DTR0CS0_TCS_BASE 16 |
| /* Bit(s) NFU_DTR0CS0_RSRV_15_14 reserved */ |
| #define NFU_DTR0CS0_TWH_MSK SHIFT11(0x7) /* ND_nWE high duration */ |
| #define NFU_DTR0CS0_TWH_BASE 11 |
| #define NFU_DTR0CS0_TWP_MSK SHIFT8(0x7) /* ND_nWE pulse width */ |
| #define NFU_DTR0CS0_TWP_BASE 8 |
| /* Bit(s) NFU_DTR0CS0_RSRV_7 reserved */ |
| #define NFU_DTR0CS0_ETRP BIT_6 /* Extended tRP */ |
| #define NFU_DTR0CS0_TRH_MSK SHIFT3(0x7) /* ND_nRE high duration */ |
| #define NFU_DTR0CS0_TRH_BASE 3 |
| #define NFU_DTR0CS0_TRP_MSK SHIFT0(0x7) /* ND_nRE pulse width */ |
| #define NFU_DTR0CS0_TRP_BASE 0 |
| |
| /* NFU_DTR1CS0 0x000C Data Controller Timing Parameter 1 Register for |
| * ND_nCS0 |
| */ |
| /* ND_nWE high to ND_nRE Low for Read */ |
| #define NFU_DTR1CS0_TR_MSK SHIFT16(0xffff) |
| #define NFU_DTR1CS0_TR_BASE 16 |
| #define NFU_DTR1CS0_WAIT_MODE BIT_15 /* Wait_Mode */ |
| /* Bit(s) NFU_DTR1CS0_RSRV_14_8 reserved */ |
| /* ND_nWE High to ND_nRE Low for a Read Status */ |
| #define NFU_DTR1CS0_TWHR_MSK SHIFT4(0xf) |
| #define NFU_DTR1CS0_TWHR_BASE 4 |
| /* ND_ALE Low to ND_nRE Low Delay */ |
| #define NFU_DTR1CS0_TAR_MSK SHIFT0(0xf) |
| #define NFU_DTR1CS0_TAR_BASE 0 |
| |
| /* NFU_DSR 0x0014 Data Controller Status Register */ |
| /* Bit(s) NFU_DSR_RSRV_31_21 reserved */ |
| #define NFU_DSR_ERR_CNT_MSK SHIFT16(0x1f) /* Block Error Count */ |
| #define NFU_DSR_ERR_CNT_BASE 16 |
| #define NFU_DSR_TRUSTVIO BIT_15 /* Trust Violation */ |
| /* Bit(s) NFU_DSR_RSRV_14_13 reserved */ |
| #define NFU_DSR_RDY BIT_12 /* RDY */ |
| #define NFU_DSR_NFRDY BIT_11 /* NAND Flash Ready */ |
| #define NFU_DSR_CS0_PAGED BIT_10 /* ND_nCS0 Page Done */ |
| #define NFU_DSR_CS1_PAGED BIT_9 /* ND_nCS1 Page Done */ |
| #define NFU_DSR_CS0_CMDD BIT_8 /* ND_nCS0 Command Done */ |
| #define NFU_DSR_CS1_CMDD BIT_7 /* ND_nCS1 Command Done */ |
| #define NFU_DSR_CS0_BBD BIT_6 /* ND_nCS0 Bad Block Detect */ |
| #define NFU_DSR_CS1_BBD BIT_5 /* ND_nCS1 Bad Block Detect */ |
| #define NFU_DSR_UNCERR BIT_4 /* Uncorrectable Error */ |
| #define NFU_DSR_CORERR BIT_3 /* Correctable Error */ |
| #define NFU_DSR_WRDREQ BIT_2 /* Write Data Request */ |
| #define NFU_DSR_RDDREQ BIT_1 /* Read Data Request */ |
| #define NFU_DSR_WRCMDREQ BIT_0 /* Write Command Request */ |
| |
| /* NFU_DPCR 0x0018 Data Controller Page Count Register */ |
| /* Bit(s) NFU_DPCR_RSRV_31_24 reserved */ |
| /* Page count for device interfaced using ND_nCS1 */ |
| #define NFU_DPCR_PG_CNT_1_MSK SHIFT16(0xff) |
| #define NFU_DPCR_PG_CNT_1_BASE 16 |
| /* Bit(s) NFU_DPCR_RSRV_15_8 reserved */ |
| /* Page count for device interfaced using ND_nCS0 */ |
| #define NFU_DPCR_PG_CNT_0_MSK SHIFT0(0xff) |
| #define NFU_DPCR_PG_CNT_0_BASE 0 |
| |
| /* NFU_DBBRx 0x001C Data Controller Bad Block Registers 0 and 1 */ |
| /* Bad Block Information */ |
| #define NFU_DBBRX_BAD_BLOCK_INFORMATION_MSK SHIFT0(0xffffffff) |
| #define NFU_DBBRX_BAD_BLOCK_INFORMATION_BASE 0 |
| |
| /* NFU_DREDEL 0x0024 Read Enable Return Delay Register */ |
| /* Bit(s) NFU_DREDEL_RSRV_31_28 reserved */ |
| #define NFU_DREDEL_ND_RE_SEL_MSK SHIFT24(0xf) /* nd_re_sel */ |
| #define NFU_DREDEL_ND_RE_SEL_BASE 24 |
| #define NFU_DREDEL_ND_RE_DEL_7_MSK SHIFT21(0x7) /* nd_re_del_7 */ |
| #define NFU_DREDEL_ND_RE_DEL_7_BASE 21 |
| #define NFU_DREDEL_ND_RE_DEL_6_MSK SHIFT18(0x7) /* nd_re_del_6 */ |
| #define NFU_DREDEL_ND_RE_DEL_6_BASE 18 |
| #define NFU_DREDEL_ND_RE_DEL_5_MSK SHIFT15(0x7) /* nd_re_del_5 */ |
| #define NFU_DREDEL_ND_RE_DEL_5_BASE 15 |
| #define NFU_DREDEL_ND_RE_DEL_4_MSK SHIFT12(0x7) /* nd_re_del_4 */ |
| #define NFU_DREDEL_ND_RE_DEL_4_BASE 12 |
| #define NFU_DREDEL_ND_RE_DEL_3_MSK SHIFT9(0x7) /* nd_re_del_3 */ |
| #define NFU_DREDEL_ND_RE_DEL_3_BASE 9 |
| #define NFU_DREDEL_ND_RE_DEL_2_MSK SHIFT6(0x7) /* nd_re_del_2 */ |
| #define NFU_DREDEL_ND_RE_DEL_2_BASE 6 |
| #define NFU_DREDEL_ND_RE_DEL_1_MSK SHIFT3(0x7) /* nd_re_del_1 */ |
| #define NFU_DREDEL_ND_RE_DEL_1_BASE 3 |
| #define NFU_DREDEL_ND_RE_DEL_0_MSK SHIFT0(0x7) /* nd_re_del_0 */ |
| #define NFU_DREDEL_ND_RE_DEL_0_BASE 0 |
| |
| /* NFU_DECCCTRL 0x0028 ECC Control Register */ |
| /* Bit(s) NFU_DECCCTRL_RSRV_31_15 reserved */ |
| /* ECC Bytes used in Spare Area */ |
| #define NFU_DECCCTRL_ECC_SPARE_MSK SHIFT7(0xff) |
| #define NFU_DECCCTRL_ECC_SPARE_BASE 7 |
| /* ECC Warning Threshold */ |
| #define NFU_DECCCTRL_ECC_THRESH_MSK SHIFT1(0x3f) |
| #define NFU_DECCCTRL_ECC_THRESH_BASE 1 |
| #define NFU_DECCCTRL_BCH_EN BIT_0 /* BCH Enable */ |
| |
| /* NFU_DBZCNT 0x002C Timer for ND_RnB0 and ND_RnB1 */ |
| #define NFU_DBZCNT_ND_RNBCNT1_MSK SHIFT6(0x3ffffff) /* RnB Busy Count 1 */ |
| #define NFU_DBZCNT_ND_RNBCNT1_BASE 6 |
| |
| /* NFU_DMUTEX 0x0030 NAND Controller MUTEX Lock Register */ |
| /* Bit(s) NFU_DMUTEX_RSRV_31_1 reserved */ |
| #define NFU_DMUTEX_MUTEX BIT_0 /* Mutex lock */ |
| |
| /* NFU_DCMDMAT 0x0034 Partition Command Match Registers */ |
| #define NFU_DCMDMAT_VALIDCNT_MSK SHIFT30(0x3) /* Valid Count */ |
| #define NFU_DCMDMAT_VALIDCNT_BASE 30 |
| #define NFU_DCMDMAT_NAKEDDIS2 BIT_29 /* Naked Disallow */ |
| #define NFU_DCMDMAT_ROWADD2 BIT_28 /* Row Address */ |
| #define NFU_DCMDMAT_CMD_MSK2 SHIFT20(0xff) /* Command Match */ |
| #define NFU_DCMDMAT_CMD_BASE2 20 |
| #define NFU_DCMDMAT_NAKEDDIS1 BIT_19 /* Naked Disallow */ |
| #define NFU_DCMDMAT_ROWADD1 BIT_18 /* Row Address */ |
| #define NFU_DCMDMAT_CMD_MSK1 SHIFT10(0xff) /* Command Match */ |
| #define NFU_DCMDMAT_CMD_BASE1 10 |
| #define NFU_DCMDMAT_NAKEDDIS0 BIT_9 /* Naked Disallow */ |
| #define NFU_DCMDMAT_ROWADD0 BIT_8 /* Row Address */ |
| #define NFU_DCMDMAT_CMD_MSK0 SHIFT0(0xff) /* Command Match */ |
| #define NFU_DCMDMAT_CMD_BASE0 0 |
| |
| /* NFU_DDB 0x0040 Data Controller Data Buffer Register */ |
| #define NFU_DDB_NAND_FLASH_DATA_MSK SHIFT0(0xffffffff) /* NAND flash data */ |
| #define NFU_DDB_NAND_FLASH_DATA_BASE 0 |
| |
| /* NFU_DCB0 0x0048 Data Controller Command Buffer 0 */ |
| #define NFU_DCB0_CMD_XTYPE_MSK SHIFT29(0x7) /* Command Extended Type */ |
| #define NFU_DCB0_CMD_XTYPE_BASE 29 |
| #define NFU_DCB0_LEN_OVRD BIT_28 /* Length Override */ |
| #define NFU_DCB0_RDY_BYP BIT_27 /* Ready Bypass */ |
| #define NFU_DCB0_ST_ROW_EN BIT_26 /* Status Row Address Enable */ |
| #define NFU_DCB0_AUTO_RS BIT_25 /* Auto Read Status */ |
| #define NFU_DCB0_CSEL BIT_24 /* CS Select */ |
| #define NFU_DCB0_CMD_TYPE_MSK SHIFT21(0x7) /* Command Type */ |
| #define NFU_DCB0_CMD_TYPE_BASE 21 |
| #define NFU_DCB0_NC BIT_20 /* NC */ |
| #define NFU_DCB0_DBC BIT_19 /* Double Byte Command */ |
| #define NFU_DCB0_ADDR_CYC_MSK SHIFT16(0x7) /* Number of Address Cycles */ |
| #define NFU_DCB0_ADDR_CYC_BASE 16 |
| #define NFU_DCB0_CMD2_MSK SHIFT8(0xff) /* Second command */ |
| #define NFU_DCB0_CMD2_BASE 8 |
| #define NFU_DCB0_CMD1_MSK SHIFT0(0xff) /* First command */ |
| #define NFU_DCB0_CMD1_BASE 0 |
| |
| /* NDCB1 0x004C Data Controller Command Buffer 1 */ |
| #define NDCB1_ADDR4_MSK SHIFT24(0xff) /* ADDR4 */ |
| #define NDCB1_ADDR4_BASE 24 |
| #define NDCB1_ADDR3_MSK SHIFT16(0xff) /* ADDR3 */ |
| #define NDCB1_ADDR3_BASE 16 |
| #define NDCB1_ADDR2_MSK SHIFT8(0xff) /* ADDR2 */ |
| #define NDCB1_ADDR2_BASE 8 |
| #define NDCB1_ADDR1_MSK SHIFT0(0xff) /* ADDR1 */ |
| #define NDCB1_ADDR1_BASE 0 |
| |
| /* NDCB2 0x0050 Data Controller Command Buffer 2 */ |
| #define NDCB2_ST_MASK_MSK SHIFT24(0xff) /* Status Mask */ |
| #define NDCB2_ST_MASK_BASE 24 |
| #define NDCB2_ST_CMD_MSK SHIFT16(0xff) /* Status Command */ |
| #define NDCB2_ST_CMD_BASE 16 |
| #define NDCB2_PAGE_COUNT_MSK SHIFT8(0xff) /* Page Count */ |
| #define NDCB2_PAGE_COUNT_BASE 8 |
| #define NDCB2_ADDR5_MSK SHIFT0(0xff) /* ADDR5 */ |
| #define NDCB2_ADDR5_BASE 0 |
| |
| /* NDCB3 0x0054 Data Controller Command Buffer 3 */ |
| #define NDCB3_ADDR7_MSK SHIFT24(0xff) /* ADDR7 */ |
| #define NDCB3_ADDR7_BASE 24 |
| #define NDCB3_ADDR6_MSK SHIFT16(0xff) /* ADDR6 */ |
| #define NDCB3_ADDR6_BASE 16 |
| #define NDCB3_NDLENCNT_MSK SHIFT0(0xffff) /* NDLENCNT */ |
| #define NDCB3_NDLENCNT_BASE 0 |
| |
| /* NDARBCR 0x005C NAND DFI Arbitration Control Register */ |
| /* Bit(s) NDARBCR_RSRV_31_16 reserved */ |
| #define NDARBCR_ARB_CNT_MSK SHIFT0(0xffff) /* Arbitration Count */ |
| #define NDARBCR_ARB_CNT_BASE 0 |
| |
| /* NDPTXCSX 0x0060 Partition Region Control Registers for CS0 and CS1 */ |
| //#define NDPTXCSX_VALID BIT_31 /* Valid Entry */ |
| //#define NDPTXCSX_LOCK BIT_30 /* Lock Entry */ |
| #define NDPTXCSX_TRUSTED BIT_29 /* Trusted Region */ |
| /* Bit(s) NDPTXCSX_RSRV_28_24 reserved */ |
| #define NDPTXCSX_BLOCKADD_MSK SHIFT0(0xffffff) /* Block Address */ |
| #define NDPTXCSX_BLOCKADD_BASE 0 |
| |
| |
| |
| /* -------------------- */ |
| |
| |
| #endif /* __INC_NFC_H */ |