marvell/obm/Common/Platforms/NZA3/geu_extras.h - T108 - Gitiles

 /******************************************************************************
  *
  *  (C)Copyright 2005 - 2011 Marvell. All Rights Reserved.
  *
  *  THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL.
  *  The copyright notice above does not evidence any actual or intended
  *  publication of such source code.
  *  This Module contains Proprietary Information of Marvell and should be
  *  treated as Confidential.
  *  The information in this file is provided for the exclusive use of the
  *  licensees of Marvell.
  *  Such users have the right to use, modify, and incorporate this code into
  *  products for purposes authorized by the license agreement provided they
  *  include this notice and the associated copyright notice with any such
  *  product.
  *  The information in this file is provided "AS IS" without warranty.

  ******************************************************************************/

 #ifndef __GEU_EXTRAS__
 #define __GEU_EXTRAS__

 #include "GEU.h"

 #define GEU_FUSE_VAL_LIFECYCLE_DM_CM  					(GEU_BLOCK0_RESERVED_1)		// (GEU_BASE + 0x420) Block 0 Reserved Fuse Bit Register 1
 #define GEU_FUSE_VAL_APCPMP_ECC 						(GEU_AP_CP_MP_ECC)			// (GEU_BASE + 0x41C) AP_CP_MP ECC bits
 #define GEU_FUSE_VAL_OEM_HASH_KEY0						(GEU_FUSE_VAL_OEM_HASH_KEY)	// (GEU_BASE + 0x444) Fuse Value for OEM Hash Key Registers 1- 8
 #define GEU_FUSE_VAL_OEM_JTAG_HASH_KEY0                 (GEU_FUSE_VAL_OEM_JTAG_HASH)// (GEU_BASE + 0x464) Fuse Value for OEM JTAG Key Hash Registers 1- 8
 #define	GEU_FUSE_VAL_SECURITY_CONFIG					(GEU_BLOCK7_RESERVED_0)		// (GEU_BASE + 0x490) Block 7 Reserved Fuse Bit Register 0
 #define GEU_FUSE_VAL_LIFECYCLE_JPD_FA_DD_OEM_UID_ECC	(GEU_BLOCK7_RESERVED_5)		// (GEU_BASE + 0x4A4) Block 7 Reserved Fuse Bit Register 5

 #define	GEU_FUSE_VAL_USB_VER_ID							(GEU_BLOCK7_RESERVED_1)	   	// (GEU_BASE + 0x494) Block 7 Reserved Fuse Bit Register 1
 #define	GEU_FUSE_VAL_SECURITY_USB_ECC					(GEU_BLOCK7_RESERVED_2)	   	// (GEU_BASE + 0x498) Block 7 Reserved Fuse Bit Register 2
 #define	GEU_FUSE_VAL_OEM_KEY0_HASH_ECC					(GEU_BLOCK7_RESERVED_3)	   	// (GEU_BASE + 0x49C) Block 7 Reserved Fuse Bit Register 3
 #define GEU_FUSE_VAL_LIFECYCLE_JPD_FA_DD_OEM_UID_ECC	(GEU_BLOCK7_RESERVED_5)		// (GEU_BASE + 0x4A4) Block 7 Reserved Fuse Bit Register 5
 #define GEU_ECC_STATUS0									(GEU_ECC_STATUS)			// (GEU_BASE + 0x4C4) ECC Status Register

 #define REGULATOR_CNT_REG (GEU_REGULATOR_CNT_REG)
 #define FUSE_SCLK_DIV_CNTR (GEU_FUSE_SCLK_DIV_CNTR)


 #define JPD_FA_DD_MASK					(0x01FF)			//bits [8:0] @ GEU_BASE + 0x01A4
 #define JPD_FA_DD_OFFSET				(0x0)
 #define GEU_SECURITY_USB_ECC_MASK		(SHIFT0(0x000000FF))
 #define GEU_AP_CP_MP_ECC_MASK			(SHIFT0(0x00FFFFFF))


 // Block 0 GEU_LIFECYCLE_CM_DM					0x0420	GEU_LIFECYCLE CM_DM_Reserved Fuse Bit Register 1
 #define GEU_FUSE_VAL_LIFECYCLE_DM_MSK       (SHIFT3(0x7))
 #define GEU_FUSE_VAL_LIFECYCLE_DM_BASE      3
 #define GEU_FUSE_VAL_LIFECYCLE_CM_MSK       (SHIFT0(0x7))
 #define GEU_FUSE_VAL_LIFECYCLE_CM_BASE      0
 #define GEU_FUSE_VAL_LIFECYCLE_DM_CM_MASK   (GEU_FUSE_VAL_LIFECYCLE_CM_MSK | GEU_FUSE_VAL_LIFECYCLE_DM_MSK)

 // Block 7 Register 5
 #define GEU_FUSE_VAL_LIFECYCLE_DD_MSK                (SHIFT0(0x7))
 #define GEU_FUSE_VAL_LIFECYCLE_DD_BASE               0
 #define GEU_FUSE_VAL_LIFECYCLE_FA_MSK                (SHIFT3(0x7))
 #define GEU_FUSE_VAL_LIFECYCLE_FA_BASE               3
 #define GEU_FUSE_VAL_LIFECYCLE_JPD_MSK               (SHIFT6(0x7))
 #define GEU_FUSE_VAL_LIFECYCLE_JPD_BASE              6
 #define GEU_OEM_UID_ECC_MSK                 (SHIFT24(0xFF))
 #define GEU_OEM_UID_ECC_BASE                24


 /*	GEU_ECC_STATUS_0						0x04C4	ECC Status Register */
 #define	GEU_ECC_STATUS0_FB7_255_192_OEM_UID_MSK 					SHIFT30(0x3)	/* Error Type C */
 #define	GEU_ECC_STATUS0_FB7_255_192_OEM_UID_BASE					30
 #define GEU_ECC_STATUS0_FB7_255_192_OEM_UID_UNCORRECTABLE_ERR_MSK	SHIFT30(0x2)

 #define	GEU_ECC_STATUS0_FB7_63_0_USBID_SECCFG_MSK			  		SHIFT28(0x3)	/* Error Type B */
 #define	GEU_ECC_STATUS0_FB7_63_0_USBID_SECCFG_BASE					28
 #define	GEU_ECC_STATUS0_FB7_63_0_USBID_SECCFG_UNCORRECTABLE_ERR_MSK	SHIFT28(0x2)


 #define	GEU_ECC_STATUS0_FB0_191_128_MP0_APCPCFG_MSK					SHIFT26(0x3)	/* Error Type A */
 #define	GEU_ECC_STATUS0_FB0_191_128_MP0_APCPCFG_BASE				26
 #define	GEU_ECC_STATUS0_FB0_191_128_MP0_APCPCFG_UNCORRECTABLE_ERR_MSK		SHIFT26(0x2)

 #define	GEU_ECC_STATUS0_FB0_127_64_MP0_APCPCFG_MSK					SHIFT24(0x3)	/* Error Type 9 */
 #define	GEU_ECC_STATUS0_FB0_127_64_MP0_APCPCFG_BASE					24
 #define	GEU_ECC_STATUS0_FB0_127_64_MP0_APCPCFG_UNCORRECTABLE_ERR_MSK	SHIFT24(0x2)

 #define	GEU_ECC_STATUS0_FB0_63_0_MP0_APCPCFG_MSK				   SHIFT22(0x3)	/* Error Type 8 */
 #define	GEU_ECC_STATUS0_FB0_63_0_MP0_APCPCFG_BASE				   22
 #define	GEU_ECC_STATUS0_FB0_63_0_MP0_APCPCFG_UNCORRECTABLE_ERR_MSK SHIFT22(0x2)

 #define	GEU_ECC_STATUS0_FB6_255_192_JTAG_KEY0_MSK					SHIFT20(0x3)	/* Error Type 7 */
 #define	GEU_ECC_STATUS0_FB6_255_192_JTAG_KEY0_BASE					20
 #define	GEU_ECC_STATUS0_FB6_255_192_JTAG_KEY0_UNCORRECTABLE_ERR_MSK	SHIFT20(0x2)

 #define	GEU_ECC_STATUS0_FB6_191_128_JTAG_KEY0_MSK					SHIFT18(0x3)	/* Error Type 6 */
 #define	GEU_ECC_STATUS0_FB6_191_128_JTAG_KEY0_BASE					18
 #define	GEU_ECC_STATUS0_FB6_191_128_JTAG_KEY0_UNCORRECTABLE_ERR_MSK	SHIFT18(0x2)

 #define	GEU_ECC_STATUS0_FB6_127_64_JTAG_KEY0_MSK					SHIFT16(0x3)	/* Error Type 5 */
 #define	GEU_ECC_STATUS0_FB6_127_64_JTAG_KEY0_BASE					16
 #define	GEU_ECC_STATUS0_FB6_127_64_JTAG_KEY0_UNCORRECTABLE_ERR_MSK SHIFT16(0x2)

 #define	GEU_ECC_STATUS0_FB6_63_0_JTAG_KEY0_MSK						SHIFT14(0x3)	/* Error Type 4 */
 #define	GEU_ECC_STATUS0_FB6_63_0_JTAG_KEY0_BASE						14
 #define	GEU_ECC_STATUS0_FB6_63_0_JTAG_KEY0_UNCORRECTABLE_ERR_MSK	SHIFT14(0x2)

 #define	GEU_ECC_STATUS0_FB2_255_192_OEM_KEY0_MSK					SHIFT12(0x3)	/* Error Type 3 */
 #define	GEU_ECC_STATUS0_FB2_255_192_OEM_KEY0_BASE					12
 #define	GEU_ECC_STATUS0_FB2_255_192_OEM_KEY0_UNCORRECTABLE_ERR_MSK	SHIFT12(0x2)

 #define	GEU_ECC_STATUS0_FB2_191_128_OEM_KEY0_MSK					SHIFT8(0x3)		/* Error Type 2 */
 #define	GEU_ECC_STATUS0_FB2_191_128_OEM_KEY0_BASE					8
 #define	GEU_ECC_STATUS0_FB2_191_128_OEM_KEY0_UNCORRECTABLE_ERR_MSK	SHIFT8(0x2)

 #define	GEU_ECC_STATUS0_FB2_127_64_OEM_KEY0_MSK						SHIFT4(0x3)		/* Error Type 1 */
 #define	GEU_ECC_STATUS0_FB2_127_64_OEM_KEY0_BASE					4
 #define	GEU_ECC_STATUS0_FB2_127_64_OEM_KEY0_UNCORRECTABLE_ERR_MSK 	SHIFT4(0x2)

 #define	GEU_ECC_STATUS0_FB2_63_0_OEM_KEY0_MSK						SHIFT0(0x3)		/* Error Type 0 */
 #define	GEU_ECC_STATUS0_FB2_63_0_OEM_KEY0_BASE						0
 #define	GEU_ECC_STATUS0_FB2_63_0_OEM_KEY0_UNCORRECTABLE_ERR_MSK		SHIFT0(0x2)
 //--

 #define	GEU_FUSE_VAL_SECURITY_CONFIG					(GEU_BLOCK7_RESERVED_0)
 #define	GEU_FUSE_VAL_USB_VER_ID							(GEU_BLOCK7_RESERVED_1)
 #define	GEU_FUSE_VAL_SECURITY_USB_ECC					(GEU_BLOCK7_RESERVED_2)
 #define	GEU_FUSE_VAL_OEM_KEY_ECC						(GEU_BLOCK7_RESERVED_3)
 #define	GEU_FUSE_VAL_OEM_JTAG_KEY_HASH_ECC				(GEU_BLOCK7_RESERVED_4)
 #define	GEU_FUSE_VAL_LIFECYCLE_JPD_FA_DD_OEM_UID_ECC	(GEU_BLOCK7_RESERVED_5)


 #endif	/* __GEU_EXTRAS_H */
	/******************************************************************************
	*
	* (C)Copyright 2005 - 2011 Marvell. All Rights Reserved.
	*
	* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL.
	* The copyright notice above does not evidence any actual or intended
	* publication of such source code.
	* This Module contains Proprietary Information of Marvell and should be
	* treated as Confidential.
	* The information in this file is provided for the exclusive use of the
	* licensees of Marvell.
	* Such users have the right to use, modify, and incorporate this code into
	* products for purposes authorized by the license agreement provided they
	* include this notice and the associated copyright notice with any such
	* product.
	* The information in this file is provided "AS IS" without warranty.

	******************************************************************************/

	#ifndef __GEU_EXTRAS__
	#define __GEU_EXTRAS__

	#include "GEU.h"

	#define GEU_FUSE_VAL_LIFECYCLE_DM_CM (GEU_BLOCK0_RESERVED_1) // (GEU_BASE + 0x420) Block 0 Reserved Fuse Bit Register 1
	#define GEU_FUSE_VAL_APCPMP_ECC (GEU_AP_CP_MP_ECC) // (GEU_BASE + 0x41C) AP_CP_MP ECC bits
	#define GEU_FUSE_VAL_OEM_HASH_KEY0 (GEU_FUSE_VAL_OEM_HASH_KEY) // (GEU_BASE + 0x444) Fuse Value for OEM Hash Key Registers 1- 8
	#define GEU_FUSE_VAL_OEM_JTAG_HASH_KEY0 (GEU_FUSE_VAL_OEM_JTAG_HASH)// (GEU_BASE + 0x464) Fuse Value for OEM JTAG Key Hash Registers 1- 8
	#define GEU_FUSE_VAL_SECURITY_CONFIG (GEU_BLOCK7_RESERVED_0) // (GEU_BASE + 0x490) Block 7 Reserved Fuse Bit Register 0
	#define GEU_FUSE_VAL_LIFECYCLE_JPD_FA_DD_OEM_UID_ECC (GEU_BLOCK7_RESERVED_5) // (GEU_BASE + 0x4A4) Block 7 Reserved Fuse Bit Register 5

	#define GEU_FUSE_VAL_USB_VER_ID (GEU_BLOCK7_RESERVED_1) // (GEU_BASE + 0x494) Block 7 Reserved Fuse Bit Register 1
	#define GEU_FUSE_VAL_SECURITY_USB_ECC (GEU_BLOCK7_RESERVED_2) // (GEU_BASE + 0x498) Block 7 Reserved Fuse Bit Register 2
	#define GEU_FUSE_VAL_OEM_KEY0_HASH_ECC (GEU_BLOCK7_RESERVED_3) // (GEU_BASE + 0x49C) Block 7 Reserved Fuse Bit Register 3
	#define GEU_FUSE_VAL_LIFECYCLE_JPD_FA_DD_OEM_UID_ECC (GEU_BLOCK7_RESERVED_5) // (GEU_BASE + 0x4A4) Block 7 Reserved Fuse Bit Register 5
	#define GEU_ECC_STATUS0 (GEU_ECC_STATUS) // (GEU_BASE + 0x4C4) ECC Status Register

	#define REGULATOR_CNT_REG (GEU_REGULATOR_CNT_REG)
	#define FUSE_SCLK_DIV_CNTR (GEU_FUSE_SCLK_DIV_CNTR)


	#define JPD_FA_DD_MASK (0x01FF) //bits [8:0] @ GEU_BASE + 0x01A4
	#define JPD_FA_DD_OFFSET (0x0)
	#define GEU_SECURITY_USB_ECC_MASK (SHIFT0(0x000000FF))
	#define GEU_AP_CP_MP_ECC_MASK (SHIFT0(0x00FFFFFF))


	// Block 0 GEU_LIFECYCLE_CM_DM 0x0420 GEU_LIFECYCLE CM_DM_Reserved Fuse Bit Register 1
	#define GEU_FUSE_VAL_LIFECYCLE_DM_MSK (SHIFT3(0x7))
	#define GEU_FUSE_VAL_LIFECYCLE_DM_BASE 3
	#define GEU_FUSE_VAL_LIFECYCLE_CM_MSK (SHIFT0(0x7))
	#define GEU_FUSE_VAL_LIFECYCLE_CM_BASE 0
	#define GEU_FUSE_VAL_LIFECYCLE_DM_CM_MASK (GEU_FUSE_VAL_LIFECYCLE_CM_MSK \| GEU_FUSE_VAL_LIFECYCLE_DM_MSK)

	// Block 7 Register 5
	#define GEU_FUSE_VAL_LIFECYCLE_DD_MSK (SHIFT0(0x7))
	#define GEU_FUSE_VAL_LIFECYCLE_DD_BASE 0
	#define GEU_FUSE_VAL_LIFECYCLE_FA_MSK (SHIFT3(0x7))
	#define GEU_FUSE_VAL_LIFECYCLE_FA_BASE 3
	#define GEU_FUSE_VAL_LIFECYCLE_JPD_MSK (SHIFT6(0x7))
	#define GEU_FUSE_VAL_LIFECYCLE_JPD_BASE 6
	#define GEU_OEM_UID_ECC_MSK (SHIFT24(0xFF))
	#define GEU_OEM_UID_ECC_BASE 24


	/* GEU_ECC_STATUS_0 0x04C4 ECC Status Register */
	#define GEU_ECC_STATUS0_FB7_255_192_OEM_UID_MSK SHIFT30(0x3) /* Error Type C */
	#define GEU_ECC_STATUS0_FB7_255_192_OEM_UID_BASE 30
	#define GEU_ECC_STATUS0_FB7_255_192_OEM_UID_UNCORRECTABLE_ERR_MSK SHIFT30(0x2)

	#define GEU_ECC_STATUS0_FB7_63_0_USBID_SECCFG_MSK SHIFT28(0x3) /* Error Type B */
	#define GEU_ECC_STATUS0_FB7_63_0_USBID_SECCFG_BASE 28
	#define GEU_ECC_STATUS0_FB7_63_0_USBID_SECCFG_UNCORRECTABLE_ERR_MSK SHIFT28(0x2)


	#define GEU_ECC_STATUS0_FB0_191_128_MP0_APCPCFG_MSK SHIFT26(0x3) /* Error Type A */
	#define GEU_ECC_STATUS0_FB0_191_128_MP0_APCPCFG_BASE 26
	#define GEU_ECC_STATUS0_FB0_191_128_MP0_APCPCFG_UNCORRECTABLE_ERR_MSK SHIFT26(0x2)

	#define GEU_ECC_STATUS0_FB0_127_64_MP0_APCPCFG_MSK SHIFT24(0x3) /* Error Type 9 */
	#define GEU_ECC_STATUS0_FB0_127_64_MP0_APCPCFG_BASE 24
	#define GEU_ECC_STATUS0_FB0_127_64_MP0_APCPCFG_UNCORRECTABLE_ERR_MSK SHIFT24(0x2)

	#define GEU_ECC_STATUS0_FB0_63_0_MP0_APCPCFG_MSK SHIFT22(0x3) /* Error Type 8 */
	#define GEU_ECC_STATUS0_FB0_63_0_MP0_APCPCFG_BASE 22
	#define GEU_ECC_STATUS0_FB0_63_0_MP0_APCPCFG_UNCORRECTABLE_ERR_MSK SHIFT22(0x2)

	#define GEU_ECC_STATUS0_FB6_255_192_JTAG_KEY0_MSK SHIFT20(0x3) /* Error Type 7 */
	#define GEU_ECC_STATUS0_FB6_255_192_JTAG_KEY0_BASE 20
	#define GEU_ECC_STATUS0_FB6_255_192_JTAG_KEY0_UNCORRECTABLE_ERR_MSK SHIFT20(0x2)

	#define GEU_ECC_STATUS0_FB6_191_128_JTAG_KEY0_MSK SHIFT18(0x3) /* Error Type 6 */
	#define GEU_ECC_STATUS0_FB6_191_128_JTAG_KEY0_BASE 18
	#define GEU_ECC_STATUS0_FB6_191_128_JTAG_KEY0_UNCORRECTABLE_ERR_MSK SHIFT18(0x2)

	#define GEU_ECC_STATUS0_FB6_127_64_JTAG_KEY0_MSK SHIFT16(0x3) /* Error Type 5 */
	#define GEU_ECC_STATUS0_FB6_127_64_JTAG_KEY0_BASE 16
	#define GEU_ECC_STATUS0_FB6_127_64_JTAG_KEY0_UNCORRECTABLE_ERR_MSK SHIFT16(0x2)

	#define GEU_ECC_STATUS0_FB6_63_0_JTAG_KEY0_MSK SHIFT14(0x3) /* Error Type 4 */
	#define GEU_ECC_STATUS0_FB6_63_0_JTAG_KEY0_BASE 14
	#define GEU_ECC_STATUS0_FB6_63_0_JTAG_KEY0_UNCORRECTABLE_ERR_MSK SHIFT14(0x2)

	#define GEU_ECC_STATUS0_FB2_255_192_OEM_KEY0_MSK SHIFT12(0x3) /* Error Type 3 */
	#define GEU_ECC_STATUS0_FB2_255_192_OEM_KEY0_BASE 12
	#define GEU_ECC_STATUS0_FB2_255_192_OEM_KEY0_UNCORRECTABLE_ERR_MSK SHIFT12(0x2)

	#define GEU_ECC_STATUS0_FB2_191_128_OEM_KEY0_MSK SHIFT8(0x3) /* Error Type 2 */
	#define GEU_ECC_STATUS0_FB2_191_128_OEM_KEY0_BASE 8
	#define GEU_ECC_STATUS0_FB2_191_128_OEM_KEY0_UNCORRECTABLE_ERR_MSK SHIFT8(0x2)

	#define GEU_ECC_STATUS0_FB2_127_64_OEM_KEY0_MSK SHIFT4(0x3) /* Error Type 1 */
	#define GEU_ECC_STATUS0_FB2_127_64_OEM_KEY0_BASE 4
	#define GEU_ECC_STATUS0_FB2_127_64_OEM_KEY0_UNCORRECTABLE_ERR_MSK SHIFT4(0x2)

	#define GEU_ECC_STATUS0_FB2_63_0_OEM_KEY0_MSK SHIFT0(0x3) /* Error Type 0 */
	#define GEU_ECC_STATUS0_FB2_63_0_OEM_KEY0_BASE 0
	#define GEU_ECC_STATUS0_FB2_63_0_OEM_KEY0_UNCORRECTABLE_ERR_MSK SHIFT0(0x2)
	//--

	#define GEU_FUSE_VAL_SECURITY_CONFIG (GEU_BLOCK7_RESERVED_0)
	#define GEU_FUSE_VAL_USB_VER_ID (GEU_BLOCK7_RESERVED_1)
	#define GEU_FUSE_VAL_SECURITY_USB_ECC (GEU_BLOCK7_RESERVED_2)
	#define GEU_FUSE_VAL_OEM_KEY_ECC (GEU_BLOCK7_RESERVED_3)
	#define GEU_FUSE_VAL_OEM_JTAG_KEY_HASH_ECC (GEU_BLOCK7_RESERVED_4)
	#define GEU_FUSE_VAL_LIFECYCLE_JPD_FA_DD_OEM_UID_ECC (GEU_BLOCK7_RESERVED_5)


	#endif /* __GEU_EXTRAS_H */