| /****************************************************************************** |
| * |
| * Name: USB_controller.h |
| * Project: Hermon-2 |
| * Purpose: Testing |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * (C)Copyright 2005 - 2011 Marvell. All Rights Reserved. |
| * |
| * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL. |
| * The copyright notice above does not evidence any actual or intended |
| * publication of such source code. |
| * This Module contains Proprietary Information of Marvell and should be |
| * treated as Confidential. |
| * The information in this file is provided for the exclusive use of the |
| * licensees of Marvell. |
| * Such users have the right to use, modify, and incorporate this code into |
| * products for purposes authorized by the license agreement provided they |
| * include this notice and the associated copyright notice with any such |
| * product. |
| * The information in this file is provided "AS IS" without warranty. |
| |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * This file was automatically generated by reg.pl using * USB1.csv |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * History: |
| * |
| ********* PLEASE INSERT THE CVS HISTORY OF THE PREVIOUS VERSION HERE. ********* |
| *******************************************************************************/ |
| |
| #ifndef __INC_USB_controller_H |
| #define __INC_USB_controller_H |
| |
| |
| /* |
| * |
| * THE BASE ADDRESSES |
| * |
| */ |
| #define UTMI_BASE 0xD4207100 |
| #define USB_BASE 0xD4208000 |
| |
| /* |
| * |
| * THE REGISTER DEFINES |
| * |
| */ |
| #define USB_ID (USB_BASE+0x0000) /* 32 bit |
| * Identification |
| * Register |
| */ |
| #define USB_HWGENERAL (USB_BASE+0x0004) /* 32 bit General |
| * Hardware |
| * Parameters |
| * Register |
| */ |
| #define USB_HWHOST (USB_BASE+0x0008) /* 32 bit Host |
| * Hardware |
| * Parameters |
| * Register |
| */ |
| #define USB_HWDEVICE (USB_BASE+0x000C) /* 32 bit Device |
| * Hardware |
| * Parameters |
| * Register |
| */ |
| #define USB_HWTXBUF (USB_BASE+0x0010) /* 32 bit TX Buffer |
| * Hardware |
| * Parameters |
| * Register |
| */ |
| #define USB_HWRXBUF (USB_BASE+0x0014) /* 32 bit RX Buffer |
| * Hardware |
| * Parameters |
| * Register |
| */ |
| #define USB_CAPLENGTH (USB_BASE+0x0100) /* 16 bit Capability |
| * Register |
| * Length - |
| * EHCI |
| * Compliant |
| * Register |
| */ |
| #define USB_HCSPARAMS (USB_BASE+0x0104) /* 32 bit Host Ctrl. |
| * Structural |
| * Parameters |
| * EHCI |
| * Compliant |
| * with |
| */ |
| #define USB_HCCPARAMS (USB_BASE+0x0108) /* 32 bit Host Ctrl. |
| * Capability |
| * Parameters |
| * EHCI |
| * Compliant |
| */ |
| #define USB_DCIVERSION (USB_BASE+0x0120) /* 32 bit Dev. |
| * Interface |
| * Version |
| * Number |
| * Register |
| */ |
| #define USB_DCCPARAMS (USB_BASE+0x0124) /* 32 bit Device |
| * Ctrl. |
| * Capability |
| * Parameters |
| * Register |
| */ |
| #define USB_CMD (USB_BASE+0x0140) /* 32 bit USB Command |
| * Register |
| */ |
| #define USB_STS (USB_BASE+0x0144) /* 32 bit USB Status |
| * Register |
| */ |
| #define USB_INTR (USB_BASE+0x0148) /* 32 bit USB |
| * Interrupt |
| * Enable |
| * Register |
| */ |
| #define USB_FRINDEX (USB_BASE+0x014C) /* 32 bit USB Frame |
| * Index |
| * Register |
| */ |
| #define USB_PERIODICLISTBASE (USB_BASE+0x0154) /* 32 bit Host |
| * Controller |
| * Frame |
| * List Base |
| * Address |
| * Register |
| * (Host |
| * Mode) |
| */ |
| #define USB_DEVICEADDR (USB_BASE+0x0154) /* 32 bit Device |
| * Controller |
| * USB |
| * Device |
| * Address |
| * Register |
| * (Device |
| * Mode) |
| */ |
| #define USB_ASYNCLISTADDR (USB_BASE+0x0158) /* 32 bit Host |
| * Controller |
| * Next |
| * Asynchronous |
| * List |
| * Address |
| * Register |
| */ |
| #define USB_ENDPOINTLISTADDR (USB_BASE+0x0158) /* 32 bit Address at |
| * Endpoint |
| * List in |
| * Memory |
| * Register |
| */ |
| #define USB_BURSTSIZE (USB_BASE+0x0160) /* 32 bit |
| * Programmable |
| * Burst |
| * Size |
| * Register |
| * - Host |
| * Controller |
| */ |
| #define USB_ENDPTNAK (USB_BASE+0x0178) /* 32 bit Endpoint |
| * NAK |
| * Register |
| */ |
| #define USB_ENDPTNAKEN (USB_BASE+0x017C) /* 32 bit Endpoint |
| * NAK |
| * Enable |
| * Register |
| */ |
| #define USB_PORTSC (USB_BASE+0x0184) /* 32 bit Port |
| * Status/Control |
| * Register |
| */ |
| #define USB_OTGSC (USB_BASE+0x01A4) /* 32 bit OTG Status |
| * and |
| * Control |
| * Register |
| */ |
| #define USB_MODE (USB_BASE+0x01A8) /* 32 bit USB Device |
| * Mode |
| * Register |
| */ |
| #define USB_ENDPTSETUPSTAT (USB_BASE+0x01AC) /* 32 bit Endpoint |
| * Setup |
| * Status |
| * Register |
| */ |
| #define USB_ENDPTPRIME (USB_BASE+0x01B0) /* 32 bit Endpoint |
| * Initialization |
| * Register |
| */ |
| #define USB_ENDPTFLUSH (USB_BASE+0x01B4) /* 32 bit Endpoint |
| * De-Initialize |
| * Register |
| */ |
| #define USB_ENDPTSTAT (USB_BASE+0x01B8) /* 32 bit Endpoint |
| * STAT |
| * Register |
| */ |
| #define USB_ENDPTCOMPLETE (USB_BASE+0x01BC) /* 32 bit Endpoint |
| * Complete |
| * Register |
| */ |
| #define USB_ENDPTCTRL0 (USB_BASE+0x01C0) /* 32 bit Endpoint |
| * Control 0 |
| * Register |
| */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3 (USB_BASE+0x01C4) /* Endpoint Control 1 to |
| * Endpoint |
| * Control 3 |
| * Registers |
| * Start |
| */ |
| #define UTMI_CTRL (UTMI_BASE+0x0004) /* 32 bit USB Control |
| * Register |
| */ |
| #define UTMI_PLL (UTMI_BASE+0x0008) /* 32 bit PLL Register */ |
| #define UTMI_TX (UTMI_BASE+0x000C) /* 32 bit Tx Register */ |
| #define UTMI_RX (UTMI_BASE+0x0010) /* 32 bit Rx Register */ |
| #define UTMI_IVREF (UTMI_BASE+0x0014) /* 32 bit IVREF |
| * Register |
| */ |
| #define UTMI_TEST_GRP_0 (UTMI_BASE+0x0018) /* 32 bit Test Group |
| * 0 Register |
| */ |
| #define UTMI_TEST_GRP_1 (UTMI_BASE+0x001C) /* 32 bit Test Group |
| * 1 Register |
| */ |
| #define UTMI_TEST_GRP_2 (UTMI_BASE+0x0020) /* 32 bit Test Group |
| * 2 Register |
| */ |
| #define UTMI_ID_GRP (UTMI_BASE+0x0024) /* 26 bit ID Group |
| * Register |
| */ |
| #define UTMI_USB_INT (UTMI_BASE+0x0028) /* 32 bit ID Group |
| * Register |
| */ |
| #define UTMI_DBG_CTL (UTMI_BASE+0x002C) /* 16 bit ID Group |
| * Register |
| */ |
| #define UTMI_CTL1 (UTMI_BASE+0x0030) /* 16 bit ID Group |
| * Register |
| */ |
| #define UTMI_TEST_GRP_3 (UTMI_BASE+0x0034) /* 32 bit Test Group |
| * 3 Register |
| */ |
| #define UTMI_OTG_ADDON (UTMI_BASE+0x003c) /* 32 bit OTG enable |
| * Register |
| */ |
| #define UTMI_TEST_GRP_4 (UTMI_BASE+0x0338) /* 32 bit Test Group |
| * 4 Register |
| */ |
| #define UTMI_TEST_GRP_5 (UTMI_BASE+0x033C) /* 32 bit Test Group |
| * 5 Register |
| */ |
| |
| /* |
| * |
| * THE BIT DEFINES |
| * |
| */ |
| /* USB_ID 0x0000 Identification Register */ |
| /* Bit(s) USB_ID_RSRV_31_24 reserved */ |
| #define USB_ID_REVISION_MSK SHIFT16(0xff) /* REVISION[7:0] */ |
| #define USB_ID_REVISION_BASE 16 |
| /* Bit(s) USB_ID_RSRV_15_14 reserved */ |
| #define USB_ID_NID5_0_MSK SHIFT8(0x3f) /* NID[5:0] */ |
| #define USB_ID_NID5_0_BASE 8 |
| /* Bit(s) USB_ID_RSRV_7_6 reserved */ |
| #define USB_ID_ID_MSK SHIFT0(0x3f) /* ID[5:0] */ |
| #define USB_ID_ID_BASE 0 |
| |
| /* USB_HWGENERAL 0x0004 General Hardware Parameters Register */ |
| /* Bit(s) USB_HWGENERAL_RSRV_31_10 reserved */ |
| #define USB_HWGENERAL_SM BIT_9 /* SM */ |
| #define USB_HWGENERAL_PHYM_MSK SHIFT6(0x7) /* PHYM */ |
| #define USB_HWGENERAL_PHYM_BASE 6 |
| #define USB_HWGENERAL_PHYW_MSK SHIFT4(0x3) /* PHYW */ |
| #define USB_HWGENERAL_PHYW_BASE 4 |
| #define USB_HWGENERAL_BWT BIT_3 /* BWT */ |
| #define USB_HWGENERAL_CLKC_MSK SHIFT1(0x3) /* CLKC */ |
| #define USB_HWGENERAL_CLKC_BASE 1 |
| #define USB_HWGENERAL_RT BIT_0 /* RT */ |
| |
| /* USB_HWHOST 0x0008 Host Hardware Parameters Register */ |
| #define USB_HWHOST_TTPER_MSK SHIFT24(0xff) /* TTPER */ |
| #define USB_HWHOST_TTPER_BASE 24 |
| #define USB_HWHOST_TTASY_MSK SHIFT16(0xff) /* TTASY */ |
| #define USB_HWHOST_TTASY_BASE 16 |
| /* Bit(s) USB_HWHOST_RSRV_15_4 reserved */ |
| #define USB_HWHOST_NPORT_MSK SHIFT1(0x7) /* NPORT */ |
| #define USB_HWHOST_NPORT_BASE 1 |
| #define USB_HWHOST_HC BIT_0 /* HC */ |
| |
| /* USB_HWDEVICE 0x000C Device Hardware Parameters Register */ |
| /* Bit(s) USB_HWDEVICE_RSRV_31_6 reserved */ |
| #define USB_HWDEVICE_DEVEP_MSK SHIFT1(0x1f) /* DEVEP */ |
| #define USB_HWDEVICE_DEVEP_BASE 1 |
| #define USB_HWDEVICE_DC BIT_0 /* DC */ |
| |
| /* USB_HWTXBUF 0x0010 TX Buffer Hardware Parameters Register */ |
| #define USB_HWTXBUF_TXLCR BIT_31 /* TXLCR */ |
| /* Bit(s) USB_HWTXBUF_RSRV_30_24 reserved */ |
| #define USB_HWTXBUF_TXCHANADD_MSK SHIFT16(0xff) /* TXCHANADD */ |
| #define USB_HWTXBUF_TXCHANADD_BASE 16 |
| #define USB_HWTXBUF_TXADD_MSK SHIFT8(0xff) /* TXADD */ |
| #define USB_HWTXBUF_TXADD_BASE 8 |
| #define USB_HWTXBUF_TCBURST_MSK SHIFT0(0xff) /* TCBURST */ |
| #define USB_HWTXBUF_TCBURST_BASE 0 |
| |
| /* USB_HWRXBUF 0x0014 RX Buffer Hardware Parameters Register */ |
| /* Bit(s) USB_HWRXBUF_RSRV_31_16 reserved */ |
| #define USB_HWRXBUF_RXADD_MSK SHIFT8(0xff) /* RXADD */ |
| #define USB_HWRXBUF_RXADD_BASE 8 |
| #define USB_HWRXBUF_RXBURST_MSK SHIFT0(0xff) /* RXBURST */ |
| #define USB_HWRXBUF_RXBURST_BASE 0 |
| |
| /* USB_CAPLENGTH 0x0100 Capability Register Length - EHCI |
| * Compliant Register |
| */ |
| /* Bit(s) USB_CAPLENGTH_RSRV_15_8 reserved */ |
| #define USB_CAPLENGTH_CAPLENGTH_MSK SHIFT0(0xff) /* CAPLENGTH */ |
| #define USB_CAPLENGTH_CAPLENGTH_BASE 0 |
| |
| /* */ |
| #define USB_HCIVERSION_HCIVERSION_MSK SHIFT0(0xffff) /* HCIVERSION */ |
| #define USB_HCIVERSION_HCIVERSION_BASE 0 |
| |
| /* USB_HCSPARAMS 0x0104 Host Ctrl. Structural Parameters EHCI |
| * Compliant with |
| */ |
| /* Bit(s) USB_HCSPARAMS_RSRV_31_28 reserved */ |
| #define USB_HCSPARAMS_N_TT_MSK SHIFT24(0xf) /* N_TT[3:0] */ |
| #define USB_HCSPARAMS_N_TT_BASE 24 |
| #define USB_HCSPARAMS_N_PTT_MSK SHIFT20(0xf) /* N_PTT[3:0] */ |
| #define USB_HCSPARAMS_N_PTT_BASE 20 |
| /* Bit(s) USB_HCSPARAMS_RSRV_19_17 reserved */ |
| #define USB_HCSPARAMS_PI BIT_16 /* PI */ |
| #define USB_HCSPARAMS_N_CC_MSK SHIFT12(0xf) /* N_CC[3:0] */ |
| #define USB_HCSPARAMS_N_CC_BASE 12 |
| #define USB_HCSPARAMS_N_PCC_MSK SHIFT8(0xf) /* N_PCC[3:0] */ |
| #define USB_HCSPARAMS_N_PCC_BASE 8 |
| /* Bit(s) USB_HCSPARAMS_RSRV_7_5 reserved */ |
| #define USB_HCSPARAMS_PPC BIT_4 /* PPC */ |
| #define USB_HCSPARAMS_N_PORTS_MSK SHIFT0(0xf) /* N_PORTS[3:0] */ |
| #define USB_HCSPARAMS_N_PORTS_BASE 0 |
| |
| /* USB_HCCPARAMS 0x0108 Host Ctrl. Capability Parameters EHCI |
| * Compliant |
| */ |
| /* Bit(s) USB_HCCPARAMS_RSRV_31_16 reserved */ |
| #define USB_HCCPARAMS_EECP_MSK SHIFT8(0xff) /* EECP[7:0] */ |
| #define USB_HCCPARAMS_EECP_BASE 8 |
| #define USB_HCCPARAMS_IST_MSK SHIFT4(0xf) /* IST[7:4] */ |
| #define USB_HCCPARAMS_IST_BASE 4 |
| /* Bit(s) USB_HCCPARAMS_RSRV_3 reserved */ |
| #define USB_HCCPARAMS_ASP BIT_2 /* ASP */ |
| #define USB_HCCPARAMS_PFL BIT_1 /* PFL */ |
| #define USB_HCCPARAMS_ADC BIT_0 /* ADC */ |
| |
| /* USB_DCIVERSION 0x0120 Dev. Interface Version Number Register */ |
| /* Bit(s) USB_DCIVERSION_RSRV_31_16 reserved */ |
| #define USB_DCIVERSION_DCIVERSION_MSK SHIFT0(0xffff) /* DCIVERSION */ |
| #define USB_DCIVERSION_DCIVERSION_BASE 0 |
| |
| /* USB_DCCPARAMS 0x0124 Device Ctrl. Capability Parameters |
| * Register |
| */ |
| /* Bit(s) USB_DCCPARAMS_RSRV_31_9 reserved */ |
| #define USB_DCCPARAMS_HC BIT_8 /* HC */ |
| #define USB_DCCPARAMS_DC BIT_7 /* DC */ |
| /* Bit(s) USB_DCCPARAMS_RSRV_6_5 reserved */ |
| #define USB_DCCPARAMS_DEN_MSK SHIFT0(0x1f) /* DEN[4:0] */ |
| #define USB_DCCPARAMS_DEN_BASE 0 |
| |
| /* USB_CMD 0x0140 USB Command Register */ |
| /* Bit(s) USB_CMD_RSRV_31_24 reserved */ |
| #define USB_CMD_ITC_MSK SHIFT16(0xff) /* ITC[7:0] */ |
| #define USB_CMD_ITC_BASE 16 |
| #define USB_CMD_FS BIT_15 /* FS[2] */ |
| /* Bit(s) USB_CMD_RSRV_14 reserved */ |
| #define USB_CMD_SUTW BIT_13 /* SUTW */ |
| #define USB_CMD_ATDTW BIT_12 /* ATDTW */ |
| #define USB_CMD_ASPE BIT_11 /* ASPE */ |
| /* Bit(s) USB_CMD_RSRV_10 reserved */ |
| #define USB_CMD_ASP_MSK SHIFT8(0x3) /* ASP[1:0] */ |
| #define USB_CMD_ASP_BASE 8 |
| /* Bit(s) USB_CMD_RSRV_7 reserved */ |
| #define USB_CMD_IAA BIT_6 /* IAA */ |
| #define USB_CMD_ASE BIT_5 /* ASE */ |
| #define USB_CMD_PSE BIT_4 /* PSE */ |
| #define USB_CMD_FS_MSK SHIFT2(0x3) /* FS[1:0] */ |
| #define USB_CMD_FS_BASE 2 |
| #define USB_CMD_RST BIT_1 /* RST */ |
| #define USB_CMD_RS BIT_0 /* RS */ |
| |
| /* USB_STS 0x0144 USB Status Register */ |
| /* Bit(s) USB_STS_RSRV_31_17 reserved */ |
| #define USB_STS_NAKI BIT_16 /* NAKI */ |
| #define USB_STS_AS BIT_15 /* AS */ |
| #define USB_STS_PS BIT_14 /* PS */ |
| #define USB_STS_RCL BIT_13 /* RCL */ |
| #define USB_STS_HCH BIT_12 /* HCH */ |
| /* Bit(s) USB_STS_RSRV_11 reserved */ |
| #define USB_STS_ULPII BIT_10 /* ULPII */ |
| /* Bit(s) USB_STS_RSRV_9 reserved */ |
| #define USB_STS_SLI BIT_8 /* SLI */ |
| #define USB_STS_SRI BIT_7 /* SRI */ |
| #define USB_STS_URI BIT_6 /* URI */ |
| #define USB_STS_AAI_0B_08H BIT_5 /* AAI 0B-08H */ |
| /* Bit(s) USB_STS_RSRV_4 reserved */ |
| #define USB_STS_FRI BIT_3 /* FRI */ |
| #define USB_STS_PCI BIT_2 /* PCI */ |
| #define USB_STS_UEI BIT_1 /* UEI */ |
| #define USB_STS_UI BIT_0 /* UI */ |
| |
| /* USB_INTR 0x0148 USB Interrupt Enable Register */ |
| /* Bit(s) USB_INTR_RSRV_31_17 reserved */ |
| #define USB_INTR_NAKE BIT_16 /* NAKE */ |
| /* Bit(s) USB_INTR_RSRV_15_9 reserved */ |
| #define USB_INTR_SLE BIT_8 /* SLE */ |
| #define USB_INTR_SRE BIT_7 /* SRE */ |
| #define USB_INTR_URE BIT_6 /* URE */ |
| #define USB_INTR_AAE BIT_5 /* AAE */ |
| #define USB_INTR_SEE BIT_4 /* SEE */ |
| #define USB_INTR_FRE BIT_3 /* FRE */ |
| #define USB_INTR_PCE BIT_2 /* PCE */ |
| #define USB_INTR_UEE BIT_1 /* UEE */ |
| #define USB_INTR_UE BIT_0 /* UE */ |
| |
| /* USB_FRINDEX 0x014C USB Frame Index Register */ |
| /* Bit(s) USB_FRINDEX_RSRV_31_14 reserved */ |
| #define USB_FRINDEX_FRINDEX_MSK SHIFT0(0x3fff) /* FRINDEX */ |
| #define USB_FRINDEX_FRINDEX_BASE 0 |
| |
| /* USB_PERIODICLISTBASE 0x0154 Host Controller Frame List Base |
| * Address Register (Host Mode) |
| */ |
| #define USB_PERIODICLISTBASE_BASEADR_MSK SHIFT12(0xfffff) /* BASEADR */ |
| #define USB_PERIODICLISTBASE_BASEADR_BASE 12 |
| /* Bit(s) USB_PERIODICLISTBASE_RSRV_11_0 reserved */ |
| |
| /* USB_DEVICEADDR 0x0154 Device Controller USB Device Address |
| * Register (Device Mode) |
| */ |
| #define USB_DEVICEADDR_USBADR_MSK SHIFT25(0x7f) /* USBADR */ |
| #define USB_DEVICEADDR_USBADR_BASE 25 |
| #define USB_DEVICEADDR_USBADRA BIT_24 /* USBADRA */ |
| /* Bit(s) USB_DEVICEADDR_RSRV_23_0 reserved */ |
| |
| /* USB_ASYNCLISTADDR 0x0158 Host Controller Next Asynchronous List |
| * Address Register |
| */ |
| #define USB_ASYNCLISTADDR_ASYBASE_MSK SHIFT5(0x7ffffff) /* ASYBASE[31:5] */ |
| #define USB_ASYNCLISTADDR_ASYBASE_BASE 5 |
| /* Bit(s) USB_ASYNCLISTADDR_RSRV_4_0 reserved */ |
| |
| /* USB_ENDPOINTLISTADDR 0x0158 Address at Endpoint List in Memory |
| * Register |
| */ |
| /* EPBASE[31:11] */ |
| #define USB_ENDPOINTLISTADDR_EPBASE_MSK SHIFT11(0x1fffff) |
| #define USB_ENDPOINTLISTADDR_EPBASE_BASE 11 |
| /* Bit(s) USB_ENDPOINTLISTADDR_RSRV_10_0 reserved */ |
| |
| /* USB_BURSTSIZE 0x0160 Programmable Burst Size Register - |
| * Host Controller |
| */ |
| /* Bit(s) USB_BURSTSIZE_RSRV_31_17 reserved */ |
| #define USB_BURSTSIZE_TXPBURST_MSK SHIFT8(0x1ff) /* TXPBURST */ |
| #define USB_BURSTSIZE_TXPBURST_BASE 8 |
| #define USB_BURSTSIZE_RXPBURST_MSK SHIFT0(0xff) /* RXPBURST */ |
| #define USB_BURSTSIZE_RXPBURST_BASE 0 |
| |
| /* USB_ENDPTNAK 0x0178 Endpoint NAK Register */ |
| #define USB_ENDPTNAK_EPTN_MSK SHIFT16(0xffff) /* EPTN [15:0] */ |
| #define USB_ENDPTNAK_EPTN_BASE 16 |
| #define USB_ENDPTNAK_EPRN_MSK SHIFT0(0xffff) /* EPRN [15:0] */ |
| #define USB_ENDPTNAK_EPRN_BASE 0 |
| |
| /* USB_ENDPTNAKEN 0x017C Endpoint NAK Enable Register */ |
| #define USB_ENDPTNAKEN_EPTNE_MSK SHIFT16(0xffff) /* EPTNE [15:0] */ |
| #define USB_ENDPTNAKEN_EPTNE_BASE 16 |
| #define USB_ENDPTNAKEN_EPRNE_MSK SHIFT0(0xffff) /* EPRNE [15:0] */ |
| #define USB_ENDPTNAKEN_EPRNE_BASE 0 |
| |
| /* USB_PORTSC 0x0184 Port Status/Control Register */ |
| #define USB_PORTSC_PTS_MSK SHIFT30(0x3) /* PTS */ |
| #define USB_PORTSC_PTS_BASE 30 |
| /* Bit(s) USB_PORTSC_RSRV_29 reserved */ |
| #define USB_PORTSC_PTW BIT_28 /* PTW */ |
| #define USB_PORTSC_PSPD_MSK SHIFT26(0x3) /* PSPD */ |
| #define USB_PORTSC_PSPD_BASE 26 |
| /* Bit(s) USB_PORTSC_RSRV_25 reserved */ |
| #define USB_PORTSC_PFSC BIT_24 /* PFSC */ |
| #define USB_PORTSC_PHCD BIT_23 /* PHCD */ |
| #define USB_PORTSC_WKOC BIT_22 /* WKOC */ |
| #define USB_PORTSC_WKDC BIT_21 /* WKDC */ |
| #define USB_PORTSC_WKCN BIT_20 /* WKCN */ |
| #define USB_PORTSC_PTC_MSK SHIFT16(0xf) /* PTC[3:0] */ |
| #define USB_PORTSC_PTC_BASE 16 |
| #define USB_PORTSC_PIC_MSK SHIFT14(0x3) /* PIC[1:0] */ |
| #define USB_PORTSC_PIC_BASE 14 |
| /* Bit(s) USB_PORTSC_RSRV_13 reserved */ |
| #define USB_PORTSC_PP BIT_12 /* PP */ |
| #define USB_PORTSC_LS_MSK SHIFT10(0x3) /* LS[1:0] */ |
| #define USB_PORTSC_LS_BASE 10 |
| #define USB_PORTSC_HSP BIT_9 /* HSP */ |
| #define USB_PORTSC_PR BIT_8 /* PR */ |
| #define USB_PORTSC_SUSP BIT_7 /* SUSP */ |
| #define USB_PORTSC_FPR BIT_6 /* FPR */ |
| #define USB_PORTSC_OCC BIT_5 /* OCC */ |
| #define USB_PORTSC_OCA BIT_4 /* OCA */ |
| #define USB_PORTSC_PEC BIT_3 /* PEC */ |
| #define USB_PORTSC_PE BIT_2 /* PE */ |
| #define USB_PORTSC_CSC BIT_1 /* CSC */ |
| #define USB_PORTSC_CCS BIT_0 /* CCS */ |
| |
| /* USB_OTGSC 0x01A4 OTG Status and Control Register */ |
| /* Bit(s) USB_OTGSC_RSRV_31 reserved */ |
| #define USB_OTGSC_DPIE BIT_30 /* DPIE */ |
| #define USB_OTGSC_1MSE BIT_29 /* 1msE */ |
| #define USB_OTGSC_BSEIE BIT_28 /* BSEIE */ |
| #define USB_OTGSC_BSVIE BIT_27 /* BSVIE */ |
| #define USB_OTGSC_ASVIE BIT_26 /* ASVIE */ |
| #define USB_OTGSC_AVVIE BIT_25 /* AVVIE */ |
| #define USB_OTGSC_IDIE BIT_24 /* IDIE */ |
| /* Bit(s) USB_OTGSC_RSRV_23 reserved */ |
| #define USB_OTGSC_DPIS BIT_22 /* DPIS */ |
| #define USB_OTGSC_1MSS BIT_21 /* 1msS */ |
| #define USB_OTGSC_BSEIS BIT_20 /* BSEIS */ |
| #define USB_OTGSC_BSVIS BIT_19 /* BSVIS */ |
| #define USB_OTGSC_ASVIS BIT_18 /* ASVIS */ |
| #define USB_OTGSC_AVVIS BIT_17 /* AVVIS */ |
| #define USB_OTGSC_IDIS BIT_16 /* IDIS */ |
| /* Bit(s) USB_OTGSC_RSRV_15 reserved */ |
| #define USB_OTGSC_DPS BIT_14 /* DPS */ |
| #define USB_OTGSC_1MST BIT_13 /* 1msT */ |
| #define USB_OTGSC_BSE BIT_12 /* BSE */ |
| #define USB_OTGSC_BSV BIT_11 /* BSV */ |
| #define USB_OTGSC_ASV BIT_10 /* ASV */ |
| #define USB_OTGSC_AVV BIT_9 /* AVV */ |
| #define USB_OTGSC_ID BIT_8 /* ID */ |
| #define USB_OTGSC_HABA BIT_7 /* HABA */ |
| #define USB_OTGSC_HADP BIT_6 /* HADP */ |
| #define USB_OTGSC_IDPU BIT_5 /* IDPU */ |
| #define USB_OTGSC_DP BIT_4 /* DP */ |
| #define USB_OTGSC_OT BIT_3 /* OT */ |
| #define USB_OTGSC_HAAR BIT_2 /* HAAR */ |
| #define USB_OTGSC_VC BIT_1 /* VC */ |
| #define USB_OTGSC_VD BIT_0 /* VD */ |
| |
| /* USB_MODE 0x01A8 USB Device Mode Register */ |
| /* Bit(s) USB_MODE_RSRV_31_5 reserved */ |
| #define USB_MODE_SDIS BIT_4 /* SDIS */ |
| #define USB_MODE_SLOM BIT_3 /* SLOM */ |
| #define USB_MODE_ES BIT_2 /* ES */ |
| #define USB_MODE_CM_MSK SHIFT0(0x3) /* CM[1:0] */ |
| #define USB_MODE_CM_BASE 0 |
| |
| /* USB_ENDPTSETUPSTAT 0x01AC Endpoint Setup Status Register */ |
| /* Bit(s) USB_ENDPTSETUPSTAT_RSRV_31_16 reserved */ |
| /* Setup Endpoint Status */ |
| #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT150_MSK SHIFT0(0xffff) |
| #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT150_BASE 0 |
| |
| /* USB_ENDPTPRIME 0x01B0 Endpoint Initialization Register */ |
| /* Bit(s) USB_ENDPTPRIME_RSRV_31_20 reserved */ |
| #define USB_ENDPTPRIME_PETB_MSK SHIFT16(0xf) /* PETB [3:0] */ |
| #define USB_ENDPTPRIME_PETB_BASE 16 |
| /* Bit(s) USB_ENDPTPRIME_RSRV_15_4 reserved */ |
| #define USB_ENDPTPRIME_PERB_MSK SHIFT0(0xf) /* PERB [3:0] */ |
| #define USB_ENDPTPRIME_PERB_BASE 0 |
| |
| /* USB_ENDPTFLUSH 0x01B4 Endpoint De-Initialize Register */ |
| /* Bit(s) USB_ENDPTFLUSH_RSRV_31_20 reserved */ |
| #define USB_ENDPTFLUSH_FETB_MSK SHIFT16(0xf) /* FETB [3:0] */ |
| #define USB_ENDPTFLUSH_FETB_BASE 16 |
| /* Bit(s) USB_ENDPTFLUSH_RSRV_15_4 reserved */ |
| #define USB_ENDPTFLUSH_FERB_MSK SHIFT0(0xf) /* FERB [3:0] */ |
| #define USB_ENDPTFLUSH_FERB_BASE 0 |
| |
| /* USB_ENDPTSTAT 0x01B8 Endpoint STAT Register */ |
| /* Bit(s) USB_ENDPTSTAT_RSRV_31_20 reserved */ |
| #define USB_ENDPTSTAT_ETBR_MSK SHIFT16(0xf) /* ETBR [3:0] */ |
| #define USB_ENDPTSTAT_ETBR_BASE 16 |
| /* Bit(s) USB_ENDPTSTAT_RSRV_15_4 reserved */ |
| #define USB_ENDPTSTAT_ERBR_MSK SHIFT0(0xf) /* ERBR [3:0] */ |
| #define USB_ENDPTSTAT_ERBR_BASE 0 |
| |
| /* USB_ENDPTCOMPLETE 0x01BC Endpoint Complete Register */ |
| /* Bit(s) USB_ENDPTCOMPLETE_RSRV_31_20 reserved */ |
| #define USB_ENDPTCOMPLETE_ETCE_MSK SHIFT16(0xf) /* ETCE [3:0] */ |
| #define USB_ENDPTCOMPLETE_ETCE_BASE 16 |
| /* Bit(s) USB_ENDPTCOMPLETE_RSRV_15_4 reserved */ |
| #define USB_ENDPTCOMPLETE_ERCE_MSK SHIFT0(0xf) /* ERCE [3:0] */ |
| #define USB_ENDPTCOMPLETE_ERCE_BASE 0 |
| |
| /* USB_ENDPTCTRL0 0x01C0 Endpoint Control 0 Register */ |
| /* Bit(s) USB_ENDPTCTRL0_RSRV_31_24 reserved */ |
| #define USB_ENDPTCTRL0_TXE BIT_23 /* TXE */ |
| /* Bit(s) USB_ENDPTCTRL0_RSRV_22_20 reserved */ |
| #define USB_ENDPTCTRL0_TXT_MSK SHIFT18(0x3) /* TXT[1:0] */ |
| #define USB_ENDPTCTRL0_TXT_BASE 18 |
| /* Bit(s) USB_ENDPTCTRL0_RSRV_17 reserved */ |
| #define USB_ENDPTCTRL0_TXS BIT_16 /* TXS */ |
| /* Bit(s) USB_ENDPTCTRL0_RSRV_15_8 reserved */ |
| #define USB_ENDPTCTRL0_RXE BIT_7 /* RXE */ |
| /* Bit(s) USB_ENDPTCTRL0_RSRV_6_4 reserved */ |
| #define USB_ENDPTCTRL0_RXT_MSK SHIFT2(0x3) /* RXT[1:0] */ |
| #define USB_ENDPTCTRL0_RXT_BASE 2 |
| /* Bit(s) USB_ENDPTCTRL0_RSRV_1 reserved */ |
| #define USB_ENDPTCTRL0_RXS BIT_0 /* RXS */ |
| |
| /* USB_ENDPTCTRL1_ENDPTCTRL3 0x01C4 Endpoint Control 1 to Endpoint Control |
| * 3 Registers |
| */ |
| /* Bit(s) USB_ENDPTCTRL1_ENDPTCTRL3_RSRV_31_24 reserved */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_TXE BIT_23 /* TXE */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_TXR BIT_22 /* TXR */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_TXI BIT_21 /* TXI */ |
| /* Bit(s) USB_ENDPTCTRL1_ENDPTCTRL3_RSRV_20 reserved */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_TXT_MSK SHIFT18(0x3) /* TXT[1:0] */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_TXT_BASE 18 |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_TXD BIT_17 /* TXD */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_TXS BIT_16 /* TXS */ |
| /* Bit(s) USB_ENDPTCTRL1_ENDPTCTRL3_RSRV_15_8 reserved */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_RXE BIT_7 /* RXE */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_RXR BIT_6 /* RXR */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_RXI BIT_5 /* RXI */ |
| /* Bit(s) USB_ENDPTCTRL1_ENDPTCTRL3_RSRV_4 reserved */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_RXT_MSK SHIFT2(0x3) /* RXT[1:0] */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_RXT_BASE 2 |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_RXD BIT_1 /* RXD */ |
| #define USB_ENDPTCTRL1_ENDPTCTRL3_RXS BIT_0 /* RXS */ |
| |
| /* UTMI_CTRL 0x0004 USB Control Register */ |
| #define UTMI_CTRL_USB_CTL_31_30_MSK SHIFT30(0x3) /* USB_CTL */ |
| #define UTMI_CTRL_USB_CTL_31_30_BASE 30 |
| #define UTMI_CTRL_USB_CTL_29_28_MSK SHIFT28(0x3) /* USB_CTL */ |
| #define UTMI_CTRL_USB_CTL_29_28_BASE 28 |
| #define UTMI_CTRL_ISO_FIX_ENABLE_B BIT_27 /* ISO_FIX_ENABLE_B */ |
| #define UTMI_CTRL_ISO_FIX_ENABLE_A BIT_26 /* ISO_FIX_ENABLE_A */ |
| #define UTMI_CTRL_PU_CLK BIT_23 |
| #define UTMI_CTRL_PU_REF BIT_20 |
| /* Bit(s) UTMI_CTRL_RSRV_25_15 reserved */ |
| #define UTMI_CTRL_REG_DP_PULLDOWN BIT_14 /* REG_DP_PULLDOWN */ |
| #define UTMI_CTRL_REG_DM_PULLDOWN BIT_13 /* REG_DM_PULLDOWN */ |
| #define UTMI_CTRL_REG_ARC_DPDM_MODE BIT_12 /* REG_ARC_DPDM_MODE */ |
| /* Bit(s) UTMI_CTRL_RSRV_11_2 reserved */ |
| #define UTMI_CTRL_PU_PLL BIT_1 /* PU_PLL */ |
| #define UTMI_CTRL_PU BIT_0 /* PU */ |
| |
| /* UTMI_PLL 0x0008 PLL Register */ |
| /* Bit(s) UTMI_PLL_RSRV_31 reserved */ |
| #define UTMI_PLL_PLLCALI12_MSK SHIFT29(0x3) /* PLLCALI12[1:0] */ |
| #define UTMI_PLL_PLLCALI12_BASE 29 |
| #define UTMI_PLL_PLLVDD18_MSK SHIFT27(0x3) /* PLLVDD18[1:0] */ |
| #define UTMI_PLL_PLLVDD18_BASE 27 |
| #define UTMI_PLL_PLLVDD12_MSK SHIFT25(0x3) /* PLLVDD12[1:0] */ |
| #define UTMI_PLL_PLLVDD12_BASE 25 |
| #define UTMI_PLL_CLK_BLK_EN BIT_24 /* CLK_BLK_EN */ |
| #define UTMI_PLL_PLL_READY BIT_23 /* PLL_READY */ |
| #define UTMI_PLL_KVCO_EXT BIT_22 /* KVCO_EXT */ |
| #define UTMI_PLL_VCOCAL_START BIT_21 /* VCOCAL_START */ |
| /* Bit(s) UTMI_PLL_RSRV_20_19 reserved */ |
| #define UTMI_PLL_LOCKDET_ISEL BIT_18 /* LOCKDET_ISEL */ |
| #define UTMI_PLL_KVCO_MSK SHIFT15(0x7) /* KVCO[2:0] */ |
| #define UTMI_PLL_KVCO_BASE 15 |
| #define UTMI_PLL_ICP_MSK SHIFT12(0x7) /* ICP[2:0] */ |
| #define UTMI_PLL_ICP_BASE 12 |
| #define UTMI_PLL_FBDIV_MSK SHIFT4(0xff) /* FBDIV[8:0] */ |
| #define UTMI_PLL_FBDIV_BASE 4 |
| #define UTMI_PLL_REFDIV_MSK SHIFT0(0xf) /* REFDIV[1:0] */ |
| #define UTMI_PLL_REFDIV_BASE 0 |
| |
| /* UTMI_TX 0x000C Tx Register */ |
| #define UTMI_TX_HS_STRESS_CTRL BIT_31 /* HS_STRESS_CTRL */ |
| #define UTMI_TX_REG_EXT_FS_RCAL_MSK SHIFT27(0xf) /* REG_EXT_FS_RCAL */ |
| #define UTMI_TX_REG_EXT_FS_RCAL_BASE 27 |
| #define UTMI_TX_REG_EXT_FS_RCAL_EN BIT_26 /* REG_EXT_FS_RCAL_EN */ |
| #define UTMI_TX_TXVDD18_MSK SHIFT24(0x3) /* TXVDD18[1:0] */ |
| #define UTMI_TX_TXVDD18_BASE 24 |
| #define UTMI_TX_TXVDD12_MSK SHIFT22(0x3) /* TXVDD12[1:0] */ |
| #define UTMI_TX_TXVDD12_BASE 22 |
| #define UTMI_TX_TXDATA_BLOCK_EN BIT_21 /* TXDATA_BLOCK_EN */ |
| #define UTMI_TX_CK60_PHSEL_MSK SHIFT17(0xf) /* CK60_PHSEL */ |
| #define UTMI_TX_CK60_PHSEL_BASE 17 |
| #define UTMI_TX_IMPCAL_VTH_MSK SHIFT14(0x7) /* IMPCAL_VTH[2:0] */ |
| #define UTMI_TX_IMPCAL_VTH_BASE 14 |
| #define UTMI_TX_REG_EXT_HS_RCAL_EN BIT_13 /* REG_EXT_HS_RCAL_EN */ |
| #define UTMI_TX_REG_RCAL_START BIT_12 /* REG_RCAL_START */ |
| #define UTMI_TX_LOWVDD_EN BIT_11 /* LOWVDD_EN */ |
| #define UTMI_TX_HSDRV_EN_MSK SHIFT7(0xf) /* HSDRV_EN[3:0] */ |
| #define UTMI_TX_HSDRV_EN_BASE 7 |
| #define UTMI_TX_REG_EXT_HS_RCAL_MSK SHIFT3(0xf) /* REG_EXT_HS_RCAL[3:0] */ |
| #define UTMI_TX_REG_EXT_HS_RCAL_BASE 3 |
| #define UTMI_TX_AMP_MSK SHIFT0(0x7) /* AMP[2:0] */ |
| #define UTMI_TX_AMP_BASE 0 |
| |
| /* UTMI_RX 0x0010 Rx Register */ |
| #define UTMI_RX_EARLY_VOS_ON_EN BIT_31 /* EARLY_VOS_ON_EN */ |
| #define UTMI_RX_RXDATA_BLOCK_EN BIT_30 /* RXDATA_BLOCK_EN */ |
| /* RXDATA_BLOCK_LENGTH[1:0] */ |
| #define UTMI_RX_RXDATA_BLOCK_LENGTH_MSK SHIFT28(0x3) |
| #define UTMI_RX_RXDATA_BLOCK_LENGTH_BASE 28 |
| #define UTMI_RX_EDGE_DET_EN BIT_27 /* EDGE_DET_EN */ |
| /* S2TO3_DLY_SEL[1:0] */ |
| #define UTMI_RX_S2TO3_DLY_SEL_MSK SHIFT25(0x3) |
| #define UTMI_RX_S2TO3_DLY_SEL_BASE 25 |
| /* Bit(s) UTMI_RX_RSRV_24_23 reserved */ |
| #define UTMI_RX_CDR_COEF_SEL BIT_22 /* CDR_COEF_SEL */ |
| #define UTMI_RX_CDR_FASTLOCK_EN BIT_21 /* CDR_FASTLOCK_EN */ |
| #define UTMI_RX_PHASE_FREEZE_DLY BIT_20 /* PHASE_FREEZE_DLY */ |
| #define UTMI_RX_REG_USQ_LENGTH BIT_19 /* REG_USQ_LENGTH */ |
| /* REG_ACQ_LENGTH[1:0] */ |
| #define UTMI_RX_REG_ACQ_LENGTH_MSK SHIFT17(0x3) |
| #define UTMI_RX_REG_ACQ_LENGTH_BASE 17 |
| /* REG_SQ_LENGTH[1:0] */ |
| #define UTMI_RX_REG_SQ_LENGTH_MSK SHIFT15(0x3) |
| #define UTMI_RX_REG_SQ_LENGTH_BASE 15 |
| #define UTMI_RX_DLL_SEL_MSK SHIFT13(0x3) /* DLL_SEL[1:0] */ |
| #define UTMI_RX_DLL_SEL_BASE 13 |
| #define UTMI_RX_CAP_SEL_MSK SHIFT10(0x7) /* CAP_SEL[2:0] */ |
| #define UTMI_RX_CAP_SEL_BASE 10 |
| /* DISCON_THRESH[1:0] */ |
| #define UTMI_RX_DISCON_THRESH_MSK SHIFT8(0x3) |
| #define UTMI_RX_DISCON_THRESH_BASE 8 |
| #define UTMI_RX_SQ_THRESH_MSK SHIFT4(0xf) /* SQ_THRESH[3:0] */ |
| #define UTMI_RX_SQ_THRESH_BASE 4 |
| #define UTMI_RX_LPF_COEF_MSK SHIFT2(0x3) /* LPF_COEF[1:0] */ |
| #define UTMI_RX_LPF_COEF_BASE 2 |
| #define UTMI_RX_INTPI_MSK SHIFT0(0x3) /* INTPI[1:0] */ |
| #define UTMI_RX_INTPI_BASE 0 |
| |
| /* UTMI_IVREF 0x0014 IVREF Register */ |
| #define UTMI_IVREF_SAMPLER_CTRL BIT_31 /* SAMPLER_CTRL */ |
| #define UTMI_IVREF_RXVDD18_MSK SHIFT29(0x3) /* RXVDD18[1:0] */ |
| #define UTMI_IVREF_RXVDD18_BASE 29 |
| /* Bit(s) UTMI_IVREF_RSRV_28_11 reserved */ |
| #define UTMI_IVREF_SQ_CM_SEL BIT_10 /* SQ_CM_SEL */ |
| /* EDGE_DET_SEL[1:0] */ |
| #define UTMI_IVREF_EDGE_DET_SEL_MSK SHIFT8(0x3) |
| #define UTMI_IVREF_EDGE_DET_SEL_BASE 8 |
| #define UTMI_IVREF_RXVDD12_MSK SHIFT6(0x3) /* RXVDD12[1:0] */ |
| #define UTMI_IVREF_RXVDD12_BASE 6 |
| #define UTMI_IVREF_FSDRV_EN_MSK SHIFT2(0xf) /* FSDRV_EN[3:0] */ |
| #define UTMI_IVREF_FSDRV_EN_BASE 2 |
| #define UTMI_IVREF_REG_IMP_CAL_DLY_MSK SHIFT0(0x3) /* REG_IMP_CAL_DLY */ |
| #define UTMI_IVREF_REG_IMP_CAL_DLY_BASE 0 |
| |
| /* UTMI_TEST_GRP_0 0x0018 Test Group 0 Register */ |
| #define UTMI_TEST_GRP_0_REG_FIFO_OV BIT_31 /* REG_FIFO_OV */ |
| #define UTMI_TEST_GRP_0_REG_FIFO_UF BIT_30 /* REG_FIFO_UF */ |
| /* Bit(s) UTMI_TEST_GRP_0_RSRV_29 reserved */ |
| /* REG_ARC_DPDM_MODE */ |
| #define UTMI_TEST_GRP_0_REG_ARC_DPDM_MODE BIT_28 |
| /* REG_DP_PULLDOWN */ |
| #define UTMI_TEST_GRP_0_REG_DP_PULLDOWN BIT_27 |
| /* REG_DM_PULLDOWN */ |
| #define UTMI_TEST_GRP_0_REG_DM_PULLDOWN BIT_26 |
| /* REG_FIFO_S2P_SEL */ |
| #define UTMI_TEST_GRP_0_REG_FIFO_S2P_SEL BIT_25 |
| /* REG_FIFO_FILL_NUM */ |
| #define UTMI_TEST_GRP_0_REG_FIFO_FILL_NUM_MSK SHIFT21(0xf) |
| #define UTMI_TEST_GRP_0_REG_FIFO_FILL_NUM_BASE 21 |
| /* REG_SQ_SYNC_SEL */ |
| #define UTMI_TEST_GRP_0_REG_SQ_SYNC_SEL BIT_20 |
| /* REG_FIFO_FILL_SEL */ |
| #define UTMI_TEST_GRP_0_REG_FIFO_FILL_SEL BIT_19 |
| /* REG_FIFO_OVUF_SEL */ |
| #define UTMI_TEST_GRP_0_REG_FIFO_OVUF_SEL BIT_18 |
| #define UTMI_TEST_GRP_0_REG_UTMI_LAT BIT_17 /* REG_UTMI_LAT */ |
| #define UTMI_TEST_GRP_0_REG_FIFO_SP BIT_16 /* REG_FIFO_SP */ |
| /* REG_FIFO_SQ_RST */ |
| #define UTMI_TEST_GRP_0_REG_FIFO_SQ_RST BIT_15 |
| /* REG_CLK_OUT_SEL */ |
| #define UTMI_TEST_GRP_0_REG_CLK_OUT_SEL BIT_14 |
| /* REG_EARLY_TX_ENABLE */ |
| #define UTMI_TEST_GRP_0_REG_EARLY_TX_ENABLE BIT_13 |
| /* REG_OVUF_RST_EN */ |
| #define UTMI_TEST_GRP_0_REG_OVUF_RST_EN BIT_12 |
| /* REG_EOP_RST_EN */ |
| #define UTMI_TEST_GRP_0_REG_EOP_RST_EN BIT_11 |
| /* REG_SYNC_NUM[1:0] */ |
| #define UTMI_TEST_GRP_0_REG_SYNC_NUM_MSK SHIFT9(0x3) |
| #define UTMI_TEST_GRP_0_REG_SYNC_NUM_BASE 9 |
| /* REG_TEST_FIFO_R_POL */ |
| #define UTMI_TEST_GRP_0_REG_TEST_FIFO_R_POL BIT_8 |
| /* REG_TEST_FIFO_W_POL */ |
| #define UTMI_TEST_GRP_0_REG_TEST_FIFO_W_POL BIT_7 |
| /* REG_TEST_FIFO_EN */ |
| #define UTMI_TEST_GRP_0_REG_TEST_FIFO_EN BIT_6 |
| #define UTMI_TEST_GRP_0_TESTMON_MSK SHIFT0(0x3f) /* TESTMON[5:0] */ |
| #define UTMI_TEST_GRP_0_TESTMON_BASE 0 |
| |
| /* UTMI_TEST_GRP_1 0x001C Test Group 1 Register */ |
| /* REG_HS_HDL_SYNC */ |
| #define UTMI_TEST_GRP_1_REG_HS_HDL_SYNC BIT_31 |
| /* REG_FS_HDL_OPMD */ |
| #define UTMI_TEST_GRP_1_REG_FS_HDL_OPMD BIT_30 |
| /* REG_PAD_STRENGTH[4:0] */ |
| #define UTMI_TEST_GRP_1_REG_PAD_STRENGTH_MSK SHIFT25(0x1f) |
| #define UTMI_TEST_GRP_1_REG_PAD_STRENGTH_BASE 25 |
| /* Bit(s) UTMI_TEST_GRP_1_RSRV_24_21 reserved */ |
| /* REG_TEST_DIG_LPBK */ |
| #define UTMI_TEST_GRP_1_REG_TEST_DIG_LPBK BIT_20 |
| /* REG_TEST_SKIP[2:0] */ |
| #define UTMI_TEST_GRP_1_REG_TEST_SKIP_MSK SHIFT17(0x7) |
| #define UTMI_TEST_GRP_1_REG_TEST_SKIP_BASE 17 |
| /* REG_TEST_FLAG */ |
| #define UTMI_TEST_GRP_1_REG_TEST_FLAG BIT_16 |
| /* REG_TEST_DONE */ |
| #define UTMI_TEST_GRP_1_REG_TEST_DONE BIT_15 |
| /* REG_TEST_LENGTH[1:0] */ |
| #define UTMI_TEST_GRP_1_REG_TEST_LENGTH_MSK SHIFT13(0x3) |
| #define UTMI_TEST_GRP_1_REG_TEST_LENGTH_BASE 13 |
| /* REG_TEST_TX_PATTERN[7:0] */ |
| #define UTMI_TEST_GRP_1_REG_TEST_TX_PATTERN_MSK SHIFT5(0xff) |
| #define UTMI_TEST_GRP_1_REG_TEST_TX_PATTERN_BASE 5 |
| /* REG_TEST_MODE[1:0] */ |
| #define UTMI_TEST_GRP_1_REG_TEST_MODE_MSK SHIFT3(0x3) |
| #define UTMI_TEST_GRP_1_REG_TEST_MODE_BASE 3 |
| /* REG_TEST_LPBK_EN */ |
| #define UTMI_TEST_GRP_1_REG_TEST_LPBK_EN BIT_2 |
| /* REG_TEST_BYPASS */ |
| #define UTMI_TEST_GRP_1_REG_TEST_BYPASS BIT_1 |
| /* REG_TEST_EN */ |
| #define UTMI_TEST_GRP_1_REG_TEST_EN BIT_0 |
| |
| /* UTMI_TEST_GRP_2 0x0020 Test Group 2 Register */ |
| /* REG_TEST_FIFO_R_PNT[15:0] */ |
| #define UTMI_TEST_GRP_2_REG_TEST_FIFO_R_PNT_MSK SHIFT16(0xffff) |
| #define UTMI_TEST_GRP_2_REG_TEST_FIFO_R_PNT_BASE 16 |
| /* REG_TEST_FIFO_W_PNT[15:0] */ |
| #define UTMI_TEST_GRP_2_REG_TEST_FIFO_W_PNT_MSK SHIFT0(0xffff) |
| #define UTMI_TEST_GRP_2_REG_TEST_FIFO_W_PNT_BASE 0 |
| |
| /* UTMI_ID_GRP 0x0024 ID Group Register */ |
| #define UTMI_ID_GRP_RESERVE_MSK SHIFT16(0x3ff) /* RESERVE[9:0] */ |
| #define UTMI_ID_GRP_RESERVE_BASE 16 |
| #define UTMI_ID_GRP_RESV_ID_MSK SHIFT0(0xffff) /* RESV_ID[15:0] */ |
| #define UTMI_ID_GRP_RESV_ID_BASE 0 |
| |
| /* UTMI_USB_INT 0x0028 ID Group Register */ |
| /* Bit(s) UTMI_USB_INT_RSRV_31_4 reserved */ |
| #define UTMI_USB_INT_RESUME_INT BIT_3 /* RESUME_INT */ |
| /* Bit(s) UTMI_USB_INT_RSRV_2 reserved */ |
| #define UTMI_USB_INT_LINE_INT_EN BIT_1 /* LINE_INT_EN */ |
| #define UTMI_USB_INT_INTERRUPT BIT_0 /* INTERRUPT */ |
| |
| /* UTMI_DBG_CTL 0x002C ID Group Register */ |
| /* Bit(s) UTMI_DBG_CTL_RSRV_15_0 reserved */ |
| |
| /* UTMI_CTL1 0x0030 ID Group Register */ |
| /* Bit(s) UTMI_CTL1_RSRV_15_9 reserved */ |
| #define UTMI_CTL1_ULPI_PHY_ENABLE BIT_8 /* ULPI_PHY_ENABLE */ |
| #define UTMI_CTL1_RTC_MSK SHIFT6(0x3) /* RTC */ |
| #define UTMI_CTL1_RTC_BASE 6 |
| #define UTMI_CTL1_WTC_MSK SHIFT4(0x3) /* WTC */ |
| #define UTMI_CTL1_WTC_BASE 4 |
| /* Bit(s) UTMI_CTL1_RSRV_3 reserved */ |
| #define UTMI_CTL1_USB_RESUME_PU_PLL_EN BIT_2 /* USB_RESUME_PU_PLL_EN */ |
| #define UTMI_CTL1_PDWN BIT_1 /* PDWN */ |
| #define UTMI_CTL1_CLKEN BIT_0 /* CLKEN */ |
| |
| /* UTMI_TEST_GRP_3 0x0034 Test Group 3 Register */ |
| /* REG_FS_EOP_MODE */ |
| #define UTMI_TEST_GRP_3_REG_FS_EOP_MODE BIT_31 |
| /* REG_HOST_DISCON_SEL1 */ |
| #define UTMI_TEST_GRP_3_REG_HOST_DISCON_SEL1 BIT_30 |
| /* REG_HOST_DISCON_SEL0 */ |
| #define UTMI_TEST_GRP_3_REG_HOST_DISCON_SEL0 BIT_29 |
| /* REG_TEST_TX_BITSTUFF_EN */ |
| #define UTMI_TEST_GRP_3_REG_TEST_TX_BITSTUFF_EN BIT_28 |
| /* REG_TEST_TERM_SELECT */ |
| #define UTMI_TEST_GRP_3_REG_TEST_TERM_SELECT BIT_27 |
| /* REG_TEST_SUSPENDM */ |
| #define UTMI_TEST_GRP_3_REG_TEST_SUSPENDM BIT_26 |
| /* REG_TEST_RESET */ |
| #define UTMI_TEST_GRP_3_REG_TEST_RESET BIT_25 |
| /* REG_TEST_XVCR_SELECT[1:0] */ |
| #define UTMI_TEST_GRP_3_REG_TEST_XVCR_SELECT_MSK SHIFT23(0x3) |
| #define UTMI_TEST_GRP_3_REG_TEST_XVCR_SELECT_BASE 23 |
| /* REG_TEST_OP_MODE[1:0] */ |
| #define UTMI_TEST_GRP_3_REG_TEST_OP_MODE_MSK SHIFT21(0x3) |
| #define UTMI_TEST_GRP_3_REG_TEST_OP_MODE_BASE 21 |
| /* REG_TEST_UTMI_SEL */ |
| #define UTMI_TEST_GRP_3_REG_TEST_UTMI_SEL BIT_20 |
| /* REG_FS_RX_ERROR_MODE2 */ |
| #define UTMI_TEST_GRP_3_REG_FS_RX_ERROR_MODE2 BIT_19 |
| /* REG_FS_RX_ERROR_MODE1 */ |
| #define UTMI_TEST_GRP_3_REG_FS_RX_ERROR_MODE1 BIT_18 |
| /* REG_FS_RX_ERROR_MODE */ |
| #define UTMI_TEST_GRP_3_REG_FS_RX_ERROR_MODE BIT_17 |
| /* REG_FORCE_END_EN */ |
| #define UTMI_TEST_GRP_3_REG_FORCE_END_EN BIT_16 |
| /* REG_EXT_TX_CLK_SEL */ |
| #define UTMI_TEST_GRP_3_REG_EXT_TX_CLK_SEL BIT_15 |
| /* REG_TX_BITSTUFF_ENH */ |
| #define UTMI_TEST_GRP_3_REG_TX_BITSTUFF_ENH BIT_14 |
| /* REG_TX_BITSTUFF_EN */ |
| #define UTMI_TEST_GRP_3_REG_TX_BITSTUFF_EN BIT_13 |
| /* REG_MON_SEL[5:0] */ |
| #define UTMI_TEST_GRP_3_REG_MON_SEL_MSK SHIFT7(0x3f) |
| #define UTMI_TEST_GRP_3_REG_MON_SEL_BASE 7 |
| /* Bit(s) UTMI_TEST_GRP_3_RSRV_6_0 reserved */ |
| |
| /* UTMI_OTG_ADDON 0x003c UTMI OTG Addon Register */ |
| #define UTMI_OTG_ADDON_OTG_ON BIT_0 /* OTG_ON */ |
| |
| /* UTMI_TEST_GRP_4 0x0338 Test Group 4 Register */ |
| #define UTMI_TEST_GRP_4_TP_7_SEL_MSK SHIFT28(0xf) /* TP_7_SEL[3:0] */ |
| #define UTMI_TEST_GRP_4_TP_7_SEL_BASE 28 |
| #define UTMI_TEST_GRP_4_TP_6_SEL_MSK SHIFT24(0xf) /* TP_6_SEL[3:0] */ |
| #define UTMI_TEST_GRP_4_TP_6_SEL_BASE 24 |
| #define UTMI_TEST_GRP_4_TP_5_SEL_MSK SHIFT20(0xf) /* TP_5_SEL[3:0] */ |
| #define UTMI_TEST_GRP_4_TP_5_SEL_BASE 20 |
| #define UTMI_TEST_GRP_4_TP_4_SEL_MSK SHIFT16(0xf) /* TP_4_SEL[3:0] */ |
| #define UTMI_TEST_GRP_4_TP_4_SEL_BASE 16 |
| #define UTMI_TEST_GRP_4_TP_3_SEL_MSK SHIFT12(0xf) /* TP_3_SEL[3:0] */ |
| #define UTMI_TEST_GRP_4_TP_3_SEL_BASE 12 |
| #define UTMI_TEST_GRP_4_TP_2_SEL_MSK SHIFT8(0xf) /* TP_2_SEL[3:0] */ |
| #define UTMI_TEST_GRP_4_TP_2_SEL_BASE 8 |
| #define UTMI_TEST_GRP_4_TP_1_SEL_MSK SHIFT4(0xf) /* TP_1_SEL[3:0] */ |
| #define UTMI_TEST_GRP_4_TP_1_SEL_BASE 4 |
| #define UTMI_TEST_GRP_4_TP_0_SEL_MSK SHIFT0(0xf) /* TP_0_SEL[3:0] */ |
| #define UTMI_TEST_GRP_4_TP_0_SEL_BASE 0 |
| |
| /* UTMI_TEST_GRP_5 0x033C Test Group 5 Register */ |
| #define UTMI_TEST_GRP_5_TP_F_SEL_MSK SHIFT28(0xf) /* TP_F_SEL[3:0] */ |
| #define UTMI_TEST_GRP_5_TP_F_SEL_BASE 28 |
| #define UTMI_TEST_GRP_5_TP_E_SEL_MSK SHIFT24(0xf) /* TP_E_SEL[3:0] */ |
| #define UTMI_TEST_GRP_5_TP_E_SEL_BASE 24 |
| #define UTMI_TEST_GRP_5_TP_D_SEL_MSK SHIFT20(0xf) /* TP_D_SEL[3:0] */ |
| #define UTMI_TEST_GRP_5_TP_D_SEL_BASE 20 |
| #define UTMI_TEST_GRP_5_TP_C_SEL_MSK SHIFT16(0xf) /* TP_C_SEL[3:0] */ |
| #define UTMI_TEST_GRP_5_TP_C_SEL_BASE 16 |
| #define UTMI_TEST_GRP_5_TP_B_SEL_MSK SHIFT12(0xf) /* TP_B_SEL[3:0] */ |
| #define UTMI_TEST_GRP_5_TP_B_SEL_BASE 12 |
| #define UTMI_TEST_GRP_5_TP_A_SEL_MSK SHIFT8(0xf) /* TP_A_SEL[3:0] */ |
| #define UTMI_TEST_GRP_5_TP_A_SEL_BASE 8 |
| #define UTMI_TEST_GRP_5_TP_9_SEL_MSK SHIFT4(0xf) /* TP_9_SEL[3:0] */ |
| #define UTMI_TEST_GRP_5_TP_9_SEL_BASE 4 |
| #define UTMI_TEST_GRP_5_TP_8_SEL_MSK SHIFT0(0xf) /* TP_8_SEL[3:0] */ |
| #define UTMI_TEST_GRP_5_TP_8_SEL_BASE 0 |
| |
| |
| |
| /* -------------------- */ |
| |
| |
| #endif /* __INC_USB_controller_H */ |