| /****************************************************************************** |
| * |
| * Name: DMA.h |
| * Project: Hermon-2 |
| * Purpose: Testing |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * (C)Copyright 2005 - 2011 Marvell. All Rights Reserved. |
| * |
| * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL. |
| * The copyright notice above does not evidence any actual or intended |
| * publication of such source code. |
| * This Module contains Proprietary Information of Marvell and should be |
| * treated as Confidential. |
| * The information in this file is provided for the exclusive use of the |
| * licensees of Marvell. |
| * Such users have the right to use, modify, and incorporate this code into |
| * products for purposes authorized by the license agreement provided they |
| * include this notice and the associated copyright notice with any such |
| * product. |
| * The information in this file is provided "AS IS" without warranty. |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * This file was automatically generated by reg.pl using * DMA.csv |
| * |
| ******************************************************************************/ |
| |
| /****************************************************************************** |
| * |
| * History: |
| * |
| ********* PLEASE INSERT THE CVS HISTORY OF THE PREVIOUS VERSION HERE. ********* |
| *******************************************************************************/ |
| |
| #ifndef __INC_DMA_H |
| #define __INC_DMA_H |
| |
| |
| /* |
| * |
| * THE BASE ADDRESSES |
| * |
| */ |
| #define DMA_BASE 0xD4000000 |
| #define DMA_BASE_2 DMA_BASE // To support cases where DMA_BASE is different for different flash types. |
| |
| /* |
| * |
| * THE REGISTER DEFINES |
| * |
| */ |
| #define DMA_CSR031 (DMA_BASE+0x0000) /* DMA Channel Control/Status |
| * Registers 0-31 Start |
| */ |
| #define DMA_ALGN (DMA_BASE+0x00A0) /* 32 bit DMA Alignment Register */ |
| #define DMA_PCSR (DMA_BASE+0x00A4) /* 32 bit DMA Programmed I/O |
| * Control Status |
| * Register |
| */ |
| #define DMA_RQSR0 (DMA_BASE+0x00E0) /* 32 bit DREQ Status Register 0 */ |
| #define DMA_INT (DMA_BASE+0x00F0) /* 32 bit DMA Interrupt Register */ |
| #define DMA_RCMRX (DMA_BASE+0x0100) /* DMA Request to Channel Map |
| * Registers 0-63 and |
| * 64-99 Start |
| */ |
| #define DMA_DADRX (DMA_BASE+0x0200) /* DMA Descriptor Address Registers Start */ |
| #define DMA_SADRX (DMA_BASE+0x0204) /* DMA Source Address Registers 0-31 |
| * Start |
| */ |
| #define DMA_TADRX (DMA_BASE+0x0208) /* DMA Target Address Registers 0-31 |
| * Start |
| */ |
| #define DMA_CMDX (DMA_BASE+0x020C) /* DMA Command Registers 0-31 Start */ |
| //#define DUMMY_REGISTER (DMA_BASE+0x0000) /* 32 bit This is a Dummy Register */ |
| |
| /* |
| * |
| * THE BIT DEFINES |
| * |
| */ |
| /* DMA_CSR031 0x0000 DMA Channel Control/Status Registers 0-31 */ |
| #define DMA_CSR031_RUN BIT_31 /* Run */ |
| #define DMA_CSR031_NODESCFETCH BIT_30 /* No-Descriptor Fetch */ |
| #define DMA_CSR031_STOPIRQEN BIT_29 /* Stop interrupt enabled */ |
| /* Setting the End-of-Receive interrupt enable */ |
| #define DMA_CSR031_EORIRQEN BIT_28 |
| /* Jump to the next descriptor on EOR */ |
| #define DMA_CSR031_EORJMPEN BIT_27 |
| #define DMA_CSR031_EORSTOPEN BIT_26 /* Stop channel on EOR */ |
| /* Set descriptor compare status */ |
| #define DMA_CSR031_SETCMPST BIT_25 |
| /* Clear descriptor compare status */ |
| #define DMA_CSR031_CLRCMPST BIT_24 |
| /* Request after channel stopped interrupt enable */ |
| #define DMA_CSR031_RASIRQEN BIT_23 |
| #define DMA_CSR031_MASKRUN BIT_22 /* MASKRUN */ |
| /* Bit(s) DMA_CSR031_RSRV_21_11 reserved */ |
| /* Descriptor compare status */ |
| #define DMA_CSR031_CMPST BIT_10 |
| #define DMA_CSR031_EORINT BIT_9 /* End of Receive Interrupt */ |
| #define DMA_CSR031_REQPEND BIT_8 /* Request pending */ |
| /* Bit(s) DMA_CSR031_RSRV_7_5 reserved */ |
| /* Request after channel stopped */ |
| #define DMA_CSR031_RASINTR BIT_4 |
| #define DMA_CSR031_STOPINTR BIT_3 /* Stop interrupt */ |
| #define DMA_CSR031_ENDINTR BIT_2 /* End interrupt */ |
| #define DMA_CSR031_STARTINTR BIT_1 /* Start interrupt */ |
| #define DMA_CSR031_BUSERRINTR BIT_0 /* Bus error interrupt */ |
| |
| /* DMA_ALGN 0x00A0 DMA Alignment Register */ |
| /* Alignment control for channel x */ |
| #define DMA_ALGN_DALGNX_MSK SHIFT0(0xffffffff) |
| #define DMA_ALGN_DALGNX_BASE 0 |
| |
| /* DMA_PCSR 0x00A4 DMA Programmed I/O Control Status Register */ |
| /* Activate posted writes and split reads */ |
| #define DMA_PCSR_BRGSPLIT BIT_31 |
| /* Bit(s) DMA_PCSR_RSRV_30_1 reserved */ |
| #define DMA_PCSR_BRGBUSY BIT_0 /* Bridge busy status */ |
| |
| /* DMA_RQSR0 0x00E0 DREQ Status Register 0 */ |
| /* Bit(s) DMA_RQSR0_RSRV_31_9 reserved */ |
| /* Clearing pending request */ |
| #define DMA_RQSR0_CLR BIT_8 |
| /* Bit(s) DMA_RQSR0_RSRV_7_5 reserved */ |
| #define DMA_RQSR0_REQPEND_MSK SHIFT0(0x1f) /* Request pending */ |
| #define DMA_RQSR0_REQPEND_BASE 0 |
| |
| /* DMA_INT 0x00F0 DMA Interrupt Register */ |
| #define DMA_INT_CHLINTRX_MSK SHIFT0(0xffffffff) /* Channel interrupt */ |
| #define DMA_INT_CHLINTRX_BASE 0 |
| |
| /* DMA_RCMRx 0x0100 DMA Request to Channel Map Registers 0-63 and 64-99 */ |
| /* Bit(s) DMA_RCMRX_RSRV_31_8 reserved */ |
| #define DMA_RCMRX_MAPVLD BIT_7 /* Map valid channel */ |
| /* Bit(s) DMA_RCMRX_RSRV_6_5 reserved */ |
| #define DMA_RCMRX_CHLNUM_MSK SHIFT0(0x1f) /* Channel number */ |
| #define DMA_RCMRX_CHLNUM_BASE 0 |
| |
| /* DMA_DADRx 0x0200 DMA Descriptor Address Registers */ |
| /* Descriptor address */ |
| #define DMA_DADRX_DESCRIPTOR_ADDRESS_MSK SHIFT4(0xfffffff) |
| #define DMA_DADRX_DESCRIPTOR_ADDRESS_BASE 4 |
| /* Bit(s) DMA_DADRX_RSRV_3_2 reserved */ |
| /* Enable Descriptor Branch */ |
| #define DMA_DADRX_BREN BIT_1 |
| #define DMA_DADRX_STOP BIT_0 /* Stop */ |
| |
| /* DMA_SADRx 0x0204 DMA Source Address Registers 0-31 */ |
| #define DMA_SADRX_SRCADDR_MSK SHIFT3(0x1fffffff) /* Source address */ |
| #define DMA_SADRX_SRCADDR_BASE 3 |
| #define DMA_SADRX_SRCADDR2 BIT_2 /* SRCADDR2 */ |
| #define DMA_SADRX_SRCADDR0_MSK SHIFT0(0x3) /* SRCADDR0 */ |
| #define DMA_SADRX_SRCADDR0_BASE 0 |
| |
| /* DMA_TADRx 0x0208 DMA Target Address Registers 0-31 */ |
| #define DMA_TADRX_TRGADDR_MSK SHIFT3(0x1fffffff) /* Target address */ |
| #define DMA_TADRX_TRGADDR_BASE 3 |
| #define DMA_TADRX_TRGADDR2 BIT_2 /* TRGADDR2 */ |
| #define DMA_TADRX_TRGADDR0_MSK SHIFT0(0x3) /* TRGADDR0 */ |
| #define DMA_TADRX_TRGADDR0_BASE 0 |
| |
| /* DMA_CMDx 0x020C DMA Command Registers 0-31 */ |
| #define DMA_CMDX_INCSRCADDR BIT_31 /* Source address increment */ |
| #define DMA_CMDX_INCTRGADDR BIT_30 /* Target address increment */ |
| #define DMA_CMDX_FLOWSRC BIT_29 /* Source flow control */ |
| #define DMA_CMDX_FLOWTRG BIT_28 /* Target flow control */ |
| /* Bit(s) DMA_CMDX_RSRV_27_26 reserved */ |
| /* Descriptor compare enable */ |
| #define DMA_CMDX_CMPEN BIT_25 |
| /* Bit(s) DMA_CMDX_RSRV_24 reserved */ |
| #define DMA_CMDX_ADDRMODE BIT_23 /* ADDRMODE */ |
| #define DMA_CMDX_STARTIRQEN BIT_22 /* STARTIRQEN */ |
| #define DMA_CMDX_ENDIRQEN BIT_21 /* End interrupt enable */ |
| /* Bit(s) DMA_CMDX_RSRV_20_18 reserved */ |
| #define DMA_CMDX_SIZE_MSK SHIFT16(0x3) /* Maximum burst size */ |
| #define DMA_CMDX_SIZE_BASE 16 |
| #define DMA_CMDX_WIDTH_MSK SHIFT14(0x3) /* WIDTH */ |
| #define DMA_CMDX_WIDTH_BASE 14 |
| /* Bit(s) DMA_CMDX_RSRV_13 reserved */ |
| /* Length of the transfer in bytes */ |
| #define DMA_CMDX_LEN_MSK SHIFT0(0x1fff) |
| #define DMA_CMDX_LEN_BASE 0 |
| |
| /* DUMMY_REGISTER 0x0000 This is a Dummy Register */ |
| #define DUMMY_REGISTER_DUMMY_MSK SHIFT0(0xffffffff) /* Ignore this register */ |
| #define DUMMY_REGISTER_DUMMY_BASE 0 |
| |
| |
| typedef enum |
| { |
| DMAC_UART1_RX = 4, |
| DMAC_UART1_TX = 5, |
| |
| DMAC_GSSP_RX = 6, |
| DMAC_GSSP_TX = 7, |
| |
| DMAC_USIM1_RX = 8, |
| DMAC_USIM1_TX = 9, |
| DMAC_USIM2_RX = 10, |
| DMAC_USIM2_TX = 11, |
| |
| DMAC_APB_E_Cipher = 12, |
| |
| DMAC_UART2_RX = 21, |
| DMAC_UART2_TX = 22, |
| DMAC_UART3_RX = 23, |
| DMAC_UART3_TX = 24, |
| |
| DMAC_SSP_0_RX = 52, |
| DMAC_SSP_0_TX = 53, |
| |
| DMAC_SSP_2_RX = 60, |
| DMAC_SSP_2_TX = 61, |
| |
| DMAC_NAND_DATA = 97, |
| DMAC_NAND_CMD = 99, |
| |
| DMAC_MEM2MEM_MOVE = 255 // RESERVED for Memory to Memory moves |
| }DMAC_DRCMR_T, DMAC_DEVICE_T; |
| |
| /* -------------------- */ |
| |
| |
| #endif /* __INC_DMA_H */ |