marvell/services/dxslic/api_lib/src/dxs_access.h

#ifndef __DXS_ACCESS_H__
#define __DXS_ACCESS_H__
/******************************************************************************

  Copyright (c) 2006-2015 Lantiq Deutschland GmbH
  Copyright (c) 2015 Lantiq Beteiligungs-GmbH & Co.KG
  Copyright 2018, Intel Corporation.

  For licensing information, see the file 'LICENSE' in the root folder of
  this software module.

******************************************************************************/

/**
   \file dxs_access.h
   Low level access macros and functions declarations.
*/

/* ========================================================================== */
/*                                 Includes                                   */
/* ========================================================================== */
#include "dxs_lib.h"
#include <stdio.h>

/* ========================================================================== */
/*                             Macro definitions                              */
/* ========================================================================== */

/* Define the maximum number of bytes that the SPI interface can transfer with
   one call to the interface.
   This driver will fragment all data during read or write transfer into pieces
   no larger than the value given here. To avoid overhead due to fragmentation
   use the maximum value the SPI interface can support.
   Possible values are calculated by (2+4*n) with n=1,2, ...
   The minimum possible value is 6 bytes. There is no upper limit but values
   larger than 34 bytes are never used by the DXS driver. */
#define SPI_MAXBYTES_SIZE     30
#define SPI_MAX_BUFF_SIZE_CSI 6

#define DXS_REG_CFG       0x06
#define DXS_REG_IEN1      0x08
#define DXS_REG_STAT1     0x0C
#define DXS_REG_INT1      0x10
#define DXS_REG_IEN2      0x0A
#define DXS_REG_STAT2     0x0E
#define DXS_REG_INT2      0x12
#define DXS_REG_DATA      0x14
#define DXS_REG_LEN       0x18
#define DXS_REG_CMD       0x1C
#define DXS_REG_BCFG      0x20
#define DXS_REG_BINF      0x24
/* CSI Master registers */
#define DXS_REG_CSI_M_CFG  0x30
#define DXS_REG_CSI_M_STAT 0x31
#define DXS_REG_CSI_M_CFG_PAUSE_DEFAULT   3
#define DXS_REG_CSI_M_CFG_PDEMUX  (1 << 10)

#define DXS_REG_CFG_RST_MASK        0x0080
#define DXS_REG_CFG_RST_RSTCORE     (0x1 << 7)
#define DXS_REG_CFG_8BIT_EN         (0x1 << 2)
#define DXS_REG_CFG_SC_MD           (0x1 << 1)

#define DXS_REG_BCFG_ASC_MASK       0x00FF
#define DXS_REG_BCFG_ASC_ROM        0x0
#define DXS_REG_BCFG_ASC_SPI        0x3

#define DXS_REG_BINF_BOOTSTATE_MASK 0x00FF

#define DXS_REG_INT1_ERR            1
#define DXS_REG_INT1_CBO_RDY        (1 << 11)

#define DXS_REG_INT2_CBO_UFL        (1 << 9)
#define DXS_REG_INT2_CBI_OFL        (1 << 8)

/*******************************************************************************
 * HOST Interrupt Enable 1 Register
 ******************************************************************************/
/* Reset value */
#define DXS_REG_IEN1_RESET          0x0000
/* Out-Box Ready Interrupt (11) */
#define DXS_REG_IEN1_OBX_RDY        (0x1 << 11)
/* In-Box Empty Interrupt Mask (9) */
#define DXS_REG_IEN1_IBX_EMP        (0x1 << 9)
/* Error Interrupt Mask (0) */
#define DXS_REG_IEN1_ERR            (0x1)

/*******************************************************************************
 * HOST Interrupt Enable 2 Register
 ******************************************************************************/
/* Reset value */
#define DXS_REG_IEN2_RESET          0x0000
/* Out-Box Underflow Interrupt (9) */
#define DXS_REG_IEN2_OBX_UFL        (0x1 << 9)
/* In-Box Overflow Interrupt (8) */
#define DXS_REG_IEN2_IBX_OFL        (0x1 << 8)

/* ========================================================================== */
/*                             Type definitions                               */
/* ========================================================================== */

/* ========================================================================== */
/*                           Function prototypes                              */
/* ========================================================================== */
extern int32_t DXS_RegWrite(
                        DXS_DEVICE_t *pDev,
                        uint8_t offset,
                        uint16_t nValue);

extern int32_t DXS_RegRead(
                        DXS_DEVICE_t *pDev,
                        uint8_t offset,
                        uint16_t *pValue);

extern int32_t DXS_RegWriteMulti(
                        DXS_DEVICE_t *pDev,
                        uint8_t offset,
                        uint16_t *nValue,
                        uint8_t count);

extern int32_t DXS_RegReadMulti(
                        DXS_DEVICE_t *pDev,
                        uint8_t offset,
                        uint16_t *pValue,
                        uint8_t count);

extern void DXS_cpw2b ( uint8_t *pBbuf,
                        const uint16_t * const pWbuf,
                        const uint32_t nWoffset,
                        const uint32_t nB);

extern void DXS_cpb2w ( uint16_t *pWbuf,
                        const uint8_t * const pBbuf,
                        uint32_t nB);
extern void DXS_cpb2dw ( uint32_t *pWbuf,
                        const uint8_t * const pBbuf,
                        uint32_t nB);
extern uint32_t DXS_spi_blocksize_get(DXS_DEVICE_t *pDev);
extern void DXS_StatusGet(DXS_DEVICE_t *pDev);

extern int32_t dxs_spi_write(
                        int fd,
                        uint8_t offset,
                        uint16_t *pbuf,
                        uint32_t len);

extern int32_t dxs_spi_read(
                        int fd,
                        uint8_t offset,
                        uint16_t *pbuf,
                        uint32_t len);
#endif /* __DXS_ACCESS_H__ */