marvell/uboot/arch/arm/include/asm/arch-asr1802s/cpu.h

/*
 * (C) Copyright 2018
 * ASR Microelectronics (Shanghai) Co., Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _ASR_CPU_H
#define _ASR_CPU_H

#include <asm/io.h>
#include <asm/system.h>
#include <asm/armv7.h>

/* Stepping check */
#define cpu_is_asr1802() \
       (((readl(ASR1802_CIU_BASE)) & 0xfff0) == 0x1802)
#define cpu_is_asr1802s() \
       (((readl(ASR1802_CIU_BASE)) & 0xffffff) == 0xc01802)
#define cpu_is_asr1803() \
       (((readl(ASR1802_CIU_BASE)) & 0xffff) == 0x1803)
#define cpu_is_asr1803_a0() \
       (((readl(ASR1802_CIU_BASE)) & 0xffffff) == 0xa01803)
#define cpu_is_asr1803_a1() \
       (((readl(ASR1802_CIU_BASE)) & 0xffffff) == 0xa11803)
#define cpu_is_asr1803_z1() \
       (((readl(ASR1802_CIU_BASE)) & 0xffffff) == 0x001803)
#define cpu_is_asr1826s() \
       (((readl(ASR1802_CIU_BASE)) & 0xffff) == 0x1829)
#define cpu_is_asr1901() \
       (((readl(ASR1802_CIU_BASE)) & 0xffff) == 0x1901)
#define cpu_is_asr1806() \
       (((readl(ASR1802_CIU_BASE)) & 0xffff) == 0x1806)
#define cpu_is_asr1903() \
       (((readl(ASR1802_CIU_BASE)) & 0xffff) == 0x1903)
#define cpu_is_asr1903_z1() \
       (((readl(ASR1802_CIU_BASE)) & 0xffffff) == 0xf01903)
#define cpu_is_asr1903_a0() \
       (((readl(ASR1802_CIU_BASE)) & 0xffffff) == 0xa01903)
#define cpu_is_asr1903_b0() \
       (((readl(ASR1802_CIU_BASE)) & 0xffffff) == 0xb01903)
#define cpu_is_asr1906() \
       (((readl(ASR1802_CIU_BASE)) & 0xffff) == 0x1906)

/*
 * APB CP Clock Reset/Control Registers
 */
struct asr1802apbcp_registers {
	u8 pad0[0x1c - 4];
	u32 uart0;	/*0x1c cp uart*/
	u8 pad1[0x28 - 0x1c - 4];
	u32 twsi;	/*0x28*/
};

/*
 * Timer registers
 */
struct asr1802tmr_registers {
	u32 cer;		/* Timer count enable reg */
	u32 cmr;
	u32 crsr;
	u32 clk_ctrl;		/* Timer clk control reg */
	u32 match[12];		/* Timer match registers -0x10 */
	u32 preload[4];		/* Timer preload value - 0x40 */
	u32 preload_ctrl[4];/* 0x50 */
	u32 ie[4]; /* 0x60 */
	u32 icr[4]; /* 0x70 */
	u32 status[4]; /* 0x80 */
	u32 count[4];		/* Timer count registers - 0x90 */
	u32 reserved[4]; /* 0xa0 */
	u32 wfar; /* 0xb0 */
	u32 wsar;
	u32 wmer;
	u32 wmr;
	u32 wsr;
	u32 wicr;
	u32 wcr;
	u32 wvr;
};

/*
 * scsrtc registers
 */
struct scsrtc_registers {
	u8 padding[0x1c];
	u32 dcs_mode;
};

/* GEU Register Offset */
#define ASR1806_GEU_BANK0_159_128	(0x4A8)
#define ASR1903_GEU_BANK0_240_208	(0x414)
#define ASR1903_GEU_BANK0_255_240	(0x4C8)
#define ASR1903_GEU_BANK3_255_224	(0x420)
#define APB_SPARE14_REG     (ASR1802_APBSPARE_BASE + 0x134)

extern u32 asr1802_sdram_base(int chip_sel, u32 base);

extern u32 smp_hw_cpuid(void);

extern bool board_is_scs_mode(void);

#ifdef CONFIG_PXA_AMP_SUPPORT
extern void pxa_cpu_reset(int cpu, u32 addr);
#endif

#endif /* _ASR_CPU_H */