marvell/uboot/arch/arm/include/asm/arch-asr1901/cpu.h

/*
 * (C) Copyright 2021
 * ASR Microelectronics (Shanghai) Co., Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ASR1901_CPU__H__
#define __ASR1901_CPU__H__

#include <asm/io.h>
#include <asm/system.h>
#include <asm/armv7.h>

/* Stepping check */
#define cpu_is_asr1802() \
       (((readl(ASR1901_CIU_BASE)) & 0xfff0) == 0x1802)
#define cpu_is_asr1802s() \
       (((readl(ASR1901_CIU_BASE)) & 0xffffff) == 0xc01802)
#define cpu_is_asr1803() \
       (((readl(ASR1901_CIU_BASE)) & 0xffff) == 0x1803)
#define cpu_is_asr1803_a0() \
       (((readl(ASR1901_CIU_BASE)) & 0xffffff) == 0xa01803)
#define cpu_is_asr1803_z1() \
       (((readl(ASR1901_CIU_BASE)) & 0xffffff) == 0x001803)
#define cpu_is_asr1826s() \
       (((readl(ASR1901_CIU_BASE)) & 0xffff) == 0x1829)
#define cpu_is_asr1901() \
       (((readl(ASR1901_CIU_BASE)) & 0xffff) == 0x1901)
#define cpu_is_asr1901_z1() \
       (((readl(ASR1901_CIU_BASE)) & 0xffffff) == 0xc01901)
#define cpu_is_asr1901_z2() \
       (((readl(ASR1901_CIU_BASE)) & 0xffffff) == 0xc11901)
#define cpu_is_asr1901_a0() \
       (((readl(ASR1901_CIU_BASE)) & 0xffffff) == 0xa01901)
#define cpu_is_asr1901_a0_plus() \
       (((readl(ASR1901_CIU_BASE)) & 0xf0ffff) == 0xa01901)

#define cpu_is_asr1806() \
       (((readl(ASR1901_CIU_BASE)) & 0xffff) == 0x1806)

#define cpu_is_asr1903() \
       (((readl(ASR1901_CIU_BASE)) & 0xffff) == 0x1903)
#define cpu_is_asr1903_z1() \
       (((readl(ASR1901_CIU_BASE)) & 0xffffff) == 0xf01903)
#define cpu_is_asr1903_a0() \
       (((readl(ASR1901_CIU_BASE)) & 0xffffff) == 0xa01903)
#define cpu_is_asr1903_b0() \
       (((readl(ASR1901_CIU_BASE)) & 0xffffff) == 0xb01903)

#define cpu_is_asr1906() \
       (((readl(ASR1901_CIU_BASE)) & 0xffff) == 0x1906)

/*
 * Application Power Management (APMU) Registers
 * Refer Register Datasheet 9.2
 */
struct asr1901apmu_registers {
	u8 pad0[0x0044];
	u32 dsi;	/*0x0044*/
	u8 pad1[0x004c - 0x044 - 4];
	u32 lcd_dsi;	/*0x004c*/
	u8 pad2[0x0054 - 0x04c - 4];
	u32 sd0;	/*0x0054*/
	u8 pad3[0x005c - 0x054 - 4];
	u32 usb;	/*0x005c*/
	u8 pad4[0x00e0 - 0x05c - 4];
	u32 sd2;	/*0x00e0*/
};

/*
 * APB Clock Reset/Control Registers
 * Refer Register Datasheet 6.14
 */
struct asr1901apbc_registers {
	u32 uart1;	/*0x000 ap uart*/
	u32 uart2;	/*0x004 ap uart*/
	u32 gpio;	/*0x008*/
	u8 pad0[0x02c - 0x08 - 4];
	u32 twsi0;	/*0x02c*/
	u8 pad1[0x034 - 0x2c - 4];
	u32 timers;	/*0x034*/
	u8 pad2[0x060 - 0x034 - 4];
	u32 twsi1;	/*0x60*/
	u8 pad3[0x070 - 0x060 - 4];
	u32 twsi2;	/*0x70*/
	u32 twsi3;	/*0x74*/
	u32 uart3;	/*0x78*/
};

/*
 * APB CP Clock Reset/Control Registers
 */
struct asr1901apbcp_registers {
	u8 pad0[0x1c - 4];
	u32 uart0;	/*0x1c cp uart*/
	u8 pad1[0x28 - 0x1c - 4];
	u32 twsi;	/*0x28*/
};

/*
 * CPU Interface Registers
 * Refer Register Datasheet 4.3
 */
struct asr1901cpu_registers {
	u32 chip_id;		/* Chip Id Reg */
	u32 pad0;
	u32 cpu_conf;		/* CPU Conf Reg */
	u32 pad1;
	u32 cpu_sram_spd;	/* CPU SRAM Speed Config Register */
	u32 pad2;
	u32 cpu_l2c_spd;	/* CPU L2cache Speed Config Conf */
	u32 mcb_conf0;		/* MCB Conf Reg */
	u32 sys_boot_ctl;	/* Sytem Boot Control */
};

/*
 * Timer registers
 */
struct asr1901tmr_registers {
	u32 cer;		/* Timer count enable reg */
	u32 cmr;
	u32 crsr;
	u32 clk_ctrl;		/* Timer clk control reg */
	u32 match[12];		/* Timer match registers -0x10 */
	u32 preload[4];		/* Timer preload value - 0x40 */
	u32 preload_ctrl[4];/* 0x50 */
	u32 ie[4]; /* 0x60 */
	u32 icr[4]; /* 0x70 */
	u32 status[4]; /* 0x80 */
	u32 count[4];		/* Timer count registers - 0x90 */
	u32 reserved[4]; /* 0xa0 */
	u32 wfar; /* 0xb0 */
	u32 wsar;
	u32 wmer;
	u32 wmr;
	u32 wsr;
	u32 wicr;
	u32 wcr;
	u32 wvr;
};

/*
 * apb_spare registers
 */
struct apbspare_registers {
	u8 padding[0x10C];
	u32 apb_spare4;
	u32 apb_spare5;
};

/*
 * scsrtc registers
 */
struct scsrtc_registers {
	u8 padding[0x1c];
	u32 dcs_mode;
};

#define APB_SPARE14_REG     (ASR1901_CIU_BASE + 0x134)

extern u32 asr1901_sdram_base(int chip_sel, u32 base);

extern u32 smp_hw_cpuid(void);

#ifdef CONFIG_PXA_AMP_SUPPORT
extern void pxa_cpu_reset(int cpu, u32 addr);
#endif

#endif /* ASR1901 */