marvell/uboot/board/Marvell/common/asr_common.h

#ifndef __ASR_COMMON_H__
#define __ASR_COMMON_H__

#include "asr_flag.h"

#include "asr_flash.h"
#include "mv_cp.h"
#include "tim.h"

struct cp_img_flash_layout
{
	u32 arbel_offset;
	u32 msa_offset;
	u32 rf_offset;
	u32 bx2_offset;
	u32 cp_rd_offset;
	u32 cp_rd_bk_offset;
	u32 ap_rd_offset;
	u32 ap_rd_bk_offset;
	u32 nvm_tbl_size;
	struct nvm_load_info *nvm_tbl;
}; 

struct ap_img_info
{
	u32 image_id;
	u32 load_addr;
	u32 flash_offset;
	u32 image_size;
};

enum nsaid_perm {
	DDR_PERM_RW,
	DDR_PERM_RD,
	DDR_PERM_WR,
	DDR_PERM_ABORT,
};

union nsaid_perm_desc {
	struct {
		u32 range0_perm:2;
		u32 range1_perm:2;
		u32 range2_perm:2;
		u32 range3_perm:2;
		u32 range4_perm:2;
		u32 range5_perm:2;
		u32 range6_perm:2;
		u32 range7_perm:2;
		u32 range8_perm:2;
		u32 range9_perm:2;
		u32 rangea_perm:2;
		u32 rangeb_perm:2;
		u32 rangec_perm:2;
		u32 ranged_perm:2;
		u32 rangee_perm:2;
		u32 rangef_perm:2;
	} b;

	u32 value;
};

struct nsaid_range_desc {
	u32 buff_start;
	u32 buff_end;
	union nsaid_perm_desc perm_desc;
};

/* resever a 128 bytes(0x300 to 0x380) structure to save asr memory flags */
struct asr_mflag {
	u32 reserved1[0x28 / sizeof(u32)];

	u32 diag_buff_magic;
	u32 diag_buff_addr;
	u32 diag_buff_len;

	u32 fastboot_flag;		/* fast boot mode flag, offset 0x34 */
	u32 ubifs_error_magic;		/* ubifs error magic offset 0x38 */
	u32 ubifs_error_type;		/* ubifs error magic offset 0x3c */
	u32 reserved2[0x40 / sizeof(u32)];
} __attribute__ ((__packed__));

#define ASR_MFLAG_OFFSET_FROM_CRASHKERNEL	(0x300)

#define AP_DIAG_BUF_SET_MAGIC           (0x41504447)  /* APDG */
#define AP_DIAG_BUF_SET_MAGIC2          (0x41504467)  /* APDg */

#define CONFIG_MAX_DIAG_BUFF_LEN	(12 * 1024 * 1024)

#define CONFIG_DIAG_BUF_START_ADDR	(36 * 1024* 1024)	/* none tos mode diag buff start address */


#define DDR_RANGE_ACCESS_CTRL	(0xc000007c)
#define DDR_RANGE0_LOW_CFG		(0xc0000080)
#define DDR_RANGE0_HIGH_CFG		(0xc0000084)

#define DDR_ADC_ERR_INFO		(0xc0000150)

#define DDR_RANGE0_TOP_LOW_CFG	(0xc0000A40)
#define DDR_RANGE0_TOP_HIGH_CFG	(0xc0000A44)

#define DDR_RANGE0_MASK_CFG		(0xc0000A00)

#define NSAID_ALL_READ_ONLY		(0x55555555)
#define NSAID_ALL_READ_WRITE	(0x00000000)
#define NSAID_ALL_WRITE_ONLY	(0xAAAAAAAA)
#define NSAID_ALL_ABORT			(0xFFFFFFFF)

#define NR_NSAID_RANGES			(16)


#define BOOT_LOG_MAGIC 0x42474f4c      /* "LOGB" */

#define BOARD_ID_MAGIC 0x44494442      /* "BDID" */

enum BOARD_ID {
	ASR1901_P5N = 5,
};

pTIM asr_get_dtim_primary(void);
int asr_load_verify_ap_images(struct ap_img_info * ap_imgs, int num);
int set_nocp_mode(int nocpmode);
int asr_load_verify_cp_images(u32 cpbt_mode, struct cp_img_flash_layout *lwg_layout);

int asr_get_sim_lock_fuse(void);

void nsaid_config_one_range(struct nsaid_range_desc *desc);
void nsaid_basic_init(void);
extern u32 extern_get_prod_mode(void);
extern int extern_get_cpmem(void);
extern int do_uboot_mem_test(u32 ddr_end_addr, u32 sec_ddr_start, u32 sec_ddr_end);
extern struct asr_mflag * get_asr_mflag(void);
extern u32 get_mem_size_bytes(void);
extern int prepare_ap_diag_buff(u32 buff_st, u32 buf_end);


#ifdef CONFIG_PXA182X
#include <asm/arch/pxa182x.h>
#endif

#ifdef CONFIG_ASR1802S
#include <asm/arch/asr1802.h>
#endif

#endif