| /* |
| * (C) Copyright 2012 |
| * Marvell Semiconductor <www.marvell.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| #include "panel.h" |
| |
| static u8 exit_sleep[] = {0x11}; |
| static u8 display_on[] = {0x29}; |
| static u8 sleep_in[] = {0x10}; |
| static u8 display_off[] = {0x28}; |
| |
| #define NT35565_SLEEP_OUT_DELAY 200 |
| #define NT35565_SLEEP_IN_DELAY 200 |
| #define NT35565_DISP_ON_DELAY 0 |
| #define NT35565_DISP_OFF_DELAY 0 |
| |
| static struct dsi_cmd_desc nt35565_video_display_on_cmds[] = { |
| {DSI_DI_DCS_SWRITE, 1, NT35565_SLEEP_OUT_DELAY, sizeof(exit_sleep), |
| exit_sleep}, |
| {DSI_DI_DCS_SWRITE, 1, NT35565_DISP_ON_DELAY, sizeof(display_on), |
| display_on}, |
| }; |
| |
| void panel_qhd_init_config(struct mmp_disp_info *fbi) |
| { |
| dsi_cmd_array_tx(fbi, nt35565_video_display_on_cmds, |
| ARRAY_SIZE(nt35565_video_display_on_cmds)); |
| } |
| |
| static struct dsi_cmd_desc video_display_off_cmds[] = { |
| {DSI_DI_DCS_SWRITE, 1, 0, sizeof(display_off), |
| display_off}, |
| {DSI_DI_DCS_SWRITE, 1, 0, sizeof(sleep_in), |
| sleep_in}, |
| }; |
| |
| void panel_exit_config(struct mmp_disp_info *fbi) |
| { |
| dsi_cmd_array_tx(fbi, video_display_off_cmds, |
| ARRAY_SIZE(video_display_off_cmds)); |
| } |
| |
| static u8 manufacturer_cmd_access_protect[] = {0xB0, 0x04}; |
| static u8 backlight_ctrl[] = {0xCE, 0x00, 0x01, 0x88, 0xC1, 0x00, 0x1E, 0x04}; |
| static u8 nop[] = {0x0}; |
| static u8 seq_test_ctrl[] = {0xD6, 0x01}; |
| static u8 write_display_brightness[] = {0x51, 0x0F, 0xFF}; |
| static u8 write_ctrl_display[] = {0x53, 0x24}; |
| |
| static struct dsi_cmd_desc r63311_video_display_on_cmds[] = { |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(manufacturer_cmd_access_protect), |
| manufacturer_cmd_access_protect}, |
| {DSI_DI_DCS_SWRITE, 1, 0, sizeof(nop), |
| nop}, |
| {DSI_DI_DCS_SWRITE, 1, 0, sizeof(nop), |
| nop}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(backlight_ctrl), |
| backlight_ctrl}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(seq_test_ctrl), |
| seq_test_ctrl}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(write_display_brightness), |
| write_display_brightness}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(write_ctrl_display), |
| write_ctrl_display}, |
| {DSI_DI_DCS_SWRITE, 1, 0, sizeof(display_on), |
| display_on}, |
| {DSI_DI_DCS_SWRITE, 1, 0, sizeof(exit_sleep), |
| exit_sleep}, |
| }; |
| |
| |
| void panel_1080p_init_config(struct mmp_disp_info *fbi) |
| { |
| dsi_cmd_array_tx(fbi, r63311_video_display_on_cmds, |
| ARRAY_SIZE(r63311_video_display_on_cmds)); |
| } |
| |
| #define OTM1281_SLEEP_OUT_DELAY 100 |
| #define OTM1281_DISP_ON_DELAY 100 |
| |
| static u8 reg_shift_00[] = {0x0, 0x0}; |
| static u8 enable_cmd2[] = {0xff, 0x12, 0x80, 0x1}; |
| static u8 reg_shift_80[] = {0x0, 0x80}; |
| static u8 reg_shift_81[] = {0x0, 0x81}; |
| static u8 reg_shift_82[] = {0x0, 0x82}; |
| static u8 reg_shift_b0[] = {0x0, 0xb0}; |
| /* |
| * increase frame rate to 70 Hz |
| * it should be larger than host output(60Hz) |
| */ |
| static u8 reg_osc_adj[] = {0xc1, 0x9}; |
| static u8 enable_orise[] = {0xff, 0x12, 0x80}; |
| static u8 reg_shift_b8[] = {0x0, 0xb8}; |
| static u8 f5_set[] = {0xf5, 0x0c, 0x12}; |
| static u8 reg_shift_90[] = {0x0, 0x90}; |
| static u8 pwr_ctrl3[] = {0xc5, 0x10, 0x6F, 0x02, 0x88, 0x1D, 0x15, 0x00, |
| 0x04}; |
| static u8 reg_shift_a0[] = {0x0, 0xa0}; |
| static u8 pwr_ctrl4[] = {0xc5, 0x10, 0x6F, 0x02, 0x88, 0x1D, 0x15, 0x00, |
| 0x04}; |
| static u8 pwr_ctrl12[] = {0xc5, 0x20, 0x01, 0x00, 0xb0, 0xb0, 0x00, 0x04, |
| 0x00}; |
| static u8 pwr_vdd[] = {0xd8, 0x58, 0x00, 0x58, 0x00}; |
| static u8 reg_test[] = {0xb0, 0x20}; |
| static u8 set_vcomdc[] = {0xd9, 0x94}; |
| static u8 disable_orise[] = {0xff, 0x00, 0x00}; |
| static u8 disable_cmd2[] = {0xff, 0x00, 0x00, 0x00}; |
| #define SWRESET_DELAY 120 |
| static u8 swreset[] = {0x1}; |
| |
| static struct dsi_cmd_desc otm1281_video_display_on_cmds[] = { |
| {DSI_DI_DCS_SWRITE, 1, SWRESET_DELAY, sizeof(swreset), swreset}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(enable_cmd2), enable_cmd2}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_80), reg_shift_80}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(enable_orise), enable_orise}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_81), reg_shift_81}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(reg_osc_adj), reg_osc_adj}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_82), reg_shift_82}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(reg_osc_adj), reg_osc_adj}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_b8), reg_shift_b8}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(f5_set), f5_set}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_b0), reg_shift_b0}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(reg_test), reg_test}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_90), reg_shift_90}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(pwr_ctrl3), pwr_ctrl3}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_a0), reg_shift_a0}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(pwr_ctrl4), pwr_ctrl4}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_80), reg_shift_80}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(pwr_ctrl12), pwr_ctrl12}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_00), reg_shift_00}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(pwr_vdd), pwr_vdd}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_00), reg_shift_00}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(set_vcomdc), set_vcomdc}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_80), reg_shift_80}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(disable_orise), disable_orise}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(reg_shift_80), reg_shift_80}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(disable_cmd2), disable_cmd2}, |
| |
| {DSI_DI_DCS_SWRITE, 1, OTM1281_SLEEP_OUT_DELAY, sizeof(exit_sleep), |
| exit_sleep}, |
| {DSI_DI_DCS_SWRITE, 1, OTM1281_DISP_ON_DELAY, sizeof(display_on), |
| display_on}, |
| }; |
| |
| void panel_720p_init_config(struct mmp_disp_info *fbi) |
| { |
| dsi_cmd_array_tx(fbi, otm1281_video_display_on_cmds, |
| ARRAY_SIZE(otm1281_video_display_on_cmds)); |
| } |
| |
| static u8 dsi_config[] = {0xe0, 0x43, 0x00, 0x00, 0x00, 0x00}; |
| static u8 dsi_ctr1[] = {0xB5, 0x34, 0x20, 0x40, 0x00, 0x20}; |
| static u8 dsi_ctr2[] = {0xB6, 0x04, 0x74, 0x0f, 0x16, 0x13}; |
| static u8 osc_setting[] = {0xc0, 0x01, 0x08}; |
| static u8 power_ctr1[] = {0xc1, 0x00}; |
| static u8 power_ctr3[] = {0xc3, 0x00, 0x09, 0x10, 0x02, |
| 0x00, 0x66, 0x20, 0x33, 0x00}; |
| static u8 power_ctr4[] = {0xc4, 0x23, 0x24, 0x17, 0x17, 0x59}; |
| static u8 pos_gamma_red[] = {0xd0, 0x21, 0x13, 0x67, 0x37, 0x0c, |
| 0x06, 0x62, 0x23, 0x03}; |
| static u8 neg_gamma_red[] = {0xd1, 0x32, 0x13, 0x66, 0x37, 0x02, |
| 0x06, 0x62, 0x23, 0x03}; |
| static u8 pos_gamma_green[] = {0xd2, 0x41, 0x14, 0x56, 0x37, 0x0c, |
| 0x06, 0x62, 0x23, 0x03}; |
| static u8 neg_gamma_green[] = {0xd3, 0x52, 0x14, 0x55, 0x37, 0x02, |
| 0x06, 0x62, 0x23, 0x03}; |
| static u8 pos_gamma_blue[] = {0xd4, 0x41, 0x14, 0x56, 0x37, 0x0c, |
| 0x06, 0x62, 0x23, 0x03}; |
| static u8 neg_gamma_blue[] = {0xd5, 0x52, 0x14, 0x55, 0x37, 0x02, |
| 0x06, 0x62, 0x23, 0x03}; |
| static u8 set_addr_mode[] = {0x36, 0x08}; |
| static u8 opt2[] = {0xf9, 0x00}; |
| static u8 power_ctr2_1[] = {0xc2, 0x02}; |
| static u8 power_ctr2_2[] = {0xc2, 0x06}; |
| static u8 power_ctr2_3[] = {0xc2, 0x4e}; |
| static char brightness_ctrl[] = {0x51, 0xFF}; |
| static char display_ctrl[] = {0x53, 0x24}; |
| |
| static struct dsi_cmd_desc lg720p_video_display_on_cmds[] = { |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(dsi_config), dsi_config}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(dsi_ctr1), dsi_ctr1}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(dsi_ctr2), dsi_ctr2}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(osc_setting), osc_setting}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(power_ctr1), power_ctr1}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(power_ctr3), power_ctr3}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(power_ctr4), power_ctr4}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(pos_gamma_red), pos_gamma_red}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(neg_gamma_red), neg_gamma_red}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(pos_gamma_green), pos_gamma_green}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(neg_gamma_green), neg_gamma_green}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(pos_gamma_blue), pos_gamma_blue}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(neg_gamma_blue), neg_gamma_blue}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(set_addr_mode), set_addr_mode}, |
| {DSI_DI_GENERIC_LWRITE, 1, 0, sizeof(opt2), opt2}, |
| {DSI_DI_GENERIC_LWRITE, 1, 10, sizeof(power_ctr2_1), power_ctr2_1}, |
| {DSI_DI_GENERIC_LWRITE, 1, 10, sizeof(power_ctr2_2), power_ctr2_2}, |
| {DSI_DI_GENERIC_LWRITE, 1, 80, sizeof(power_ctr2_3), power_ctr2_3}, |
| {DSI_DI_DCS_SWRITE, 1, 10, sizeof(exit_sleep), exit_sleep}, |
| {DSI_DI_GENERIC_LWRITE, 1, 10, sizeof(opt2), opt2}, |
| {DSI_DI_DCS_SWRITE, 1, 0, sizeof(display_on), display_on}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(display_ctrl), (u8 *)display_ctrl}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(brightness_ctrl), |
| (u8 *)brightness_ctrl}, |
| }; |
| |
| void lg_720p_init_config(struct mmp_disp_info *fbi) |
| { |
| dsi_cmd_array_tx(fbi, lg720p_video_display_on_cmds, |
| ARRAY_SIZE(lg720p_video_display_on_cmds)); |
| } |
| |
| static u8 set_password[] = {0xb9, 0xff, 0x83, 0x94}; |
| static u8 set_lane[] = {0xba, 0x13}; |
| static u8 set_power[] = {0xb1, 0x01, 0x00, 0x07, 0x87, 0x01, 0x11, 0x11, 0x2a, 0x30, 0x3f, |
| 0x3f, 0x47, 0x12, 0x01, 0xe6, 0xe2}; |
| static u8 set_cyc[] = {0xb4, 0x80, 0x06, 0x32, 0x10, 0x03, 0x32, 0x15, 0x08, 0x32, 0x10, 0x08, |
| 0x33, 0x04, 0x43, 0x05, 0x37, 0x04, 0x3F, 0x06, 0x61, 0x61, 0x06}; |
| static u8 set_rtl_display_reg[] = {0xb2, 0x00, 0xc8, 0x08, 0x04, 0x00, 0x22}; |
| static u8 set_gip[] = {0xD5, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x01, 0x00, 0xCC, 0x00, 0x00, |
| 0x00, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x01, 0x67, 0x45, 0x23, |
| 0x01, 0x23, 0x88, 0x88, 0x88, 0x88}; |
| static u8 set_tcon[] = {0xC7, 0x00, 0x10, 0x00, 0x10}; |
| static u8 set_init0[] = {0xBF, 0x06, 0x00, 0x10, 0x04}; |
| static u8 set_panel[] = {0xCC, 0x09}; |
| static u8 set_gamma[] = {0xE0, 0x00, 0x04, 0x06, 0x2B, 0x33, 0x3F, 0x11, 0x34, 0x0A, 0x0E, |
| 0x0D, 0x11, 0x13, 0x11, 0x13, 0x10, 0x17, 0x00, 0x04, 0x06, 0x2B, 0x33, 0x3F, 0x11, 0x34, |
| 0x0A, 0x0E, 0x0D, 0x11, 0x13, 0x11, 0x13, 0x10, 0x17, 0x0B, 0x17, 0x07, 0x11, 0x0B, 0x17, |
| 0x07, 0x11}; |
| static u8 set_dgc[] = {0xC1, 0x01, 0x00, 0x07, 0x0E, 0x15, 0x1D, 0x25, 0x2D, 0x34, 0x3C, 0x42, |
| 0x49, 0x51, 0x58, 0x5F, 0x67, 0x6F, 0x77, 0x80, 0x87, 0x8F, 0x98, 0x9F, 0xA7, 0xAF, 0xB7, |
| 0xC1, 0xCB, 0xD3, 0xDD, 0xE6, 0xEF, 0xF6, 0xFF, 0x16, 0x25, 0x7C, 0x62, 0xCA, 0x3A, 0xC2, |
| 0x1F, 0xC0, 0x00, 0x07, 0x0E, 0x15, 0x1D, 0x25, 0x2D, 0x34, 0x3C, 0x42, 0x49, 0x51, 0x58, |
| 0x5F, 0x67, 0x6F, 0x77, 0x80, 0x87, 0x8F, 0x98, 0x9F, 0xA7, 0xAF, 0xB7, 0xC1, 0xCB, 0xD3, |
| 0xDD, 0xE6, 0xEF, 0xF6, 0xFF, 0x16, 0x25, 0x7C, 0x62, 0xCA, 0x3A, 0xC2, 0x1F, 0xC0, 0x00, |
| 0x07, 0x0E, 0x15, 0x1D, 0x25, 0x2D, 0x34, 0x3C, 0x42, 0x49, 0x51, 0x58, 0x5F, 0x67, 0x6F, |
| 0x77, 0x80, 0x87, 0x8F, 0x98, 0x9F, 0xA7, 0xAF, 0xB7, 0xC1, 0xCB, 0xD3, 0xDD, 0xE6, 0xEF, |
| 0xF6, 0xFF, 0x16, 0x25, 0x7C, 0x62, 0xCA, 0x3A, 0xC2, 0x1F, 0xC0}; |
| static u8 set_vcom[] = {0xB6, 0x0C}; |
| static u8 set_init1[] = {0xD4, 0x32}; |
| |
| static struct dsi_cmd_desc hx8394a_display_on_cmds[] = { |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_password), set_password}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_lane), set_lane}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_power), set_power}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_cyc), set_cyc}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_rtl_display_reg), set_rtl_display_reg}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_gip), set_gip}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_tcon), set_tcon}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_init0), set_init0}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_panel), set_panel}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_gamma), set_gamma}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_dgc), set_dgc}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_vcom), set_vcom}, |
| {DSI_DI_DCS_LWRITE, 1, 0, sizeof(set_init1), set_init1}, |
| {DSI_DI_DCS_SWRITE, 1, 200, sizeof(exit_sleep), exit_sleep}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(display_ctrl), (u8 *)display_ctrl}, |
| {DSI_DI_DCS_SWRITE1, 1, 0, sizeof(brightness_ctrl), (u8 *)brightness_ctrl}, |
| {DSI_DI_DCS_SWRITE, 1, 50, sizeof(display_on), display_on}, |
| }; |
| |
| void hx8394a_init_config(struct mmp_disp_info *fbi) |
| { |
| dsi_cmd_array_tx(fbi, hx8394a_display_on_cmds, |
| ARRAY_SIZE(hx8394a_display_on_cmds)); |
| } |