| #ifndef _QSPI_HOST_H |
| #define _QSPI_HOST_H |
| #include <spi_flash_chip.h> |
| |
| #define BIT_0 (1 << 0) |
| #define BIT_1 (1 << 1) |
| #define BIT_2 (1 << 2) |
| #define BIT_3 (1 << 3) |
| #define BIT_4 (1 << 4) |
| #define BIT_5 (1 << 5) |
| #define BIT_6 (1 << 6) |
| #define BIT_7 (1 << 7) |
| #define BIT_8 (1 << 8) |
| #define BIT_9 (1 << 9) |
| #define BIT_10 (1 << 10) |
| #define BIT_11 (1 << 11) |
| #define BIT_12 (1 << 12) |
| #define BIT_13 (1 << 13) |
| #define BIT_14 (1 << 14) |
| #define BIT_15 (1 << 15) |
| #define BIT_16 (1 << 16) |
| #define BIT_17 (1 << 17) |
| #define BIT_18 (1 << 18) |
| #define BIT_19 (1 << 19) |
| #define BIT_20 (1 << 20) |
| #define BIT_21 (1 << 21) |
| #define BIT_22 (1 << 22) |
| #define BIT_23 (1 << 23) |
| #define BIT_24 (1 << 24) |
| #define BIT_25 (1 << 25) |
| #define BIT_26 (1 << 26) |
| #define BIT_27 (1 << 27) |
| #define BIT_28 (1 << 28) |
| #define BIT_29 (1 << 29) |
| #define BIT_30 (1 << 30) |
| #define BIT_31 ((unsigned)1 << 31) |
| |
| /* |
| *--------------------------------------------------------------- |
| * Memory Map |
| *--------------------------------------------------------------- |
| */ |
| #define QSPI0_REG_BASE 0xd420B000 |
| /* AHB RX Data Buffer base addr(QSPI_ARDB0 to QSPI_ARDB31) */ |
| #define QSPI0_ARDB_BASE 0xa0000000 |
| /* AHB base addr */ |
| #define QSPI0_AMBA_BASE 0x80000000 |
| #define QSPI0_FLASH_A1_BASE 0x80000000 |
| #define QSPI0_FLASH_A1_TOP 0x88000000 |
| #define QSPI0_FLASH_A2_BASE 0x88000000 |
| #define QSPI0_FLASH_A2_TOP 0x90000000 |
| #define QSPI0_FLASH_B1_BASE 0x90000000 |
| #define QSPI0_FLASH_B1_TOP 0x98000000 |
| #define QSPI0_FLASH_B2_BASE 0x98000000 |
| #define QSPI0_FLASH_B2_TOP 0xa0000000 |
| |
| /* |
| *--------------------------------------------------------------- |
| * Register definitions |
| *--------------------------------------------------------------- |
| */ |
| #define QSPI_MCR_OFFSET 0x000 |
| #define QSPI_IPCR_OFFSET 0x008 |
| #define QSPI_FLSHCR_OFFSET 0x00C |
| #define QSPI_BUF0CR_OFFSET 0x010 |
| #define QSPI_BUF1CR_OFFSET 0x014 |
| #define QSPI_BUF2CR_OFFSET 0x018 |
| #define QSPI_BUF3CR_OFFSET 0x01C |
| #define QSPI_BFGENCR_OFFSET 0x020 |
| #define QSPI_SOCCR_OFFSET 0x024 |
| #define QSPI_BUF0IND_OFFSET 0x030 |
| #define QSPI_BUF1IND_OFFSET 0x034 |
| #define QSPI_BUF2IND_OFFSET 0x038 |
| #define QSPI_DLACR_OFFSET 0x03C |
| #define QSPI_SFAR_OFFSET 0x100 |
| #define QSPI_SFACR_OFFSET 0x104 |
| #define QSPI_SMPR_OFFSET 0x108 |
| #define QSPI_RBSR_OFFSET 0x10C |
| #define QSPI_RBCT_OFFSET 0x110 |
| #define QSPI_TBSR_OFFSET 0x150 |
| #define QSPI_TBDR_OFFSET 0x154 |
| #define QSPI_TBCT_OFFSET 0x158 |
| #define QSPI_SR_OFFSET 0x15C |
| #define QSPI_FR_OFFSET 0x160 |
| #define QSPI_RSER_OFFSET 0x164 |
| #define QSPI_SPNDST_OFFSET 0x168 |
| #define QSPI_SPTRCLR_OFFSET 0x16C |
| #define QSPI_SFA1AD_OFFSET 0x180 |
| #define QSPI_SFA2AD_OFFSET 0x184 |
| #define QSPI_SFB1AD_OFFSET 0x188 |
| #define QSPI_SFB2AD_OFFSET 0x18C |
| #define QSPI_DLPV_OFFSET 0x190 |
| #define QSPI_RBDR0_OFFSET 0x200 |
| #define QSPI_LUTKEY_OFFSET 0x300 |
| #define QSPI_LCKCR_OFFSET 0x304 |
| #define QSPI_LUT0_OFFSET 0x310 |
| #define QSPI_LUT1_OFFSET 0x314 |
| #define QSPI_LUT2_OFFSET 0x318 |
| #define QSPI_LUT3_OFFSET 0x31C |
| |
| #define QSPI0_MCR (QSPI0_REG_BASE + QSPI_MCR_OFFSET) |
| #define QSPI0_IPCR (QSPI0_REG_BASE + QSPI_IPCR_OFFSET) |
| #define QSPI0_FLSHCR (QSPI0_REG_BASE + QSPI_FLSHCR_OFFSET) |
| #define QSPI0_BUF0CR (QSPI0_REG_BASE + QSPI_BUF0CR_OFFSET) |
| #define QSPI0_BUF1CR (QSPI0_REG_BASE + QSPI_BUF1CR_OFFSET) |
| #define QSPI0_BUF2CR (QSPI0_REG_BASE + QSPI_BUF2CR_OFFSET) |
| #define QSPI0_BUF3CR (QSPI0_REG_BASE + QSPI_BUF3CR_OFFSET) |
| #define QSPI0_BFGENCR (QSPI0_REG_BASE + QSPI_BFGENCR_OFFSET) |
| #define QSPI0_SOCCR (QSPI0_REG_BASE + QSPI_SOCCR_OFFSET) |
| #define QSPI0_BUF0IND (QSPI0_REG_BASE + QSPI_BUF0IND_OFFSET) |
| #define QSPI0_BUF1IND (QSPI0_REG_BASE + QSPI_BUF1IND_OFFSET) |
| #define QSPI0_BUF2IND (QSPI0_REG_BASE + QSPI_BUF2IND_OFFSET) |
| #define QSPI0_DLACR (QSPI0_REG_BASE + QSPI_DLACR_OFFSET) |
| #define QSPI0_SFAR (QSPI0_REG_BASE + QSPI_SFAR_OFFSET) |
| #define QSPI0_SFACR (QSPI0_REG_BASE + QSPI_SFACR_OFFSET) |
| #define QSPI0_SMPR (QSPI0_REG_BASE + QSPI_SMPR_OFFSET) |
| #define QSPI0_RBSR (QSPI0_REG_BASE + QSPI_RBSR_OFFSET) |
| #define QSPI0_RBCT (QSPI0_REG_BASE + QSPI_RBCT_OFFSET) |
| #define QSPI0_TBSR (QSPI0_REG_BASE + QSPI_TBSR_OFFSET) |
| #define QSPI0_TBDR (QSPI0_REG_BASE + QSPI_TBDR_OFFSET) |
| #define QSPI0_TBCT (QSPI0_REG_BASE + QSPI_TBCT_OFFSET) |
| #define QSPI0_SR (QSPI0_REG_BASE + QSPI_SR_OFFSET) |
| #define QSPI0_FR (QSPI0_REG_BASE + QSPI_FR_OFFSET) |
| #define QSPI0_RSER (QSPI0_REG_BASE + QSPI_RSER_OFFSET) |
| #define QSPI0_SPNDST (QSPI0_REG_BASE + QSPI_SPNDST_OFFSET) |
| #define QSPI0_SPTRCLR (QSPI0_REG_BASE + QSPI_SPTRCLR_OFFSET) |
| #define QSPI0_SFA1AD (QSPI0_REG_BASE + QSPI_SFA1AD_OFFSET) |
| #define QSPI0_SFA2AD (QSPI0_REG_BASE + QSPI_SFA2AD_OFFSET) |
| #define QSPI0_SFB1AD (QSPI0_REG_BASE + QSPI_SFB1AD_OFFSET) |
| #define QSPI0_SFB2AD (QSPI0_REG_BASE + QSPI_SFB2AD_OFFSET) |
| #define QSPI0_DLPV (QSPI0_REG_BASE + QSPI_DLPV_OFFSET) |
| #define QSPI0_RBDR0 (QSPI0_REG_BASE + QSPI_RBDR0_OFFSET) |
| #define QSPI0_LUTKEY (QSPI0_REG_BASE + QSPI_LUTKEY_OFFSET) |
| #define QSPI0_LCKCR (QSPI0_REG_BASE + QSPI_LCKCR_OFFSET) |
| #define QSPI0_LUT0 (QSPI0_REG_BASE + QSPI_LUT0_OFFSET) |
| #define QSPI0_LUT1 (QSPI0_REG_BASE + QSPI_LUT1_OFFSET) |
| #define QSPI0_LUT2 (QSPI0_REG_BASE + QSPI_LUT2_OFFSET) |
| #define QSPI0_LUT3 (QSPI0_REG_BASE + QSPI_LUT3_OFFSET) |
| |
| #define QSPI_SFACR_RESV (0x7fff << 17 | 0xfff << 4) |
| |
| #define QSPI_IPCR_SEQID_SHIFT 24 |
| #define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT) |
| #define QSPI_IPCR_RESV (0xf << 28 | 0x7f << 17) |
| |
| #define QSPI_FLSHCR_TDH_SHIFT 16 |
| #define QSPI_FLSHCR_TDH_MASK (0x3 << QSPI_FLSHCR_TDH_SHIFT) |
| #define QSPI_FLSHCR_TDH_HALF_2X (0x1 << QSPI_FLSHCR_TDH_SHIFT) |
| #define QSPI_FLSHCR_TDH_HALF_4X (0x2 << QSPI_FLSHCR_TDH_SHIFT) |
| |
| #define QSPI_MCR_END_CFD_SHIFT 2 |
| #define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT) |
| #define QSPI_MCR_END_CFD_LE (3 << QSPI_MCR_END_CFD_SHIFT) |
| #define QSPI_MCR_DQS_EN BIT_6 |
| #define QSPI_MCR_DDR_EN BIT_7 |
| #define QSPI_MCR_CLR_RXF BIT_10 |
| #define QSPI_MCR_CLR_TXF BIT_11 |
| #define QSPI_MCR_MDIS BIT_14 |
| #define QSPI_MCR_DQS_LP_EN BIT_25 |
| #define QSPI_MCR_DQS_INV_EN BIT_26 |
| #define QSPI_MCR_ISDX_SHIFT 16 |
| #define QSPI_MCR_ISDX_MASK (0xf << QSPI_MCR_ISDX_SHIFT) |
| #define QSPI_MCR_SWRSTHD BIT_1 |
| #define QSPI_MCR_SWRSTSD BIT_0 |
| #define QSPI_MCR_RESV (0xf << 20 | 0x3 << 12 | 0x3 << 8 | 0x1 << 4) |
| |
| #define QSPI_SMPR_HSENA BIT_0 |
| #define QSPI_SMPR_FSPHS BIT_5 |
| #define QSPI_SMPR_FSDLY BIT_6 |
| #define QSPI_SMPR_DDRSMP_SHIFT 16 |
| #define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT) |
| |
| #define QSPI_BUFXCR_INVALID_MSTRID 0xe |
| #define QSPI_BUF3CR_ALLMST BIT_31 |
| #define QSPI_BUF3CR_ADATSZ_SHIFT 8 |
| #define QSPI_BUF3CR_ADATSZ_MASK (0xFF << QSPI_BUF3CR_ADATSZ_SHIFT) |
| |
| #define QSPI_BFGENCR_SEQID_SHIFT 12 |
| #define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT) |
| #define QSPI_BFGENCR_PAR_EN BIT_16 |
| |
| #define QSPI_SOCCR_DLINE_EN BIT_8 |
| #define QSPI_DLACR_DLINE_CODE_SHIFT 0 |
| #define QSPI_DLACR_DLINE_CODE_MASK (0xFF << QSPI_DLACR_DLINE_CODE_SHIFT) |
| #define QSPI_DLACR_DLINE_STEP_SHIFT 8 |
| #define QSPI_DLACR_DLINE_STEP_MASK (0xFF << QSPI_DLACR_DLINE_STEP_SHIFT) |
| |
| #define QSPI_RBSR_RDBFL_SHIFT 8 |
| #define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT) |
| |
| #define QSPI_RBCT_RXBRD BIT_8 |
| #define QSPI_RBCT_WMRK_SHITT 0 |
| #define QSPI_RBCT_WMRK_MASK (0x1f << QSPI_RBCT_WMRK_SHITT) |
| #define QSPI_RBCT_RESV (0x7fffff << 9 | 0x7 << 5) |
| |
| #define QSPI_TBCT_WMRK_SHITT 0 |
| #define QSPI_TBCT_WMRK_MASK (0x1f << QSPI_TBCT_WMRK_SHITT) |
| #define QSPI_TBCT_RESV (~0x1f) |
| |
| #define QSPI_SR_TXFULL BIT_27 |
| #define QSPI_SR_TXDMA BIT_26 |
| #define QSPI_SR_TXWA BIT_25 |
| #define QSPI_SR_TXEDA BIT_24 |
| #define QSPI_SR_RXDMA BIT_23 |
| #define QSPI_SR_RXFULL BIT_19 |
| #define QSPI_SR_RXWE BIT_16 |
| #define QSPI_SR_AHB_ACC BIT_2 |
| #define QSPI_SR_IP_ACC BIT_1 |
| #define QSPI_SR_BUSY BIT_0 |
| |
| #define QSPI_FR_DLPFF BIT_31 |
| #define QSPI_FR_TBFF BIT_27 |
| #define QSPI_FR_TBUF BIT_26 |
| #define QSPI_FR_ILLINE BIT_23 |
| #define QSPI_FR_RBOF BIT_17 |
| #define QSPI_FR_RBDF BIT_16 |
| #define QSPI_FR_ABSEF BIT_15 |
| #define QSPI_FR_AITEF BIT_14 |
| #define QSPI_FR_AIBSEF BIT_13 |
| #define QSPI_FR_ABOF BIT_12 |
| #define QSPI_FR_IUEF BIT_11 |
| #define QSPI_FR_IPAEF BIT_7 |
| #define QSPI_FR_IPIEF BIT_6 |
| #define QSPI_FR_IPGEF BIT_4 |
| #define QSPI_FR_TFF BIT_0 |
| |
| #define QSPI_RSER_DLPFIE BIT_31 |
| #define QSPI_RSER_TBFIE BIT_27 |
| #define QSPI_RSER_TBUIE BIT_26 |
| #define QSPI_RSER_TBFDE BIT_25 |
| #define QSPI_RSER_ILLINIE BIT_23 |
| #define QSPI_RSER_RBDDE BIT_21 |
| #define QSPI_RSER_RBOIE BIT_17 |
| #define QSPI_RSER_RBDIE BIT_16 |
| #define QSPI_RSER_ABSEIE BIT_15 |
| #define QSPI_RSER_AITIE BIT_14 |
| #define QSPI_RSER_AIBSIE BIT_13 |
| #define QSPI_RSER_ABOIE BIT_12 |
| #define QSPI_RSER_IUEIE BIT_11 |
| #define QSPI_RSER_IPIEIE BIT_6 |
| #define QSPI_RSER_IPGEIE BIT_4 |
| #define QSPI_RSER_TFIE BIT_0 |
| #define QSPI_RSER_RESV (0x7 << 28 | 0x1 << 24 | 0x1 << 22 | \ |
| 0x7 << 18 | 0x7 << 8 | 0x1 << 5 | \ |
| 0x7 << 1) |
| |
| #define QSPI_SPTRCLR_IPPTRC BIT_8 |
| #define QSPI_SPTRCLR_RESV (0x7fffff << 9 | 0x7f << 1) |
| |
| #define QSPI_LCKCR_LOCK BIT_0 |
| #define QSPI_LCKCR_UNLOCK BIT_1 |
| |
| #define LUT_KEY_VALUE 0x5af05af0 |
| |
| /* |
| *--------------------------------------------------------------- |
| * Enumeration & Structure |
| *--------------------------------------------------------------- |
| */ |
| enum QSPI_INST_E { |
| QSPI_INSTR_STOP = 0x0, |
| QSPI_INSTR_CMD = 0x1, |
| QSPI_INSTR_ADDR = 0x2, |
| QSPI_INSTR_DUMMY = 0x3, |
| QSPI_INSTR_MODE = 0x4, |
| QSPI_INSTR_MODE2 = 0x5, |
| QSPI_INSTR_MODE4 = 0x6, |
| QSPI_INSTR_READ = 0x7, |
| QSPI_INSTR_WRITE = 0x8, |
| QSPI_INSTR_JMP_ON_CS = 0x9, |
| QSPI_INSTR_ADDR_DDR = 0xA, |
| QSPI_INSTR_MODE_DDR = 0xB, |
| QSPI_INSTR_MODE2_DDR = 0xC, |
| QSPI_INSTR_MODE4_DDR = 0xD, |
| QSPI_INSTR_READ_DDR = 0xE, |
| QSPI_INSTR_WRITE_DDR = 0xF, |
| QSPI_INSTR_DATA_LEARN = 0x10, |
| QSPI_INSTR_CMD_DDR = 0x11, |
| }; |
| |
| enum QSPI_PAD_E { |
| QSPI_PAD_1X = 0x0, |
| QSPI_PAD_2X = 0x1, |
| QSPI_PAD_4X = 0x2, |
| QSPI_PAD_RSVD = 0x3 |
| }; |
| |
| #define QSPI_RX_BUFF_MAX 32 |
| #define QSPI_TX_BUFF_MAX 32 |
| #define QSPI_TX_BUFF_POP_MIN 16 |
| #define QSPI_AHB_BUFF_MAX_SIZE (256*3) |
| |
| #define QSPI_DMA_RX_CHANNEL 27 |
| #ifdef CONFIG_ASR1901 |
| #define QSPI_DMA_TX_CHANNEL 15 |
| #define QSPI_DMA_TX_DRCMR 45 |
| #else |
| #define QSPI_DMA_TX_CHANNEL 28 |
| #define QSPI_DMA_TX_DRCMR 99 |
| #endif |
| #define ENABLE_QSPI_INT |
| #define ENABLE_QSPI_DMA |
| |
| struct spi_flash_cmd; |
| |
| enum { |
| QSPI_LUT_NOTSET = -1, |
| QSPI_LUT_SEQID0 = 0, |
| QSPI_LUT_SEQID1, |
| QSPI_LUT_SEQID2, |
| QSPI_LUT_SEQID3, |
| QSPI_LUT_SEQID4, |
| QSPI_LUT_SEQID5, |
| QSPI_LUT_SEQID6, |
| QSPI_LUT_SEQID7, |
| QSPI_LUT_SEQID8, |
| QSPI_LUT_SEQID9, |
| QSPI_LUT_SEQID10, |
| QSPI_LUT_SEQID11, |
| QSPI_LUT_SEQID12, |
| QSPI_LUT_SEQID13, |
| QSPI_LUT_SEQID14, |
| QSPI_LUT_SEQID15, |
| }; |
| |
| enum { |
| QSPI_NORMAL_MODE = 0, |
| QSPI_DISABLE_MODE, |
| QSPI_STOP_MODE, |
| }; |
| |
| enum { |
| QSPI_FUNC_CLK_26MHZ = 0, |
| QSPI_FUNC_CLK_52MHZ, |
| QSPI_FUNC_CLK_78MHZ, |
| QSPI_FUNC_CLK_104MHZ, |
| QSPI_FUNC_CLK_156MHZ, |
| QSPI_FUNC_CLK_208MHZ, |
| QSPI_FUNC_CLK_312MHZ, |
| QSPI_FUNC_CLK_416MHZ, |
| }; |
| |
| enum { |
| QSPI_CS_A1 = 0, |
| QSPI_CS_A2, |
| QSPI_CS_B1, |
| QSPI_CS_B2, |
| QSPI_CS_MAX, |
| }; |
| |
| struct qspi_host |
| { |
| struct spi_flash_cmd *cmd; |
| int bytes_left; |
| volatile int complete; |
| int wmrk; |
| int cs_addr[QSPI_CS_MAX]; |
| int use_intr; |
| int en_tx_dma; |
| int use_dma; |
| int use_xip; |
| int bus_clk; |
| int lut_map; |
| int has_dtr; |
| int support_dqs; |
| }; |
| |
| struct qspi_host * qspi_host_init(int cs, int mhz, int use_xip); |
| |
| #endif |