| #ifndef __PPSET_H |
| #define __PPSET_H |
| #include <linux/types.h> |
| |
| #define MV_OK (0x00) /* Operation succeeded */ |
| #define MV_FAIL (0x01) /* Operation failed */ |
| |
| typedef enum op_tag{ |
| OP0 = 0, |
| OP1, |
| OP2, |
| OP3, |
| OP4, |
| OP5, |
| OP6, |
| OP7, |
| OP8, |
| OP_UNCHANGE, |
| OP_INVALID |
| } op_index; |
| |
| typedef enum DVC_type { |
| DVC00 = 0, |
| DVC01, |
| DVC10, |
| DVC11, |
| } dvc_index; |
| |
| typedef struct core_freq_tag { |
| const char *label; |
| uint32_t pclk; |
| uint32_t memclk; |
| uint32_t busclk; |
| uint32_t pll2; |
| uint32_t pll2p; |
| uint32_t dvc; |
| uint64_t dvcs; /* all possible dvc among profiles. */ |
| uint64_t dvcsa; /* for A0 */ |
| } core_freq; |
| |
| typedef struct dfc_setting_tag { |
| uint32_t pll2ref; |
| uint32_t pll2fb; |
| uint32_t apb_spare2; /* for PLL2 */ |
| uint32_t pmum_fccr; |
| uint32_t pmua_cc_ap_cp; |
| uint32_t mc_reg_table; /* index and enable */ |
| } dfc_setting; |
| |
| typedef struct ddr_freq_tag { |
| const char *label; |
| uint32_t dclk; |
| uint32_t pll2; |
| uint32_t pll2p; |
| uint32_t dfl_setting; |
| uint32_t dvc; |
| uint64_t dvcs; |
| uint64_t dvcsa; /* for A0 */ |
| } ddr_freq; |
| |
| typedef struct axi_freq_tag { |
| const char *label; |
| uint32_t aclk; |
| uint32_t dvc; |
| uint64_t dvcs; |
| uint64_t dvcsa; /* for A0 */ |
| } axi_freq; |
| |
| typedef struct axi_setting_tag { |
| uint32_t pmum_fccr; |
| uint32_t pmua_cc_ap_cp; |
| } axi_setting; |
| |
| /* Coresight/Debug */ |
| typedef struct cs_freq_tag { |
| const char *label; |
| uint32_t atclk; /* is synced to trace_clk, share one FC_request */ |
| uint32_t dbg_clk; /* use another FC frequest */ |
| uint32_t trace_clk; |
| uint32_t dvc; |
| uint64_t dvcs; |
| } cs_freq; |
| |
| typedef struct cs_setting_tag { |
| uint32_t trace_config; |
| } cs_setting; |
| |
| typedef struct mck5_table_entry_tag{ |
| /* Reg Table Data Reg0, [31:0] regdata */ |
| uint32_t reg_data; |
| /* Reg Table Data Reg1,[17] end, [16] pause, [11:0] regoffset */ |
| uint32_t offset_pause_end; |
| /* Reg Table Control Reg, [7:5] regtable sel, [4:0] SRAM table addr */ |
| uint32_t table_sel_addr; |
| } mck5_talbe_entry; |
| |
| /* FIXME: must remove the table after has fuse info !!! */ |
| struct svtrng { |
| unsigned int min; |
| unsigned int max; |
| unsigned int profile; |
| }; |
| |
| #define NA 0 /* stand for not defined since it's not used */ |
| extern op_index c_aop, c_csop; |
| extern op_index c_cop, c_axiop; |
| extern core_freq *ca7_value; |
| extern cs_freq cs_value[]; |
| extern core_freq cr5_value[]; |
| extern axi_freq aclk_value[]; |
| |
| /* |
| *Note: since AP wants to know the DDR OP and it's controlled by CP in Nezha2. |
| *Let CP use the CIU->SW_SCRATCH register to save the current DDR OP. |
| *and AP read the register to get the OP |
| */ |
| |
| void pp_init(void); |
| void dump_pmu_reg(void); |
| uint32_t adfc(uint32_t top); |
| uint32_t ddfc(uint32_t top); |
| uint32_t cdfc(uint32_t top); |
| uint32_t axidfc(uint32_t top); |
| void csdfc(uint32_t top); |
| uint32_t pxa182x_fc_init(int ddr_mode, int max_corefreq_mode); |
| |
| void dump_app_fcreg(void); |
| void dump_app_pmureg(void); |
| void dump_main_pmureg(void); |
| void dump_pll_ctrlreg(void); |
| |
| typedef struct |
| { |
| volatile uint32_t STATUS; |
| volatile uint32_t CONFIG; |
| volatile uint32_t INIT_KEY_VALUE[8]; |
| volatile uint32_t INPUT_DATA_ENC_DEC[4]; |
| union{ |
| volatile uint32_t GUE_1ST_OFF_CODE_OCB_MODE[4]; |
| volatile uint32_t CBC_INIT_VAL_REG[4]; |
| volatile uint32_t FUSE_PROG_VAL1[4]; |
| }; |
| union{ |
| volatile uint32_t GUE_2ND_OFF_CODE_OCB_MODE[4]; |
| volatile uint32_t FUSE_PROG_VAL2[4]; |
| }; |
| volatile uint32_t OUT_DATA_AFTER_ENC_DEC[4]; |
| volatile uint32_t SRAM_SPACE_ROUND_KEY_TABLE[64]; |
| volatile uint32_t ROM_SPACE_SBOX_TABLE[64]; |
| volatile uint32_t ROM_SPACE_INV_SBOX_TABLE[64]; |
| volatile uint32_t OTP_DATA1; |
| volatile uint32_t OTP_DATA2; |
| volatile uint32_t OTP_DATA3; |
| volatile uint32_t OTP_DATA4; |
| volatile uint32_t RESERVED0[(0x404-0x374)/4-1]; |
| volatile uint32_t FUSE_VAL_APCFG1; |
| volatile uint32_t FUSE_VAL_APCFG2; |
| volatile uint32_t FUSE_VAL_APCFG3; |
| volatile uint32_t FUSE_MANU_PARA_0; |
| volatile uint32_t FUSE_MANU_PARA_1; |
| volatile uint32_t FUSE_MANU_PARA_2; |
| volatile uint32_t AP_CP_MP_ECC; |
| volatile uint32_t BLOCK0_RESERVED_1; |
| volatile uint32_t FUSE_VAL_ROOT_KEY1; |
| volatile uint32_t FUSE_VAL_ROOT_KEY2; |
| volatile uint32_t FUSE_VAL_ROOT_KEY3; |
| volatile uint32_t FUSE_VAL_ROOT_KEY4; |
| volatile uint32_t FUSE_VAL_ROOT_KEY5; |
| volatile uint32_t FUSE_VAL_ROOT_KEY6; |
| volatile uint32_t FUSE_VAL_ROOT_KEY7; |
| volatile uint32_t FUSE_VAL_ROOT_KEY8; |
| volatile uint32_t FUSE_VAL_OEM_HASH_KEY[8]; |
| volatile uint32_t FUSE_VAL_OEM_JTAG_HASH[8]; |
| volatile uint32_t FUSE_STATUS; |
| volatile uint32_t HW_RANDOM_NUM_GEN; |
| volatile uint32_t FUSE_VAL_OEM_UID_H; |
| volatile uint32_t BLOCK7_RESERVED_0; |
| volatile uint32_t BLOCK7_RESERVED_1; |
| volatile uint32_t BLOCK7_RESERVED_2; |
| volatile uint32_t BLOCK7_RESERVED_3; |
| volatile uint32_t BLOCK7_RESERVED_4; |
| volatile uint32_t BLOCK7_RESERVED_5; |
| volatile uint32_t FUSE_VAL_OEM_UID_L; |
| volatile uint32_t RESERVED1[(0x4C0-0x4A8)/4-1]; |
| volatile uint32_t ECC_CAL; |
| volatile uint32_t ECC_STATUS; |
| volatile uint32_t FUSE_VAL_APCP_ECC; |
| } GEU_TypeDef; |
| |
| #define GEU_BASE 0xD4201000 |
| |
| #define GEU (( GEU_TypeDef *) GEU_BASE ) |
| typedef struct |
| { |
| volatile uint32_t CC_CP; /* 0x0 */ |
| volatile uint32_t CC_AP; /* 0x4 */ |
| volatile uint32_t DM_CC_CP; /* 0x8 */ |
| volatile uint32_t DM_CC_AP; /* 0xC */ |
| volatile uint32_t FC_TIMER; /* 0x10 */ |
| volatile uint32_t CP_IDLE_CFG; /* 0x14 */ |
| volatile uint32_t AP_IDLE_CFG; /* 0x18 */ |
| volatile uint32_t SQU_CLK_GATE_CTRL; /* 0x1C */ |
| volatile uint32_t IRE_CLK_GATE_CTRL; /* 0x20 */ |
| volatile uint32_t RESERVED0; /* 0x24 */ |
| volatile uint32_t CCIC_CLK_GATE_CTRL; /* 0x28 */ |
| volatile uint32_t FBRC0_CLK_GATE_CTRL; /* 0x2C */ |
| volatile uint32_t FBRC1_CLK_GATE_CTRL; /* 0x30 */ |
| volatile uint32_t USB_CLK_GATE_CTRL; /* 0x34 */ |
| volatile uint32_t RESERVED1[2]; /* 0x38-0x3C */ |
| volatile uint32_t PMU_CLK_GATE_CTRL; /* 0x40 */ |
| volatile uint32_t LTE_DMA_AXI2MC0_CLK_RES_CTRL; /* 0x44 */ |
| volatile uint32_t AXI_CLK_RES_CTRL; /* 0x48 */ |
| volatile uint32_t HSI_CLK_RES_CTRL; /* 0x4C */ |
| volatile uint32_t CCIC_CLK_RES_CTRL; /* 0x50 */ |
| volatile uint32_t SDH0_CLK_RES_CTRL; /* 0x54 */ |
| volatile uint32_t SDH1_CLK_RES_CTRL; /* 0x58 */ |
| volatile uint32_t USB_CLK_RES_CTRL; /* 0x5C */ |
| volatile uint32_t NF_CLK_RES_CTRL; /* 0x60 */ |
| volatile uint32_t DMA_CLK_RES_CTRL; /* 0x64 */ |
| volatile uint32_t AES_CLK_RES_CTRL; /* 0x68 */ |
| volatile uint32_t MCB_CLK_RES_CTRL; /* 0X6C */ |
| volatile uint32_t CP_IMR; /* 0x70 */ |
| volatile uint32_t CP_IRWC; /* 0x74 */ |
| volatile uint32_t CP_ISR; /* 0x78 */ |
| volatile uint32_t SD_ROT_WAKE_CLR; /* 0X7C */ |
| volatile uint32_t PMU_FBRC_CLK; /* 0x80 */ |
| volatile uint32_t PWR_STBL_TIMER; /* 0X84 */ |
| volatile uint32_t DEBUG_REG; /* 0x88 */ |
| volatile uint32_t SRAM_PWR_DWN; /* 0x8C */ |
| volatile uint32_t CORE_STATUS; /* 0x90 */ |
| volatile uint32_t RES_FRM_SLP_CLR; /* 0x94 */ |
| volatile uint32_t AP_IMR; /* 0x98 */ |
| volatile uint32_t AP_IRWC; /* 0x9C */ |
| volatile uint32_t AP_ISR; /* 0xA0 */ |
| volatile uint32_t DX8_CLK_RES_CTRL; /* 0XA4 */ |
| volatile uint32_t PMU_VPRO_PWRDWN; /* 0xA8 */ |
| volatile uint32_t DTC_CLK_RES_CTRL; /* 0xAC */ |
| volatile uint32_t MC_HW_SLP_TYPE; /* 0XB0 */ |
| volatile uint32_t MC_SLP_REQ_AP; /* 0XB4 */ |
| volatile uint32_t MC_SLP_REQ_CP; /* 0xb8 */ |
| volatile uint32_t MC_SLP_REQ_MSA; /* 0xbc */ |
| volatile uint32_t MC_MC_SLP_TYPE; /* 0XC0 */ |
| volatile uint32_t PLL_SEL_STATUS; /* 0xc4 */ |
| volatile uint32_t SYNC_MODE_BYPASS; /* 0xC8 */ |
| volatile uint32_t GC_CLK_RES_CTRL; /* 0xCC */ |
| volatile uint32_t GC_PWRDWN; /* 0xd0 */ |
| volatile uint32_t SMC_CLK_RES_CTRL; /* 0xD4 */ |
| volatile uint32_t PWR_CTRL_REG; /* 0xD8 */ |
| volatile uint32_t PWR_BLK_TMR_REG; /* 0xDC */ |
| volatile uint32_t SDH2_CLK_RES_CTRL; /* 0xE0 */ |
| volatile uint32_t SDH_NOM_DENOM_CTRL; /* 0xE4 */ |
| volatile uint32_t RESERVED2[2]; /* 0xE8-0XEC */ |
| volatile uint32_t PWR_STATUS_REG; /* 0xF0 */ |
| volatile uint32_t MCK4_CTRL; /* 0xF4 */ |
| volatile uint32_t RESERVED3[(0x100-0xF4)/4-1]; |
| volatile uint32_t CC2_AP; /* 0x100 */ |
| volatile uint32_t CC2_CP; /* 0x104 */ |
| volatile uint32_t TRACE_CONFIG; /* 0x108 */ |
| volatile uint32_t RESERVED4[(0x120-0x108)/4-1]; |
| volatile uint32_t CA7MP_IDLE_CFG0; /* 0x120 */ |
| volatile uint32_t CA7_CORE0_IDLE_CFG; /* 0x124 */ |
| volatile uint32_t RESERVED5[(0x140-0x124)/4-1]; |
| volatile uint32_t DVC_DEBUG; /* 0x140 */ |
| volatile uint32_t RESERVED6[(0x170-0x140)/4-1]; |
| volatile uint32_t CA7_PWR_MISC; /* 0x170 */ |
| } PMUA_TypeDef; |
| |
| #define PMUA_BASE 0xD4282800 |
| #define PMUA (( PMUA_TypeDef *) PMUA_BASE ) |
| |
| typedef struct |
| { |
| volatile uint32_t CPCR; |
| volatile uint32_t CPSR; |
| volatile uint32_t FCCR; |
| volatile uint32_t POCR; |
| volatile uint32_t POSR; |
| volatile uint32_t SUCCR; |
| volatile uint32_t VRCR; |
| volatile uint32_t RESERVED0; |
| volatile uint32_t CPRR; |
| volatile uint32_t CCGR; |
| volatile uint32_t CRSR; |
| volatile uint32_t XDCR; |
| volatile uint32_t GPCR; |
| volatile uint32_t PLL2CR; |
| volatile uint32_t SCCR; |
| volatile uint32_t MCCR; |
| volatile uint32_t ISCCRX[2]; |
| volatile uint32_t CWUCRS; |
| volatile uint32_t CWUCRM; //0X004C */ |
| volatile uint32_t RESERVED1[(0x100-0x4c)/4-1]; |
| volatile uint32_t DSOC; //0X100 */ |
| volatile uint32_t RESERVED2[(0x200-0x100)/4-1]; |
| volatile uint32_t WDTPCR; //0X200 */ |
| volatile uint32_t RESERVED3[(0x400-0x200)/4-1]; |
| volatile uint32_t CMPRX[5]; //0X400 */ |
| volatile uint32_t RESERVED5[(0x1000-0x410)/4-1]; |
| volatile uint32_t APCR; //0X1000 */ |
| volatile uint32_t APSR; //0X1004 */ |
| volatile uint32_t RESERVED6[(0x1020-0x1004)/4-1]; |
| volatile uint32_t APRR; //0x1020 */ |
| volatile uint32_t ACGR; |
| volatile uint32_t ARSR; //0X1028 */ |
| volatile uint32_t RESERVED7[(0x20)/4-1]; |
| volatile uint32_t AWUCRS; //0X1048 */ |
| volatile uint32_t AWUCRM; |
| } PMUM_TypeDef; |
| |
| |
| #define PMUM_BASE 0xD4050000 |
| #define PMUM ((PMUM_TypeDef *) PMUM_BASE ) |
| |
| typedef struct |
| { |
| volatile uint32_t CHIP_ID; |
| volatile uint32_t SEAGULL_CPU_CONF; |
| volatile uint32_t MOHAWK_CPU_CONF; |
| volatile uint32_t SEAGULL_CPU_SRAM_SPD; |
| volatile uint32_t MOHAWK_CPU_SRAM_SPD; |
| volatile uint32_t SEAGULL_CPU_L2C_SRAM_SPD; |
| volatile uint32_t MOHAWK_CPU_L2C_SRAM_SPD; |
| volatile uint32_t RESERVED0[1]; |
| volatile uint32_t SYS_BOOT_CNTRL; |
| volatile uint32_t SW_BRANCH_ADDR; |
| volatile uint32_t PERF_COUNT0_CNTRL_A; |
| volatile uint32_t PERF_COUNT1_CNTRL_A; |
| volatile uint32_t PERF_COUNT2_CNTRL; |
| volatile uint32_t PERF_COUNT0; |
| volatile uint32_t PERF_COUNT1; |
| volatile uint32_t PERF_COUNT2; |
| volatile uint32_t MC_CONF; |
| volatile uint32_t RESERVED1[1]; |
| volatile uint32_t U3_CONF; |
| volatile uint32_t RESERVED2[1]; |
| volatile uint32_t AXI2MC0_CTRL; |
| volatile uint32_t RESERVED3[2]; |
| volatile uint32_t AXI2MC2_CTRL; |
| volatile uint32_t RESERVED4[5]; |
| volatile uint32_t PERF_COUNT3; |
| volatile uint32_t PERF_COUNT3_CNTRL_A; |
| volatile uint32_t PERF_COUNT0_CNTRL_B; |
| volatile uint32_t PERF_COUNT1_CNTRL_B; |
| volatile uint32_t PERF_COUNT2_CNTRL_B; |
| volatile uint32_t PERF_COUNT3_CNTRL_B; |
| volatile uint32_t RESERVED5[1]; |
| volatile uint32_t DDR_PHY_TST_CONFIG; |
| volatile uint32_t DDR_PHY_TST_SEED; |
| volatile uint32_t DDR_PHY_TST_SIGNATURE; |
| volatile uint32_t DDR_PHY_TST_STATUS; |
| volatile uint32_t CR5_CONF; |
| volatile uint32_t CR5_SRAM_CONF; |
| volatile uint32_t CR5_PPX_CONF; |
| volatile uint32_t CR5_PPV_CONF; |
| volatile uint32_t SEAGULL_L2C_ADDR_FILTER_CONF; |
| volatile uint32_t SEAGULL_L2C_CONF; |
| volatile uint32_t SEAGULL_L2C_SRAM_CONF; |
| volatile uint32_t RESERVED6[1]; |
| volatile uint32_t CA7_SCU_CONF; |
| volatile uint32_t CA7_CORESIGHT_ROM_ADDR; |
| volatile uint32_t CA7_CORESIGHT_SELF_ADDR; |
| volatile uint32_t RESERVED7[1]; |
| volatile uint32_t CA7_CPU_SRAM_CONF_0; |
| volatile uint32_t CA7_CPU_SRAM_CONF_1; |
| volatile uint32_t CA7_WARM_RESET_VECTOR; |
| volatile uint32_t RESERVED8[1]; |
| volatile uint32_t CA7_CORE_CONF; |
| volatile uint32_t RESERVED9[1]; |
| volatile uint32_t SW_SCRATCH; |
| } CIU_TypeDef; |
| #define CIU_BASE 0xD4282C00 |
| #define CIU ((CIU_TypeDef*)CIU_BASE) |
| |
| typedef struct { |
| volatile uint32_t APB_SPARE0; |
| volatile uint32_t RESERVED0[2]; |
| volatile uint32_t SENSOR_V18; |
| volatile uint32_t RECERVED1[(0x100-0x0C)/4-1]; |
| volatile uint32_t PLL1_SW_CTRL; /* 0x100 */ |
| volatile uint32_t PLL2_SW_CTRL; |
| volatile uint32_t PLL3_SW_CTRL; |
| volatile uint32_t PLL4_SW_CTRL; |
| volatile uint32_t PLL5_SW_CTRL; /* helanlte */ |
| } APBSPARE_TypeDef; |
| #define APBSPARE_BASE 0xD4090000 |
| #define APBSPARE (( APBSPARE_TypeDef *) APBSPARE_BASE ) |
| |
| #define PMU_DVC_BASE (0xd4050000) |
| #define PMU_DVC_DVCR (PMU_DVC_BASE + 0x2000) |
| #define PMU_DVC_AP (PMU_DVC_BASE + 0x2020) |
| #define PMU_DVC_CP (PMU_DVC_BASE + 0x2024) |
| #define PMU_DVC_DP (PMU_DVC_BASE + 0x2028) |
| #define PMU_DVC_APSUB (PMU_DVC_BASE + 0x202c) |
| #define PMU_DVC_APCHIP (PMU_DVC_BASE + 0x2030) |
| #define PMU_DVC_STATUS (PMU_DVC_BASE + 0x2040) |
| #define PMU_DVC_IMR (PMU_DVC_BASE + 0x2050) |
| #define PMU_DVC_ISR (PMU_DVC_BASE + 0x2054) |
| #define PMU_DVC_DEBUG (PMU_DVC_BASE + 0x2058) |
| #define PMU_DVC_EXRA_STR (PMU_DVC_BASE + 0x205c) |
| #define PMU_DVC_VL01STR_A0 (PMU_DVC_BASE + 0x2060) /* A0 start level */ |
| #define PMU_DVC_VL12STR_A0 (PMU_DVC_BASE + 0x2064) |
| #define PMU_DVC_VL23STR_A0 (PMU_DVC_BASE + 0x2068) |
| |
| #define PMUA_DFC_BASE (0xd4282800) |
| #define PMUA_DFC_AP (PMUA_DFC_BASE + 0x180) |
| #define PMUA_DFC_STATUS (PMUA_DFC_BASE + 0x188) |
| #define PMUA_DFC_LEVEL0 (PMUA_DFC_BASE + 0x190) |
| #define PMUA_DFC_LEVEL1 (PMUA_DFC_BASE + 0x194) |
| #define PMUA_DFC_LEVEL2 (PMUA_DFC_BASE + 0x198) |
| #define PMUA_DFC_LEVEL3 (PMUA_DFC_BASE + 0x19C) |
| #define PMUA_DFC_LEVEL4 (PMUA_DFC_BASE + 0x1A0) |
| #define PMUA_DFC_LEVEL5 (PMUA_DFC_BASE + 0x1A4) |
| #define PMUA_DFC_LEVEL6 (PMUA_DFC_BASE + 0x1A8) |
| #define PMUA_AP_ISR (PMUA_DFC_BASE + 0x0A0) |
| |
| #endif |
| |