| From 2c241c25b76d105f798881e1a3c6e3c09c3b27ff Mon Sep 17 00:00:00 2001 |
| From: Maxime Ripard <maxime@cerno.tech> |
| Date: Mon, 13 Jan 2020 13:40:37 +0100 |
| Subject: [PATCH] drm/vc4: crtc: Add function to compute FIFO level |
| bits |
| |
| The longer FIFOs in vc5 pixelvalves means that the FIFO full level |
| doesn't fit in the original register field and that we also have a |
| secondary field. In order to prepare for this, let's move the registers |
| fill part to a helper function. |
| |
| Signed-off-by: Maxime Ripard <maxime@cerno.tech> |
| --- |
| drivers/gpu/drm/vc4/vc4_crtc.c | 11 +++++++++-- |
| 1 file changed, 9 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/gpu/drm/vc4/vc4_crtc.c |
| +++ b/drivers/gpu/drm/vc4/vc4_crtc.c |
| @@ -277,6 +277,14 @@ static u32 vc4_get_fifo_full_level(struc |
| } |
| } |
| |
| +static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc, |
| + u32 format) |
| +{ |
| + u32 level = vc4_get_fifo_full_level(vc4_crtc, format); |
| + return VC4_SET_FIELD(level & 0x3f, |
| + PV_CONTROL_FIFO_LEVEL); |
| +} |
| + |
| /* |
| * Returns the encoder attached to the CRTC. |
| * |
| @@ -377,9 +385,8 @@ static void vc4_crtc_config_pv(struct dr |
| CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); |
| |
| CRTC_WRITE(PV_CONTROL, |
| + vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) | |
| VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | |
| - VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format), |
| - PV_CONTROL_FIFO_LEVEL) | |
| VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | |
| PV_CONTROL_CLR_AT_START | |
| PV_CONTROL_TRIGGER_UNDERFLOW | |