| From 8df093fe2ae1717389df0dcdc620c02cc35abb21 Mon Sep 17 00:00:00 2001 |
| From: Ansuel Smith <ansuelsmth@gmail.com> |
| Date: Mon, 15 Jun 2020 23:06:05 +0200 |
| Subject: PCI: qcom: Add ipq8064 rev2 variant |
| |
| Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit |
| different offset based on the revision. |
| |
| Link: https://lore.kernel.org/r/20200615210608.21469-10-ansuelsmth@gmail.com |
| Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> |
| Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
| Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> |
| --- |
| drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- |
| 1 file changed, 3 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/pci/controller/dwc/pcie-qcom.c |
| +++ b/drivers/pci/controller/dwc/pcie-qcom.c |
| @@ -368,7 +368,8 @@ static int qcom_pcie_init_2_1_0(struct q |
| val &= ~BIT(0); |
| writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); |
| |
| - if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { |
| + if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || |
| + of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { |
| writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | |
| PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | |
| PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), |
| @@ -1329,6 +1330,7 @@ err_pm_runtime_put: |
| static const struct of_device_id qcom_pcie_match[] = { |
| { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, |
| { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 }, |
| + { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 }, |
| { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 }, |
| { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 }, |
| { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, |