| From e870793b277eeaf3c455971d9610f039fd9ab160 Mon Sep 17 00:00:00 2001 |
| From: Vladimir Oltean <vladimir.oltean@nxp.com> |
| Date: Thu, 14 Nov 2019 17:03:23 +0200 |
| Subject: [PATCH] net: mscc: ocelot: create a helper for changing the port MTU |
| |
| Since in an NPI/DSA setup, not all ports will have the same MTU, we need |
| to make sure the watermarks for pause frames and/or tail dropping logic |
| that existed in the driver is still coherent for the new MTU values. |
| |
| We need to do this because the NPI (aka external CPU) port needs an |
| increased MTU for the DSA tag. This will be done in a future patch. |
| |
| Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> |
| Reviewed-by: Andrew Lunn <andrew@lunn.ch> |
| Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| --- |
| drivers/net/ethernet/mscc/ocelot.c | 40 ++++++++++++++++++++++---------------- |
| 1 file changed, 23 insertions(+), 17 deletions(-) |
| |
| --- a/drivers/net/ethernet/mscc/ocelot.c |
| +++ b/drivers/net/ethernet/mscc/ocelot.c |
| @@ -2096,11 +2096,32 @@ static int ocelot_init_timestamp(struct |
| return 0; |
| } |
| |
| -static void ocelot_init_port(struct ocelot *ocelot, int port) |
| +static void ocelot_port_set_mtu(struct ocelot *ocelot, int port, size_t mtu) |
| { |
| struct ocelot_port *ocelot_port = ocelot->ports[port]; |
| int atop_wm; |
| |
| + ocelot_port_writel(ocelot_port, mtu, DEV_MAC_MAXLEN_CFG); |
| + |
| + /* Set Pause WM hysteresis |
| + * 152 = 6 * mtu / OCELOT_BUFFER_CELL_SZ |
| + * 101 = 4 * mtu / OCELOT_BUFFER_CELL_SZ |
| + */ |
| + ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | |
| + SYS_PAUSE_CFG_PAUSE_STOP(101) | |
| + SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port); |
| + |
| + /* Tail dropping watermark */ |
| + atop_wm = (ocelot->shared_queue_sz - 9 * mtu) / OCELOT_BUFFER_CELL_SZ; |
| + ocelot_write_rix(ocelot, ocelot_wm_enc(9 * mtu), |
| + SYS_ATOP, port); |
| + ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); |
| +} |
| + |
| +static void ocelot_init_port(struct ocelot *ocelot, int port) |
| +{ |
| + struct ocelot_port *ocelot_port = ocelot->ports[port]; |
| + |
| INIT_LIST_HEAD(&ocelot_port->skbs); |
| |
| /* Basic L2 initialization */ |
| @@ -2121,8 +2142,7 @@ static void ocelot_init_port(struct ocel |
| DEV_MAC_HDX_CFG); |
| |
| /* Set Max Length and maximum tags allowed */ |
| - ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN, |
| - DEV_MAC_MAXLEN_CFG); |
| + ocelot_port_set_mtu(ocelot, port, VLAN_ETH_FRAME_LEN); |
| ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | |
| DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | |
| DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, |
| @@ -2132,20 +2152,6 @@ static void ocelot_init_port(struct ocel |
| ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); |
| ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); |
| |
| - /* Set Pause WM hysteresis |
| - * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ |
| - * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ |
| - */ |
| - ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | |
| - SYS_PAUSE_CFG_PAUSE_STOP(101) | |
| - SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port); |
| - |
| - /* Tail dropping watermark */ |
| - atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; |
| - ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), |
| - SYS_ATOP, port); |
| - ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); |
| - |
| /* Drop frames with multicast source address */ |
| ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, |
| ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, |