| From be9165b9fdcf2a18ee201ffdaf8d69801387eb91 Mon Sep 17 00:00:00 2001 |
| From: Kuldeep Singh <kuldeep.singh@nxp.com> |
| Date: Tue, 18 Feb 2020 10:42:50 +0800 |
| Subject: [PATCH] spi: spi-fsl-qspi: Introduce variable to fix different |
| invalid master Id |
| |
| Different platforms have different Master with different SourceID on |
| AHB bus. The 0X0E Master ID is used by cluster 3 in case of LS2088A. |
| So, patch introduce an invalid master id variable to fix invalid |
| mastered on different platforms. |
| |
| Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> |
| Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> |
| [rebase] |
| Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
| --- |
| drivers/spi/spi-fsl-qspi.c | 17 +++++++++++++++++ |
| 1 file changed, 17 insertions(+) |
| |
| --- a/drivers/spi/spi-fsl-qspi.c |
| +++ b/drivers/spi/spi-fsl-qspi.c |
| @@ -68,6 +68,11 @@ |
| #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8) |
| #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16) |
| |
| +#define QUADSPI_BUF0CR 0x10 |
| +#define QUADSPI_BUF1CR 0x14 |
| +#define QUADSPI_BUF2CR 0x18 |
| +#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe |
| + |
| #define QUADSPI_BUF3CR 0x1c |
| #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31) |
| #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8) |
| @@ -197,6 +202,7 @@ |
| struct fsl_qspi_devtype_data { |
| unsigned int rxfifo; |
| unsigned int txfifo; |
| + int invalid_mstrid; |
| unsigned int ahb_buf_size; |
| unsigned int quirks; |
| bool little_endian; |
| @@ -205,6 +211,7 @@ struct fsl_qspi_devtype_data { |
| static const struct fsl_qspi_devtype_data vybrid_data = { |
| .rxfifo = SZ_128, |
| .txfifo = SZ_64, |
| + .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
| .ahb_buf_size = SZ_1K, |
| .quirks = QUADSPI_QUIRK_SWAP_ENDIAN, |
| .little_endian = true, |
| @@ -213,6 +220,7 @@ static const struct fsl_qspi_devtype_dat |
| static const struct fsl_qspi_devtype_data imx6sx_data = { |
| .rxfifo = SZ_128, |
| .txfifo = SZ_512, |
| + .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
| .ahb_buf_size = SZ_1K, |
| .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618, |
| .little_endian = true, |
| @@ -221,6 +229,7 @@ static const struct fsl_qspi_devtype_dat |
| static const struct fsl_qspi_devtype_data imx7d_data = { |
| .rxfifo = SZ_128, |
| .txfifo = SZ_512, |
| + .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
| .ahb_buf_size = SZ_1K, |
| .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | |
| QUADSPI_QUIRK_USE_TDH_SETTING, |
| @@ -230,6 +239,7 @@ static const struct fsl_qspi_devtype_dat |
| static const struct fsl_qspi_devtype_data imx6ul_data = { |
| .rxfifo = SZ_128, |
| .txfifo = SZ_512, |
| + .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
| .ahb_buf_size = SZ_1K, |
| .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | |
| QUADSPI_QUIRK_USE_TDH_SETTING, |
| @@ -239,6 +249,7 @@ static const struct fsl_qspi_devtype_dat |
| static const struct fsl_qspi_devtype_data ls1021a_data = { |
| .rxfifo = SZ_128, |
| .txfifo = SZ_64, |
| + .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, |
| .ahb_buf_size = SZ_1K, |
| .quirks = 0, |
| .little_endian = false, |
| @@ -248,6 +259,7 @@ static const struct fsl_qspi_devtype_dat |
| .rxfifo = SZ_128, |
| .txfifo = SZ_64, |
| .ahb_buf_size = SZ_1K, |
| + .invalid_mstrid = 0x0, |
| .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL, |
| .little_endian = true, |
| }; |
| @@ -661,6 +673,7 @@ static int fsl_qspi_exec_op(struct spi_m |
| void __iomem *base = q->iobase; |
| u32 addr_offset = 0; |
| int err = 0; |
| + int invalid_mstrid = q->devtype_data->invalid_mstrid; |
| |
| mutex_lock(&q->lock); |
| |
| @@ -684,6 +697,10 @@ static int fsl_qspi_exec_op(struct spi_m |
| qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC, |
| base + QUADSPI_SPTRCLR); |
| |
| + qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR); |
| + qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR); |
| + qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR); |
| + |
| fsl_qspi_prepare_lut(q, op); |
| |
| /* |