| #include <common.h> | |
| #include <sha256.h> | |
| #include <sha1.h> | |
| #include <asm/errno.h> | |
| #include "te200_sha.h" | |
| #include <asm/arch/cpu.h> | |
| static int wait_hash_command_done(int ms) | |
| { | |
| unsigned int val; | |
| int timeout = ms*1000; | |
| do { | |
| //wait bit0 to be set | |
| val = TE_REG_READ(TE_HASH_INTR_STAT); | |
| if (val & 0x1) | |
| break; | |
| timeout --; | |
| udelay(1); | |
| if(timeout == 0) { | |
| printf("TE200 hash time out\n\r"); | |
| return -1; | |
| } | |
| }while(1); | |
| TE_REG_WRITE(TE_HASH_INTR_STAT, 0x00000001); //clear int status | |
| return 0; | |
| } | |
| void sha256_starts_te200(sha256_context * ctx) | |
| { | |
| unsigned int val; | |
| int ret = 0; | |
| (void)ctx; | |
| val = TE_REG_READ(TE_CLK_CTRL); | |
| val &= ~1; //open sha clock | |
| TE_REG_WRITE(TE_CLK_CTRL, val); | |
| val = TE_REG_READ(TE_CLK_CTRL); | |
| val |= 1; //open sha clock | |
| TE_REG_WRITE(TE_CLK_CTRL, val); | |
| TE_REG_WRITE(TE_HASH_QUEUE, 0x80000041); //hash init cmd, sha-256 | |
| TE_REG_WRITE(TE_HASH_CTRL, 0x00000001); //trigger cmd | |
| ret = wait_hash_command_done(20); | |
| return ret; | |
| } | |
| void sha256_update_te200(sha256_context *ctx, const uint8_t *input, uint32_t length) | |
| { | |
| int ret = 0; | |
| flush_dcache_range(input, (uint32_t)input + length); | |
| TE_REG_WRITE(TE_HASH_QUEUE, 0x40000001); //hash proc cmd, big end.(0x40000003: little end) | |
| TE_REG_WRITE(TE_HASH_QUEUE, (uint32_t)input); | |
| TE_REG_WRITE(TE_HASH_QUEUE, (uint32_t)length); | |
| TE_REG_WRITE(TE_HASH_CTRL, 0x00000001); | |
| /* wait 64ms per 1MB */ | |
| ret = wait_hash_command_done(((length + 0xFFFFF) >> 14)); | |
| return; | |
| } | |
| void sha256_finish_te200(sha256_context * ctx, uint8_t digest[32]) | |
| { | |
| unsigned int val; | |
| int ret = 0; | |
| flush_dcache_range(digest, (uint32_t)digest + 32); | |
| TE_REG_WRITE(TE_HASH_QUEUE, 0x20000081); //hash finish cmd | |
| TE_REG_WRITE(TE_HASH_QUEUE, (uint32_t)digest); | |
| TE_REG_WRITE(TE_HASH_CTRL, 0x00000001); | |
| ret = wait_hash_command_done(100); | |
| val = TE_REG_READ(TE_CLK_CTRL); | |
| val &= ~1; //close sha clock | |
| TE_REG_WRITE(TE_CLK_CTRL, val); | |
| return; | |
| } |