| From a9f1c1d3e410596d0a39fd92562cc48ef960b1b7 Mon Sep 17 00:00:00 2001 |
| From: Li Yang <leoyang.li@nxp.com> |
| Date: Fri, 5 Oct 2018 18:33:49 -0500 |
| Subject: [PATCH] ARM: dts: accumulated change |
| |
| Signed-off-by: Li Yang <leoyang.li@nxp.com> |
| --- |
| arch/arm/boot/dts/ls1021a-qds.dts | 15 +++++++++++++++ |
| arch/arm/boot/dts/ls1021a-twr.dts | 15 +++++++++++++++ |
| arch/arm/boot/dts/ls1021a.dtsi | 29 ++++++++++++++++++++++++----- |
| 3 files changed, 54 insertions(+), 5 deletions(-) |
| |
| --- a/arch/arm/boot/dts/ls1021a-qds.dts |
| +++ b/arch/arm/boot/dts/ls1021a-qds.dts |
| @@ -126,6 +126,21 @@ |
| }; |
| }; |
| |
| +&qspi { |
| + num-cs = <2>; |
| + status = "okay"; |
| + |
| + qflash0: s25fl128s@0 { |
| + compatible = "spansion,m25p80"; |
| + #address-cells = <1>; |
| + #size-cells = <1>; |
| + spi-max-frequency = <20000000>; |
| + reg = <0>; |
| + spi-rx-bus-width = <4>; |
| + spi-tx-bus-width = <4>; |
| + }; |
| +}; |
| + |
| &enet0 { |
| tbi-handle = <&tbi0>; |
| phy-handle = <&sgmii_phy1c>; |
| --- a/arch/arm/boot/dts/ls1021a-twr.dts |
| +++ b/arch/arm/boot/dts/ls1021a-twr.dts |
| @@ -144,6 +144,21 @@ |
| }; |
| }; |
| |
| +&qspi { |
| + num-cs = <2>; |
| + status = "okay"; |
| + |
| + qflash0: n25q128a13@0 { |
| + compatible = "n25q128a13", "jedec,spi-nor"; |
| + #address-cells = <1>; |
| + #size-cells = <1>; |
| + spi-max-frequency = <20000000>; |
| + reg = <0>; |
| + spi-rx-bus-width = <4>; |
| + spi-tx-bus-width = <4>; |
| + }; |
| +}; |
| + |
| &enet0 { |
| tbi-handle = <&tbi0>; |
| phy-handle = <&sgmii_phy2>; |
| --- a/arch/arm/boot/dts/ls1021a.dtsi |
| +++ b/arch/arm/boot/dts/ls1021a.dtsi |
| @@ -167,12 +167,13 @@ |
| ifc: ifc@1530000 { |
| compatible = "fsl,ifc", "simple-bus"; |
| reg = <0x0 0x1530000 0x0 0x10000>; |
| + big-endian; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| dcfg: dcfg@1ee0000 { |
| compatible = "fsl,ls1021a-dcfg", "syscon"; |
| - reg = <0x0 0x1ee0000 0x0 0x10000>; |
| + reg = <0x0 0x1ee0000 0x0 0x1000>; |
| big-endian; |
| }; |
| |
| @@ -338,7 +339,7 @@ |
| }; |
| |
| i2c0: i2c@2180000 { |
| - compatible = "fsl,vf610-i2c"; |
| + compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2180000 0x0 0x10000>; |
| @@ -347,11 +348,12 @@ |
| clocks = <&clockgen 4 1>; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 39>, <&edma0 1 38>; |
| + fsl-scl-gpio = <&gpio3 23 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@2190000 { |
| - compatible = "fsl,vf610-i2c"; |
| + compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2190000 0x0 0x10000>; |
| @@ -360,6 +362,7 @@ |
| clocks = <&clockgen 4 1>; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 37>, <&edma0 1 36>; |
| + fsl-scl-gpio = <&gpio3 23 0>; |
| status = "disabled"; |
| }; |
| |
| @@ -546,6 +549,16 @@ |
| status = "disabled"; |
| }; |
| |
| + ftm0: ftm0@29d0000 { |
| + compatible = "fsl,ftm-alarm"; |
| + reg = <0x0 0x29d0000 0x0 0x10000>, |
| + <0x0 0x1ee2140 0x0 0x4>; |
| + reg-names = "ftm", "FlexTimer1"; |
| + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
| + big-endian; |
| + status = "okay"; |
| + }; |
| + |
| pwm1: pwm@29e0000 { |
| compatible = "fsl,vf610-ftm-pwm"; |
| #pwm-cells = <3>; |
| @@ -828,6 +841,8 @@ |
| dr_mode = "host"; |
| snps,quirk-frame-length-adjustment = <0x20>; |
| snps,dis_rxdet_inp3_quirk; |
| + usb3-lpm-capable; |
| + snps,dis-u1u2-when-u3-quirk; |
| snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
| }; |
| |
| @@ -836,7 +851,9 @@ |
| reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ |
| 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ |
| reg-names = "regs", "config"; |
| - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ |
| + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ |
| + interrupt-names = "pme", "aer"; |
| fsl,pcie-scfg = <&scfg 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| @@ -860,7 +877,9 @@ |
| reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ |
| 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ |
| reg-names = "regs", "config"; |
| - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
| + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ |
| + interrupt-names = "pme", "aer"; |
| fsl,pcie-scfg = <&scfg 1>; |
| #address-cells = <3>; |
| #size-cells = <2>; |