| From 494c1f9c5c86396d2974c6072f728e2325b72703 Mon Sep 17 00:00:00 2001 |
| From: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> |
| Date: Wed, 7 Mar 2018 11:35:07 +0200 |
| Subject: [PATCH] Sound: Soc: fsl: Set SAI Channel Mode to Output Mode |
| |
| Transmit data pins will output zero when slots are masked or channels |
| are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when |
| slots are masked or channels are disabled. When data pins are tri-stated, |
| there is noise on some channels when FS clock value is high and data is |
| read while fsclk is transitioning from high to low. |
| |
| Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> |
| Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> |
| --- |
| sound/soc/fsl/fsl_sai.c | 14 +++++++++++--- |
| sound/soc/fsl/fsl_sai.h | 2 ++ |
| 2 files changed, 13 insertions(+), 3 deletions(-) |
| |
| --- a/sound/soc/fsl/fsl_sai.c |
| +++ b/sound/soc/fsl/fsl_sai.c |
| @@ -589,6 +589,11 @@ static int fsl_sai_hw_params(struct snd_ |
| |
| val_cr4 |= FSL_SAI_CR4_FRSZ(slots); |
| |
| + /* Output Mode - data pins transmit 0 when slots are masked |
| + * or channels are disabled |
| + */ |
| + val_cr4 |= FSL_SAI_CR4_CHMOD; |
| + |
| /* |
| * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will |
| * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), |
| @@ -599,14 +604,16 @@ static int fsl_sai_hw_params(struct snd_ |
| if (!sai->slave_mode[tx]) { |
| if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { |
| regmap_update_bits(sai->regmap, FSL_SAI_TCR4(offset), |
| - FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, |
| + FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | |
| + FSL_SAI_CR4_CHMOD_MASK, |
| val_cr4); |
| regmap_update_bits(sai->regmap, FSL_SAI_TCR5(offset), |
| FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | |
| FSL_SAI_CR5_FBT_MASK, val_cr5); |
| } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { |
| regmap_update_bits(sai->regmap, FSL_SAI_RCR4(offset), |
| - FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, |
| + FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | |
| + FSL_SAI_CR4_CHMOD_MASK, |
| val_cr4); |
| regmap_update_bits(sai->regmap, FSL_SAI_RCR5(offset), |
| FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | |
| @@ -682,7 +689,8 @@ static int fsl_sai_hw_params(struct snd_ |
| } |
| |
| regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset), |
| - FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, |
| + FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | |
| + FSL_SAI_CR4_CHMOD_MASK, |
| val_cr4); |
| regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, offset), |
| FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | |
| --- a/sound/soc/fsl/fsl_sai.h |
| +++ b/sound/soc/fsl/fsl_sai.h |
| @@ -129,6 +129,8 @@ |
| #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) |
| #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) |
| #define FSL_SAI_CR4_SYWD_MASK (0x1f << 8) |
| +#define FSL_SAI_CR4_CHMOD (1 << 5) |
| +#define FSL_SAI_CR4_CHMOD_MASK (1 << 5) |
| #define FSL_SAI_CR4_MF BIT(4) |
| #define FSL_SAI_CR4_FSE BIT(3) |
| #define FSL_SAI_CR4_FSP BIT(1) |