b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2023 ASR Microelectronics Co., Ltd. |
| 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | #include "asr1806.dtsi" |
| 8 | |
| 9 | / { |
| 10 | model = "ASR 1806(FALCON-T) Board EVB"; |
| 11 | compatible = "asr,1803-evb", "asr,1803"; |
| 12 | |
| 13 | chosen { |
| 14 | bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M"; |
| 15 | }; |
| 16 | |
| 17 | memory { |
| 18 | reg = <0x00000000 0x10000000>; |
| 19 | }; |
| 20 | |
| 21 | firmware { |
| 22 | optee { |
| 23 | compatible = "linaro,optee-tz"; |
| 24 | method = "smc"; |
| 25 | }; |
| 26 | }; |
| 27 | |
| 28 | soc { |
| 29 | axi@d4200000 { /* AXI */ |
| 30 | usbphy: usbphy@d4207000 { |
| 31 | status = "okay"; |
| 32 | }; |
| 33 | #ifdef CONFIG_USB_DWC2_ASR_OTG /* otg mode */ |
| 34 | usb: usb@c0000000 { |
| 35 | dr_mode = "otg"; |
| 36 | pinctrl-names = "default","sleep"; |
| 37 | pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>; |
| 38 | pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>; |
| 39 | usbid_gpio = <99>; |
| 40 | edge_detect_gpio = <99>; |
| 41 | otg,use-gpio-vbus; |
| 42 | gpio-num = <122>; |
| 43 | status = "okay"; |
| 44 | }; |
| 45 | #else |
| 46 | usb: usb@c0000000 { |
| 47 | status = "okay"; |
| 48 | }; |
| 49 | #endif |
| 50 | |
| 51 | eth0: asr-eth@0xd4281800 { |
| 52 | compatible = "asr,asr-eth"; |
hj.shao | 213a35e | 2025-06-24 04:25:54 -0700 | [diff] [blame] | 53 | pinctrl-names = "default", "rgmii-pins", "sleep"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 54 | pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>; |
hj.shao | 213a35e | 2025-06-24 04:25:54 -0700 | [diff] [blame] | 55 | pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>; |
| 56 | pinctrl-2 = <&emac_pmx_func0_slp &emac_pmx_func1_slp &emac_pmx_func2_slp>; |
| 57 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 58 | reg = <0xd4281800 0x200>; |
| 59 | interrupts = <10 11>; |
| 60 | lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| 61 | clocks = <&soc_clocks ASR1803_CLK_EMAC |
| 62 | &soc_clocks ASR1803_CLK_EMAC_PTP>; |
| 63 | clock-names = "emac-clk", "ptp-clk"; |
| 64 | ptp-support; |
| 65 | ptp-clk-rate = <100000000>; |
| 66 | status = "okay"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 67 | enable-suspend; |
hj.shao | f72d6ff | 2025-06-10 04:34:26 -0700 | [diff] [blame] | 68 | // reset-gpio = <&gpio 42 0>; |
| 69 | // reset-active-low; |
| 70 | // reset-delays-us = <100000 100000 100000>; |
| 71 | local-mac-address = [02 00 00 00 10 01]; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 72 | //ldo-gpio = <&gpio 40 0>; |
| 73 | //ldo-active-low; |
| 74 | // ldo-delays-us = <0 100000 100000>; |
| 75 | //vmmc-supply = <0x19>; |
| 76 | mdio-clk-div = <254>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 77 | flow-control-threshold = <60 90>; |
| 78 | clk-tuning-enable; |
| 79 | /* clk-config(32bit) |
| 80 | * |
| 81 | * clk_sel(clk-config[23:16]) |
| 82 | * RGMII: |
| 83 | * tx | clk_sel: 0 - from external RX clock |
| 84 | * 1 - from inverted external RX clock |
| 85 | * rx | clk_sel: 0 - from external RX clock |
| 86 | * 1 - from inverted external RX clock |
| 87 | * |
| 88 | * RMII: |
| 89 | * tx | clk_sel: 0 - RMII clock |
| 90 | * 1 - Inverted RMII clock |
| 91 | * rx | clk_sel: 0 - RMII clock |
| 92 | * 1 - Inverted RMII clock |
| 93 | * |
| 94 | */ |
| 95 | #if 0 |
| 96 | /* enable 1000M phy*/ |
| 97 | 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 98 | phy-handle = <&phy3>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 99 | #else |
| 100 | /* enable 100M phy*/ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 101 | 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */ |
hj.shao | fe1632a | 2025-06-05 00:19:33 -0700 | [diff] [blame] | 102 | phy-handle = <&phy0>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 103 | #endif |
| 104 | /* enable fix link for ethernet switch */ |
| 105 | /* |
| 106 | fixed-link { |
| 107 | speed = <100>; |
| 108 | full-duplex; |
| 109 | phy-mode = "rmii"; |
| 110 | }; |
| 111 | */ |
| 112 | |
| 113 | mdio: mdio-bus { |
| 114 | #address-cells = <0x1>; |
| 115 | #size-cells = <0x0>; |
| 116 | /* YT8521 10M/100M/100OM 1.8V RGMII PHY */ |
| 117 | phy0: phy@0 { |
| 118 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 119 | device_type = "ethernet-phy"; |
| 120 | reg = <0x0>; /* set phy address*/ |
hj.shao | f72d6ff | 2025-06-10 04:34:26 -0700 | [diff] [blame] | 121 | rst-gpio = <&gpio 42 0>; |
hj.shao | fb3ba9b | 2025-06-19 02:53:56 -0700 | [diff] [blame] | 122 | //#LYNQ_MODFIY modify for task-1618 2025/6/19 start |
| 123 | power-en-gpio = <&gpio 32 1>; |
| 124 | //#LYNQ_MODFIY modify for task-1618 2025/6/19 end |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 125 | phy-mode = "rgmii"; |
hj.shao | fe1632a | 2025-06-05 00:19:33 -0700 | [diff] [blame] | 126 | // tx_rx_delay = <0xb 0x0>; /* 150ps per step*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | /* YT8512B 10M/100M 3.3V RMII PHY */ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 130 | // phy3: phy@3 { |
| 131 | // compatible = "ethernet-phy-ieee802.3-c22"; |
| 132 | // device_type = "ethernet-phy"; |
| 133 | // reg = <0x3>; /* set phy address*/ |
| 134 | // phy-mode = "rmii"; |
| 135 | // driver_strength = <0x3>; |
| 136 | // }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 137 | |
| 138 | /* IP175D 10M/100M 3.3V RMII SWITCH */ |
| 139 | phy1: phy@1 { |
| 140 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 141 | device_type = "ethernet-phy"; |
| 142 | reg = <0x1>; /* set phy address*/ |
| 143 | phy-mode = "rmii"; |
| 144 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 145 | |
| 146 | |
| 147 | /* jl 3103 phy */ |
| 148 | phy3: phy@3 { |
| 149 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 150 | device_type = "ethernet-phy"; |
| 151 | reg = <0x3>; /* set phy address*/ |
| 152 | phy-mode = "rgmii-id"; |
| 153 | lynq,jl3103=<100 0>; |
| 154 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 155 | }; |
| 156 | }; |
| 157 | qspi: spi@0xd420b000 { |
| 158 | asr,qspi-freq = <78000000>; |
| 159 | status = "okay"; |
| 160 | }; |
zw.wang | 3ef3a31 | 2025-06-13 16:21:25 +0800 | [diff] [blame] | 161 | |
| 162 | #if 0 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 163 | /* SD card */ |
| 164 | sdh0: sdh@d4280000 { |
| 165 | pinctrl-names = "default", "slow", "fast", "sleep"; |
| 166 | pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>; |
| 167 | pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>; |
| 168 | pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>; |
| 169 | pinctrl-3 = <&sdh0_pmx_cd_wakeup>; |
| 170 | /* |
| 171 | * Genernal use, juse set vmmc-supply and vqmmc-supply |
| 172 | * vmmc-supply = <&supply1> |
| 173 | * vqmmc-supply = <&supply2> |
| 174 | * |
| 175 | * For compatibility, to select one from two supply source |
| 176 | * vmmc-supply = <&supply1 &supply1_backup>; |
| 177 | * vqmmc-supply = <&supply2 &supply2_backup>; |
| 178 | * vmmc2-supply = <&supply1_backup &supply1>; |
| 179 | * vqmmc2-supply = <&supply2_backup &supply2>; |
| 180 | */ |
| 181 | vmmc-supply = <&vcc_sdh1>; |
zw.wang | 5deb3e8 | 2025-05-30 11:29:23 +0800 | [diff] [blame] | 182 | vqmmc-supply = <&pm802ldo6 &pm803ldo8>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 183 | #ifndef CONFIG_ASR_DSDS |
| 184 | vmmc2-supply = <&vcc_sdh1 &pm802ldo4>; |
| 185 | vqmmc2-supply = <&pm803ldo8 &pm802ldo6>; |
| 186 | #endif |
| 187 | bus-width = <4>; |
| 188 | no-mmc; |
| 189 | no-sdio; |
| 190 | /*non-removable; |
| 191 | broken-cd;*/ |
| 192 | wp-inverted; |
| 193 | asr,sdh-pm-runtime-en; |
| 194 | asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>; |
| 195 | #if 1 /* CD via gpio */ |
zw.wang | 5deb3e8 | 2025-05-30 11:29:23 +0800 | [diff] [blame] | 196 | //cd-gpios = <&gpio 90 1>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 197 | asr,sdh-quirks2 = <( |
| 198 | SDHCI_QUIRK2_SET_AIB_MMC | |
| 199 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
| 200 | )>; |
| 201 | asr,sdh-host-caps = <( |
| 202 | MMC_CAP_CD_WAKE |
| 203 | )>; |
| 204 | asr,sdh-quirks = <( |
| 205 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
| 206 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| 207 | )>; |
| 208 | #else /* CD via SDH */ |
| 209 | asr,sdh-quirks = <( |
| 210 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| 211 | )>; |
| 212 | asr,sdh-quirks2 = <( |
| 213 | SDHCI_QUIRK2_SET_AIB_MMC | |
| 214 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
| 215 | SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON |
| 216 | )>; |
| 217 | #endif |
| 218 | /* prop "sdh-dtr-data": |
| 219 | <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */ |
| 220 | asr,sdh-dtr-data = |
| 221 | <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>, |
| 222 | <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>, |
| 223 | <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>, |
| 224 | <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>, |
| 225 | <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>, |
| 226 | <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>; |
| 227 | status = "okay"; |
| 228 | }; |
zw.wang | 3ef3a31 | 2025-06-13 16:21:25 +0800 | [diff] [blame] | 229 | #endif |
| 230 | /* EMMC*/ |
| 231 | sdh0: sdh@d4280000 { |
| 232 | pinctrl-names = "default", "slow", "fast"; |
| 233 | pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>; |
| 234 | pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>; |
| 235 | pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>; |
| 236 | vmmc-supply = <&pm803ldo6 &pm803ldo8>; |
| 237 | bus-width = <4>; |
| 238 | no-sdio; |
| 239 | no-sd; |
| 240 | non-removable; |
| 241 | broken-cd; |
| 242 | wp-inverted; |
| 243 | asr,sdh-pm-runtime-en; |
| 244 | cap-mmc-highspeed; |
| 245 | mmc-ddr-1_8v; |
| 246 | asr,sdh-host-caps-disable = <(MMC_CAP_1_2V_DDR)>; |
zw.wang | 5faa4c5 | 2025-08-01 18:34:54 +0800 | [diff] [blame] | 247 | asr,sdh-host-caps2-disable = <(MMC_CAP2_HSX00_1_2V | MMC_CAP2_HS400 )>; |
zw.wang | 3ef3a31 | 2025-06-13 16:21:25 +0800 | [diff] [blame] | 248 | asr,sdh-host-caps2 = <( |
| 249 | MMC_CAP2_ONLY_1_8V |
| 250 | )>; |
| 251 | asr,sdh-quirks = <( |
| 252 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
| 253 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| 254 | )>; |
| 255 | asr,sdh-quirks2 = <( |
| 256 | SDHCI_QUIRK2_SET_AIB_MMC | |
| 257 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
| 258 | )>; |
| 259 | /* prop "sdh-dtr-data": |
| 260 | <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */ |
| 261 | asr,sdh-dtr-data = |
| 262 | <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>, |
| 263 | <PXA_MMC_TIMING_MMC_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>, |
| 264 | <PXA_MMC_TIMING_MMC_DDR52 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>, |
zw.wang | 5faa4c5 | 2025-08-01 18:34:54 +0800 | [diff] [blame] | 265 | <PXA_MMC_TIMING_MMC_HS200 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 53 0 0 0>, |
zw.wang | 3ef3a31 | 2025-06-13 16:21:25 +0800 | [diff] [blame] | 266 | <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>; |
| 267 | status = "okay"; |
| 268 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 269 | |
| 270 | /* SDIO */ |
| 271 | sdh1: sdh@d4280800 { |
zw.wang | ad00beb | 2025-06-24 16:54:39 +0800 | [diff] [blame] | 272 | pinctrl-names = "default", "fast", "sleep_sdio"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 273 | pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2>; |
| 274 | pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast>; |
zw.wang | ad00beb | 2025-06-24 16:54:39 +0800 | [diff] [blame] | 275 | pinctrl-2 = <&sdh1_pmx_func1_sleep_sdio &sdh1_pmx_func2_sleep_sdio>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 276 | /* pinctrl-2 = <&sdh1_pmx_edge_wakeup>;*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 277 | bus-width = <4>; |
| 278 | no-mmc; |
| 279 | no-sd; |
| 280 | non-removable; |
| 281 | keep-power-in-suspend; |
| 282 | enable-sdio-wakeup; |
| 283 | /* clk-scaling-config: |
| 284 | <up_threshold down_threshold polling_interval> */ |
| 285 | clk-scaling-config = <25 12 200>; |
| 286 | min-ddr-qos = <156000 312000 400000>; |
| 287 | asr,sdh-pm-runtime-en; |
| 288 | asr,sdh-quirks = <( |
| 289 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
| 290 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| 291 | )>; |
| 292 | asr,sdh-quirks2 = <( |
| 293 | SDHCI_QUIRK2_NO_TIMER_RETUNING | |
| 294 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
| 295 | SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON |
| 296 | )>; |
| 297 | asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>; |
| 298 | asr,sdh-host-caps2 = <( |
| 299 | MMC_CAP2_ONLY_1_8V | |
| 300 | MMC_CAP2_DISABLE_PROBE_CDSCAN | |
| 301 | MMC_CAP2_CLK_SCALE | |
| 302 | MMC_CAP2_BUS_CLK_NO_SCALE |
| 303 | )>; |
| 304 | /* prop "sdh-dtr-data": |
| 305 | <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */ |
| 306 | asr,sdh-dtr-data = |
| 307 | <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>, |
| 308 | <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>, |
| 309 | <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>, |
| 310 | <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>, |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 311 | //<PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>, |
| 312 | <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_52M PXA_SDH_DTR_52M 0 0 0 0>, |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 313 | <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>; |
| 314 | status = "okay"; |
| 315 | }; |
| 316 | pcie0: pcie@0xd4288000{ |
| 317 | reset-gpios = <&gpio 42 0 >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 318 | status = "disbabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 319 | }; |
| 320 | pciephy0: pcie-phy@d4206000 { |
| 321 | status = "okay"; |
| 322 | }; |
| 323 | }; |
| 324 | |
| 325 | apb@d4000000 { |
| 326 | ssp_dai1: pxa-ssp-dai@1 { |
| 327 | compatible = "asr,pxa-ssp-dai"; |
| 328 | reg = <0x1 0x0>; |
| 329 | |
| 330 | port = <&ssp1>; |
| 331 | pinctrl-names = "default","ssp"; |
| 332 | pinctrl-0 = <&i2s_gpio>; |
| 333 | pinctrl-1 = <&i2s_func>; |
| 334 | ssp-gpio = <&gpio 25 0 &gpio 26 0 &gpio 27 0 &gpio 28 0>; |
| 335 | |
| 336 | dmas = <&pdma0 54 1 |
| 337 | &pdma0 55 1>; |
| 338 | dma-names = "rx", "tx"; |
| 339 | |
| 340 | platform_driver_name = "pdma_platform"; |
| 341 | burst_size = <4>; |
| 342 | playback_period_bytes = <2048>; |
| 343 | playback_buffer_bytes = <4096>; |
| 344 | capture_period_bytes = <2048>; |
| 345 | capture_buffer_bytes = <4096>; |
| 346 | }; |
| 347 | mfpr: mfpr@d401e000 { |
| 348 | status = "okay"; |
| 349 | /* intend to replace lpm-board-cfg |
| 350 | no-apbsd-in-d1pp = <0x1>; //"wakeup-state-d1pp" |
| 351 | pin1:pin1@d401e01B0 { |
| 352 | offset = <0x1B0>; |
| 353 | udr-cfg = <0xA040>; |
| 354 | }; |
| 355 | pin2:pin2@d401e01B4 { |
| 356 | offset = <0x1B4>; |
| 357 | udr-cfg = <0xA040>; |
| 358 | }; |
| 359 | */ |
| 360 | }; |
| 361 | timer0: timer@d4014000 { |
| 362 | status = "okay"; |
| 363 | }; |
| 364 | uart1: uart@d4017000 { /* nezhas evb use ap uart */ |
| 365 | pinctrl-names = "default","sleep"; |
| 366 | pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>; |
| 367 | pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 368 | //edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 369 | status = "okay"; |
| 370 | }; |
| 371 | uart2: uart@d4036000 { |
| 372 | pinctrl-names = "default"; |
hj.shao | 9f48a91 | 2025-06-11 00:19:29 -0700 | [diff] [blame] | 373 | |
| 374 | //#LYNQ_MODFIY modify for task-1618 2025/6/11 start |
| 375 | pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd>; //&gps_pmx_func_cts_rts>; |
| 376 | //#LYNQ_MODFIY modify for task-1618 2025/6/11 end |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 377 | status = "okay"; |
| 378 | }; |
| 379 | uart3: uart@d4018000 { |
| 380 | pinctrl-names = "default"; |
| 381 | pinctrl-0 = <&uart3_pmx_func>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 382 | status = "okay"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 383 | }; |
| 384 | uart4: uart@d401f000 { |
zw.wang | ad00beb | 2025-06-24 16:54:39 +0800 | [diff] [blame] | 385 | pinctrl-names = "default","sleep"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 386 | pinctrl-0 = <&uart4_pmx_func>; /*BAUD :9600*/ |
zw.wang | ad00beb | 2025-06-24 16:54:39 +0800 | [diff] [blame] | 387 | pinctrl-1 = <&uart4_pmx_func_sleep>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 388 | /*pinctrl-0 = <&uart4_pmx_func_rxd &uart4_pmx_func_txd &uart4_pmx_func_cts_rts>;*/ |
| 389 | status = "okay"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 390 | }; |
| 391 | rtc: rtc@d4010000 { |
| 392 | status = "okay"; |
| 393 | }; |
| 394 | pmx: pinmux@d401e000 { |
| 395 | /* pin base = base_addr / 4, nr pins & gpio function */ |
| 396 | pinctrl-single,gpio-range = < |
| 397 | /* |
| 398 | * GPIO number is hardcoded for range at here. |
| 399 | * In gpio chip, GPIO number is not hardcoded for range. |
| 400 | * Since one gpio pin may be routed to multiple pins, |
| 401 | * define these gpio range in pxa910-dkb.dts not pxa910.dtsi. |
| 402 | */ |
| 403 | /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */ |
| 404 | &range 55 32 0 /* GPIO0 ~ GPIO31 */ |
| 405 | &range 87 32 0 /* GPIO32 ~ GPIO63 */ |
| 406 | &range 119 32 0 /* GPIO64 ~ GPIO95 */ |
| 407 | &range 151 32 0 /* GPIO96 ~ GPIO127 */ |
| 408 | >; |
| 409 | |
| 410 | ssp0_pmx_func: ssp0_pmx_func { |
| 411 | pinctrl-single,pins = < |
| 412 | GPIO36 AF1 /* TXD */ |
| 413 | GPIO35 AF1 /* RXD */ |
| 414 | GPIO34 AF1 /* FRM */ |
| 415 | /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */ |
| 416 | GPIO33 AF1 /* SCLK */ |
| 417 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 418 | DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage |
| 419 | }; |
| 420 | ssp2_pmx_func: ssp2_pmx_func { |
| 421 | pinctrl-single,pins = < |
| 422 | GPIO37 AF3 /* TXD */ |
| 423 | GPIO38 AF3 /* SCLK */ |
| 424 | GPIO39 AF3 /* FRM */ |
| 425 | GPIO40 AF3 /* RXD */ |
| 426 | >; |
| 427 | DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 428 | }; |
| 429 | lcd_bl_func: lcd_bl_func { |
| 430 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 431 | /* VCXO_OUT AF1 GPIO126, lcd bl */ |
| 432 | /* GPIO24 AF0 reset */ |
| 433 | /* GPIO22 AF0 lcd d/c */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 434 | >; |
| 435 | MFP_DEFAULT; |
| 436 | }; |
| 437 | uart1_pmx_func1: uart1_pmx_func1 { |
| 438 | pinctrl-single,pins = < |
| 439 | GPIO29 AF1 |
| 440 | >; |
| 441 | MFP_DEFAULT; |
| 442 | }; |
| 443 | uart1_pmx_func2: uart1_pmx_func2 { |
| 444 | pinctrl-single,pins = < |
| 445 | GPIO30 AF1 |
| 446 | >; |
| 447 | MFP_DEFAULT; |
| 448 | }; |
| 449 | uart1_pmx_func1_sleep: uart1_pmx_func1_sleep { |
| 450 | pinctrl-single,pins = < |
| 451 | GPIO29 AF1 |
| 452 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 453 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 454 | }; |
| 455 | twsi0_pmx_func: twsi0_pmx_func { |
| 456 | pinctrl-single,pins = < |
| 457 | GPIO49 AF1 |
| 458 | GPIO50 AF1 |
| 459 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 460 | DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 461 | }; |
| 462 | twsi0_pmx_gpio: twsi0_pmx_gpio { |
| 463 | pinctrl-single,pins = < |
| 464 | GPIO49 AF0 |
| 465 | GPIO50 AF0 |
| 466 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 467 | DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 468 | }; |
yu.dong | 23a7d13 | 2025-06-24 10:47:01 -0700 | [diff] [blame] | 469 | twsi0_pmx_sleep: twsi0_pmx_sleep { |
| 470 | pinctrl-single,pins = < |
| 471 | GPIO49 AF0 |
| 472 | GPIO50 AF0 |
| 473 | >; |
| 474 | DS_OFF;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 475 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 476 | #if 1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 477 | twsi1_pmx_func: twsi1_pmx_func { |
| 478 | pinctrl-single,pins = < |
| 479 | GPIO10 AF1 |
| 480 | GPIO11 AF1 |
| 481 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 482 | DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 483 | }; |
| 484 | twsi1_pmx_gpio: twsi1_pmx_gpio { |
| 485 | pinctrl-single,pins = < |
| 486 | GPIO10 AF0 |
| 487 | GPIO11 AF0 |
| 488 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 489 | DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 490 | }; |
yu.dong | 23a7d13 | 2025-06-24 10:47:01 -0700 | [diff] [blame] | 491 | twsi1_pmx_sleep: twsi1_pmx_sleep { |
| 492 | pinctrl-single,pins = < |
| 493 | GPIO10 AF0 |
| 494 | GPIO11 AF0 |
| 495 | >; |
| 496 | DS_OFF;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 497 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 498 | #endif |
| 499 | /* no pull, no LPM */ |
| 500 | dvc_pmx_func: dvc_pmx_func { |
| 501 | /* hw-dvc */ |
| 502 | pinctrl-single,pins = < |
| 503 | TDS_DIO0 AF0 |
| 504 | TDS_DIO1 AF0 |
| 505 | >; |
| 506 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 507 | }; |
| 508 | leds_pmx_func: leds_pmx_func { |
| 509 | pinctrl-single,pins = < |
| 510 | DF_IO10 AF1 |
| 511 | DF_IO11 AF1 |
| 512 | DF_IO12 AF1 |
| 513 | >; |
| 514 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 515 | }; |
| 516 | |
| 517 | gps_pmx_onoff: gps_pmx_onoff { |
| 518 | pinctrl-single,pins = < |
| 519 | TDS_TXREV AF1 |
| 520 | >; |
| 521 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 522 | }; |
| 523 | gps_pmx_reset: gps_pmx_reset { |
| 524 | pinctrl-single,pins = < |
| 525 | TDS_RXON AF1 |
| 526 | >; |
| 527 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 528 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 529 | |
| 530 | //zqy |
| 531 | gnss_clk_on: gnss_clk_on { |
| 532 | pinctrl-single,pins = < |
| 533 | GPIO43 AF2 /*32K CLK */ |
| 534 | |
| 535 | /*VCXO_REQ AF1 GPIO[125] GPS_WAKE_HOST */ |
| 536 | GPIO47 AF0 /* HOST_WAKE_GPS */ |
| 537 | GPIO45 AF0 /*RESET */ |
| 538 | CLK_REQ AF1 /*sleep en*/ |
| 539 | |
| 540 | >; |
| 541 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW; |
| 542 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 543 | gps_pmx_uart_rxd: gps_pmx_uart_rxd { |
| 544 | /* gps dedicated uart */ |
| 545 | pinctrl-single,pins = < |
| 546 | GPIO51 AF1 |
hj.shao | 9f48a91 | 2025-06-11 00:19:29 -0700 | [diff] [blame] | 547 | |
| 548 | //#LYNQ_MODFIY modify for task-1618 2025/6/11 start |
| 549 | /*GPIO32 AF1*/ |
| 550 | //#LYNQ_MODFIY modify for task-1618 2025/6/11 end |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 551 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 552 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 553 | }; |
| 554 | gps_pmx_uart_txd: gps_pmx_uart_txd { |
| 555 | /* gps dedicated uart */ |
| 556 | pinctrl-single,pins = < |
| 557 | GPIO52 AF1 |
hj.shao | 9f48a91 | 2025-06-11 00:19:29 -0700 | [diff] [blame] | 558 | //#LYNQ_MODFIY modify for task-1618 2025/6/11 start |
| 559 | /*GPIO31 AF1*/ |
| 560 | //#LYNQ_MODFIY modify for task-1618 2025/6/11 end |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 561 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 562 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 563 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 564 | gps_pmx_func_cts_rts: gps_pmx_func_cts_rts { |
| 565 | pinctrl-single,pins = < |
| 566 | GPIO31 AF1 /* cts */ |
| 567 | GPIO32 AF1 /* rts */ |
| 568 | >; |
| 569 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 570 | }; |
| 571 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 572 | uart3_pmx_func: uart3_pmx_func { |
| 573 | pinctrl-single,pins = < |
| 574 | GPIO53 AF1 /* RX */ |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 575 | /* GPIO54 AF1 TX */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 576 | >; |
lichengzhang | b746a89 | 2025-06-24 15:41:08 +0800 | [diff] [blame] | 577 | MFP_PULL_DOWN; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 578 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 579 | |
| 580 | |
| 581 | uart4_pmx_func_rxd: uart4_pmx_func_rxd { |
| 582 | pinctrl-single,pins = < |
| 583 | GPIO37 AF2 |
| 584 | GPIO40 AF2 |
| 585 | >; |
| 586 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 587 | }; |
| 588 | uart4_pmx_func_txd: uart4_pmx_func_txd { |
| 589 | pinctrl-single,pins = < |
| 590 | GPIO38 AF2 |
| 591 | GPIO39 AF2 |
| 592 | >; |
| 593 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 594 | }; |
| 595 | |
| 596 | uart4_pmx_func_cts_rts: uart4_pmx_func_cts_rts { |
| 597 | pinctrl-single,pins = < |
| 598 | GPIO39 AF2 |
| 599 | GPIO40 AF2 |
| 600 | >; |
| 601 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 602 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 603 | uart4_pmx_func: uart4_pmx_func { |
| 604 | pinctrl-single,pins = < |
| 605 | GPIO44 AF1 /* RX */ |
| 606 | GPIO45 AF1 /* TX */ |
| 607 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 608 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 609 | }; |
zw.wang | ad00beb | 2025-06-24 16:54:39 +0800 | [diff] [blame] | 610 | uart4_pmx_func_sleep: uart4_pmx_func_sleep { |
| 611 | pinctrl-single,pins = < |
| 612 | GPIO44 AF0 /* RX */ |
| 613 | GPIO45 AF0 /* TX */ |
| 614 | >; |
| 615 | MFP_PULL_DOWN; |
| 616 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 617 | panel_rst_func: panel_rst_func { |
| 618 | pinctrl-single,pins = < |
| 619 | DF_nCS1 AF1 |
| 620 | >; |
| 621 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 622 | }; |
| 623 | |
| 624 | sd_ldo_en: sd_ldo_en { |
| 625 | pinctrl-single,pins = < |
| 626 | GPIO45 AF0 |
| 627 | >; |
| 628 | MFP_PULL_DOWN; |
| 629 | }; |
| 630 | sdh0_pmx_func1: sdh0_pmx_func1 { |
| 631 | pinctrl-single,pins = < |
| 632 | MMC1_DAT3 AF0 |
| 633 | MMC1_DAT2 AF0 |
| 634 | MMC1_DAT1 AF0 |
| 635 | MMC1_DAT0 AF0 |
| 636 | MMC1_CMD AF0 |
| 637 | >; |
| 638 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 639 | }; |
| 640 | sdh0_pmx_func2: sdh0_pmx_func2 { |
| 641 | pinctrl-single,pins = < |
| 642 | MMC1_CLK AF0 |
| 643 | >; |
| 644 | DS_MEDIUM;PULL_NONE;EDGE_NONE; |
| 645 | }; |
| 646 | sdh0_pmx_func3: sdh0_pmx_func3 { |
| 647 | pinctrl-single,pins = < |
| 648 | MMC1_CD AF1 |
| 649 | >; |
| 650 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 651 | }; |
| 652 | sdh0_pmx_cd_wakeup: sdh0_pmx_func1_cd_wakeup { |
| 653 | pinctrl-single,pins = < |
| 654 | MMC1_CD AF1 |
| 655 | >; |
| 656 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 657 | }; |
| 658 | sdh0_pmx_func1_slow: sdh0_pmx_func1_slow { |
| 659 | pinctrl-single,pins = < |
| 660 | MMC1_DAT3 AF0 |
| 661 | MMC1_DAT2 AF0 |
| 662 | MMC1_DAT1 AF0 |
| 663 | MMC1_DAT0 AF0 |
| 664 | MMC1_CMD AF0 |
| 665 | >; |
| 666 | DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 667 | }; |
| 668 | sdh0_pmx_func2_slow: sdh0_pmx_func2_slow { |
| 669 | pinctrl-single,pins = < |
| 670 | MMC1_CLK AF0 |
| 671 | >; |
| 672 | DS_FAST0;PULL_NONE;EDGE_NONE; |
| 673 | }; |
| 674 | sdh0_pmx_func1_fast: sdh0_pmx_func1_fast { |
| 675 | pinctrl-single,pins = < |
| 676 | MMC1_DAT3 AF0 |
| 677 | MMC1_DAT2 AF0 |
| 678 | MMC1_DAT1 AF0 |
| 679 | MMC1_DAT0 AF0 |
| 680 | MMC1_CMD AF0 |
| 681 | >; |
| 682 | DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 683 | }; |
| 684 | sdh0_pmx_func2_fast: sdh0_pmx_func2_fast { |
| 685 | pinctrl-single,pins = < |
| 686 | MMC1_CLK AF0 |
| 687 | >; |
| 688 | DS_FAST1;PULL_NONE;EDGE_NONE; |
| 689 | }; |
| 690 | sdh1_pmx_func1_fast: sdh1_pmx_func1_fast { |
| 691 | pinctrl-single,pins = < |
| 692 | TDS_DIO13 AF0 /* WLAN_DAT3 */ |
| 693 | TDS_DIO14 AF0 /* WLAN_DAT2 */ |
| 694 | TDS_DIO15 AF0 /* WLAN_DAT1 */ |
| 695 | TDS_DIO16 AF0 /* WLAN_DAT0 */ |
| 696 | TDS_DIO17 AF0 /* WLAN_CMD */ |
| 697 | >; |
| 698 | DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 699 | }; |
| 700 | sdh1_pmx_func2_fast: sdh1_pmx_func2_fast { |
| 701 | pinctrl-single,pins = < |
| 702 | TDS_DIO18 AF0 /* WLAN_CLK */ |
| 703 | >; |
| 704 | DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 705 | }; |
| 706 | sdh1_pmx_func1: sdh1_pmx_func1 { |
| 707 | pinctrl-single,pins = < |
| 708 | TDS_DIO13 AF0 /* WLAN_DAT3 */ |
| 709 | TDS_DIO14 AF0 /* WLAN_DAT2 */ |
| 710 | TDS_DIO15 AF0 /* WLAN_DAT1 */ |
| 711 | TDS_DIO16 AF0 /* WLAN_DAT0 */ |
| 712 | TDS_DIO17 AF0 /* WLAN_CMD */ |
| 713 | >; |
| 714 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW; |
| 715 | }; |
| 716 | sdh1_pmx_func2: sdh1_pmx_func2 { |
| 717 | pinctrl-single,pins = < |
| 718 | TDS_DIO18 AF0 /* WLAN_CLK */ |
| 719 | >; |
| 720 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_LOW; |
| 721 | }; |
zw.wang | ad00beb | 2025-06-24 16:54:39 +0800 | [diff] [blame] | 722 | sdh1_pmx_func1_sleep_sdio: sdh1_pmx_func1_sleep_sdio { |
| 723 | pinctrl-single,pins = < |
| 724 | TDS_DIO13 AF1 |
| 725 | TDS_DIO14 AF1 |
| 726 | TDS_DIO15 AF1 |
| 727 | TDS_DIO16 AF1 |
| 728 | TDS_DIO17 AF1 |
| 729 | >; |
| 730 | MFP_PULL_DOWN; |
| 731 | }; |
| 732 | sdh1_pmx_func2_sleep_sdio: sdh1_pmx_func2_sleep_sdio { |
| 733 | pinctrl-single,pins = < |
| 734 | TDS_DIO18 AF1 |
| 735 | >; |
| 736 | MFP_PULL_DOWN; |
| 737 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 738 | sdh1_pmx_func3: sdh1_pmx_func3 { |
| 739 | pinctrl-single,pins = < |
| 740 | GPIO10 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */ |
| 741 | >; |
| 742 | MFP_PULL_DOWN; |
| 743 | }; |
| 744 | sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup { |
| 745 | pinctrl-single,pins = < |
| 746 | GPIO10 AF0 /* VCXO_REQ AF1 */ |
| 747 | >; |
| 748 | DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL; |
| 749 | }; |
| 750 | sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off { |
| 751 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 752 | /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */ |
| 753 | /* GPIO08 AF0 GPIO32 AF0 LDO_EN */ |
| 754 | MMC1_CD AF1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 755 | >; |
| 756 | MFP_PULL_DOWN; |
| 757 | }; |
| 758 | sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on { |
| 759 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 760 | /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */ |
| 761 | /* GPIO08 AF0 GPIO32 AF0 LDO_EN */ |
| 762 | MMC1_CD AF1 |
| 763 | >; |
| 764 | MFP_PULL_UP; |
| 765 | }; |
| 766 | |
| 767 | |
| 768 | mbtk_sdh_pmx_off: mbtk_sdh_pmx_off { |
| 769 | pinctrl-single,pins = < |
| 770 | VCXO_REQ AF1 //gpio125 wlan en |
| 771 | GPIO123 AF1 //wlan pwr en |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 772 | /*VCXO_OUT AF1 /*gpio127 wifi wake*/ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 773 | >; |
| 774 | MFP_PULL_DOWN; |
| 775 | }; |
| 776 | mbtk_sdh_pmx_on: mbtk_sdh_pmx_on { |
| 777 | pinctrl-single,pins = < |
| 778 | VCXO_REQ AF1 //gpio125 wlan en |
| 779 | GPIO123 AF1 //wlan pwr en |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 780 | /*VCXO_OUT AF1 /*gpio127 wifi wake*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 781 | >; |
| 782 | MFP_PULL_UP; |
| 783 | }; |
| 784 | alc5616_pmx_func1: alc5616_pmx_func1 { |
| 785 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 786 | /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 787 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
| 788 | >; |
| 789 | MFP_DEFAULT; |
| 790 | }; |
| 791 | alc5616_pmx_func2: alc5616_pmx_func2 { |
| 792 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 793 | /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */ |
| 794 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
| 795 | >; |
| 796 | MFP_DEFAULT; |
| 797 | }; |
| 798 | |
| 799 | es8311_pa_func1: es8311_pa_func1 { |
| 800 | pinctrl-single,pins = < |
| 801 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
yu.dong | b3e4937 | 2025-06-23 23:57:56 -0700 | [diff] [blame] | 802 | GPIO54 AF0 /* CODEC_VDDD_EN */ |
| 803 | GPIO24 AF0 /* NAD_PA_PWR_EN */ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 804 | >; |
| 805 | MFP_DEFAULT; |
| 806 | }; |
| 807 | es8311_pa_func2: es8311_pa_func2 { |
| 808 | pinctrl-single,pins = < |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 809 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
yu.dong | b3e4937 | 2025-06-23 23:57:56 -0700 | [diff] [blame] | 810 | GPIO54 AF0 /* CODEC_VDDD_EN */ |
| 811 | GPIO24 AF0 /* NAD_PA_PWR_EN */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 812 | >; |
| 813 | MFP_DEFAULT; |
| 814 | }; |
| 815 | audio_pa_pmx_func: audio_pa_pmx_func { |
| 816 | pinctrl-single,pins = < |
| 817 | GPIO14 AF0 /* PA */ |
| 818 | >; |
| 819 | MFP_DEFAULT; |
| 820 | }; |
| 821 | ecall_pmx_func: ecall_pmx_func { |
| 822 | pinctrl-single,pins = < |
| 823 | GPIO08 AF0 /* auto mode ecall */ |
| 824 | GPIO09 AF0 /* manual mode ecall */ |
| 825 | >; |
| 826 | MFP_DEFAULT; |
| 827 | }; |
| 828 | slic_pmx_func1: slic_pmx_func1 { |
| 829 | pinctrl-single,pins = < |
| 830 | GPIO20 AF0 /* SLIC_INT, GPIO20 */ |
| 831 | VCXO_OUT AF1 /* GPIO127, SLIC_3V3LDO_EN/LCD_BK_EN */ |
| 832 | >; |
| 833 | MFP_DEFAULT; |
| 834 | }; |
| 835 | slic_pmx_func2: slic_pmx_func2 { |
| 836 | pinctrl-single,pins = < |
| 837 | GPIO21 AF0 /* SLIC_RESET, GPIO21 */ |
| 838 | >; |
| 839 | MFP_DEFAULT; |
| 840 | }; |
| 841 | slic_pmx_func1_sleep: slic_pmx_func1_sleep { |
| 842 | pinctrl-single,pins = < |
| 843 | GPIO20 AF0 /* SLIC_INT, GPIO20 */ |
| 844 | >; |
| 845 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 846 | }; |
| 847 | |
| 848 | otg_vbus_func: otg_vbus_func { |
| 849 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 850 | /* VBUS_DRV AF1 GPIO[122] */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 851 | >; |
| 852 | DS_MEDIUM;PULL_DOWN;EDGE_NONE; |
| 853 | }; |
| 854 | |
| 855 | emac_pmx_func0: emac_pmx_func0 { |
| 856 | pinctrl-single,pins = < |
| 857 | GPIO00 AF1 /* GMAC1_RX_DV */ |
| 858 | GPIO01 AF1 /* GMAC1_RX_D0 */ |
| 859 | GPIO02 AF1 /* GMAC1_RX_D1 */ |
| 860 | GPIO03 AF1 /* GMAC1_RX_CLK */ |
| 861 | /* GPIO04 AF1 GMAC1_RX_D2 */ |
| 862 | /* GPIO05 AF1 GMAC1_RX_D3 */ |
| 863 | GPIO06 AF1 /* GMAC1_TX_D0 */ |
| 864 | GPIO07 AF1 /* GMAC1_TX_D1 */ |
| 865 | /* GPIO12 AF1 GMAC1_TX_CLK */ |
| 866 | /* GPIO13 AF1 GMAC1_TX_D2 */ |
| 867 | /* GPIO14 AF1 GMAC1_TX_D3 */ |
| 868 | GPIO15 AF1 /* GMAC1_TX_EN */ |
| 869 | GPIO16 AF1 /* GMAC1_TX_MDC */ |
| 870 | /* GPIO17 AF1 GMAC1_TX_MDIO */ |
| 871 | >; |
| 872 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 873 | }; |
| 874 | emac_pmx_func1: emac_pmx_func1 { |
| 875 | pinctrl-single,pins = < |
| 876 | GPIO04 AF1 /* GMAC1_RX_D2 */ |
| 877 | GPIO05 AF1 /* GMAC1_RX_D3 */ |
| 878 | GPIO12 AF1 /* GMAC1_TX_CLK */ |
| 879 | GPIO13 AF1 /* GMAC1_TX_D2 */ |
| 880 | GPIO14 AF1 /* GMAC1_TX_D3 */ |
| 881 | >; |
| 882 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 883 | }; |
| 884 | emac_pmx_func2: emac_pmx_func2 { |
| 885 | pinctrl-single,pins = < |
| 886 | GPIO17 AF1 /* GMAC1_TX_MDIO */ |
| 887 | GPIO18 AF1 /* GMAC1_TX_INT_N */ |
| 888 | >; |
| 889 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 890 | }; |
hj.shao | 213a35e | 2025-06-24 04:25:54 -0700 | [diff] [blame] | 891 | |
| 892 | emac_pmx_func0_slp: emac_pmx_func0_slp { |
| 893 | pinctrl-single,pins = < |
| 894 | GPIO00 AF1 /* GMAC1_RX_DV */ |
| 895 | GPIO01 AF1 /* GMAC1_RX_D0 */ |
| 896 | GPIO02 AF1 /* GMAC1_RX_D1 */ |
| 897 | GPIO03 AF1 /* GMAC1_RX_CLK */ |
| 898 | /* GPIO04 AF1 GMAC1_RX_D2 */ |
| 899 | /* GPIO05 AF1 GMAC1_RX_D3 */ |
| 900 | GPIO06 AF1 /* GMAC1_TX_D0 */ |
| 901 | GPIO07 AF1 /* GMAC1_TX_D1 */ |
| 902 | /* GPIO12 AF1 GMAC1_TX_CLK */ |
| 903 | /* GPIO13 AF1 GMAC1_TX_D2 */ |
| 904 | /* GPIO14 AF1 GMAC1_TX_D3 */ |
| 905 | GPIO15 AF1 /* GMAC1_TX_EN */ |
| 906 | GPIO16 AF1 /* GMAC1_TX_MDC */ |
| 907 | /* GPIO17 AF1 GMAC1_TX_MDIO */ |
| 908 | >; |
| 909 | DS_OFF;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 910 | }; |
| 911 | |
| 912 | emac_pmx_func1_slp: emac_pmx_func1_slp { |
| 913 | pinctrl-single,pins = < |
| 914 | GPIO04 AF1 /* GMAC1_RX_D2 */ |
| 915 | GPIO05 AF1 /* GMAC1_RX_D3 */ |
| 916 | GPIO12 AF1 /* GMAC1_TX_CLK */ |
| 917 | GPIO13 AF1 /* GMAC1_TX_D2 */ |
| 918 | GPIO14 AF1 /* GMAC1_TX_D3 */ |
| 919 | >; |
| 920 | DS_OFF;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 921 | }; |
| 922 | emac_pmx_func2_slp: emac_pmx_func2_slp { |
| 923 | pinctrl-single,pins = < |
| 924 | GPIO17 AF1 /* GMAC1_TX_MDIO */ |
| 925 | GPIO18 AF1 /* GMAC1_TX_INT_N */ |
| 926 | >; |
| 927 | DS_OFF;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 928 | }; |
| 929 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 930 | emac_pmx_func3: emac_pmx_func3 { |
| 931 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 932 | GPIO42 AF0 /* RESET */ |
hj.shao | fb3ba9b | 2025-06-19 02:53:56 -0700 | [diff] [blame] | 933 | //#LYNQ_MODFIY modify for task-1618 2025/6/19 start |
| 934 | GPIO32 AF0 /* POWER EN */ |
| 935 | //#LYNQ_MODFIY modify for task-1618 2025/6/19 end |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 936 | /* GPIO40 AF0 LDO_EN */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 937 | >; |
| 938 | DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 939 | }; |
| 940 | usim1_pmx_func: usim1_pmx_func { |
| 941 | pinctrl-single,pins = < |
yq.wang | 107f986 | 2025-05-12 15:44:50 +0800 | [diff] [blame] | 942 | PRI_TCK AF1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 943 | >; |
| 944 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 945 | }; |
| 946 | usim1_pmx_func_sleep: usim1_pmx_func_sleep { |
| 947 | pinctrl-single,pins = < |
yq.wang | 107f986 | 2025-05-12 15:44:50 +0800 | [diff] [blame] | 948 | PRI_TCK AF1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 949 | >; |
| 950 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 951 | }; |
| 952 | usim2_pmx_func: usim2_pmx_func { |
| 953 | pinctrl-single,pins = < |
| 954 | GPIO44 AF0 |
| 955 | >; |
| 956 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 957 | }; |
| 958 | usim2_pmx_func_sleep: usim2_pmx_func_sleep { |
| 959 | pinctrl-single,pins = < |
| 960 | GPIO44 AF0 |
| 961 | >; |
| 962 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 963 | }; |
| 964 | pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off { |
| 965 | pinctrl-single,pins = < |
| 966 | GPIO42 AF0 /* PERST_N */ |
| 967 | GPIO24 AF0 /* DC_EN */ |
| 968 | >; |
| 969 | MFP_PULL_DOWN; |
| 970 | }; |
| 971 | pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on { |
| 972 | pinctrl-single,pins = < |
| 973 | GPIO42 AF0 /* PERST_N */ |
| 974 | GPIO24 AF0 /* DC_EN */ |
| 975 | >; |
| 976 | MFP_PULL_UP; |
| 977 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 978 | pin_func_work: pin_func_work { |
| 979 | pinctrl-single,pins = < |
| 980 | |
| 981 | GPIO08 AF0 /*T108 status led* / |
| 982 | |
| 983 | VBUS_DRV AF2 /*32k*/ |
| 984 | |
| 985 | |
| 986 | GPIO46 AF0 /*wifi en*/ |
| 987 | |
| 988 | GPIO19 AF0 /*bt en*/ |
| 989 | |
| 990 | >; |
| 991 | MFP_DEFAULT; |
| 992 | }; |
| 993 | |
| 994 | |
| 995 | sc_ext_int0: sc_ext_int0 { |
| 996 | pinctrl-single,pins = < |
| 997 | GPIO21 AF0 |
| 998 | >; |
| 999 | DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL; |
| 1000 | }; |
| 1001 | sc_ext_int1: sc_ext_int1 { |
| 1002 | pinctrl-single,pins = < |
| 1003 | GPIO22 AF0 |
| 1004 | >; |
| 1005 | MFP_DEFAULT; |
| 1006 | }; |
| 1007 | |
| 1008 | sc_ext_int2: sc_ext_int2 { |
| 1009 | pinctrl-single,pins = < |
| 1010 | GPIO23 AF0 |
| 1011 | >; |
| 1012 | MFP_DEFAULT; |
| 1013 | }; |
| 1014 | |
| 1015 | |
| 1016 | sc_ext_int3: sc_ext_int3 { |
| 1017 | pinctrl-single,pins = < |
| 1018 | GPIO24 AF0 |
| 1019 | >; |
| 1020 | MFP_DEFAULT; |
| 1021 | }; |
| 1022 | |
| 1023 | |
| 1024 | mbtk_plat_irq_func: mbtk_plat_irq_func { |
| 1025 | pinctrl-single,pins = < |
| 1026 | |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1027 | /*GPIO21 AF0 |
| 1028 | GPIO22 AF0 */ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1029 | GPIO23 AF0 |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 1030 | GPIO24 AF0 |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1031 | |
| 1032 | >; |
| 1033 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 1034 | }; |
| 1035 | mbtk_plat_irq_func_sleep: mbtk_plat_irq_func_sleep { |
| 1036 | pinctrl-single,pins = < |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1037 | /*GPIO21 AF0 |
| 1038 | GPIO22 AF0*/ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1039 | GPIO23 AF0 |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 1040 | GPIO24 AF0 |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1041 | >; |
| 1042 | DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL; |
| 1043 | }; |
| 1044 | |
| 1045 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1046 | gpiokey_pmx_func: gpiokey_pmx_func { |
| 1047 | pinctrl-single,pins = < |
| 1048 | GPIO09 AF0 |
| 1049 | >; |
| 1050 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 1051 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1052 | |
lichengzhang | b746a89 | 2025-06-24 15:41:08 +0800 | [diff] [blame] | 1053 | /*for ssp2 is not in use, it needs to be used as a regular gpio,default state is input and low*/ |
| 1054 | gpiokey_ssp2_func: gpiokey_ssp2_func { |
| 1055 | pinctrl-single,pins = < |
| 1056 | GPIO37 AF0 /* TXD */ |
| 1057 | GPIO38 AF0 /* SCLK */ |
| 1058 | GPIO39 AF0 /* FRM */ |
| 1059 | GPIO40 AF0 /* RXD */ |
| 1060 | >; |
| 1061 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 1062 | }; |
| 1063 | |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1064 | wake_pmx_func1: wake_pmx_func1 { |
| 1065 | pinctrl-single,pins = < |
| 1066 | USB_ID AF1 |
| 1067 | >; |
| 1068 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 1069 | }; |
| 1070 | |
hong.liu | f241688 | 2025-05-23 20:41:06 -0700 | [diff] [blame] | 1071 | led_pmx_func1: led_pmx_func1 { |
| 1072 | pinctrl-single,pins = < |
| 1073 | GPIO08 AF0 |
| 1074 | >; |
| 1075 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 1076 | }; |
| 1077 | |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1078 | |
| 1079 | wake_pmx_func: wake_pmx_func { |
| 1080 | pinctrl-single,pins = < |
| 1081 | PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/ |
| 1082 | |
| 1083 | PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/ |
| 1084 | GPIO41 AF0 |
| 1085 | PRI_TDO AF1 /*GPIO120*/ |
| 1086 | |
| 1087 | |
| 1088 | >; |
| 1089 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 1090 | }; |
| 1091 | wake_pmx_func_sleep: wake_pmx_func_sleep { |
| 1092 | pinctrl-single,pins = < |
| 1093 | PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/ |
| 1094 | |
| 1095 | PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/ |
| 1096 | GPIO41 AF0 |
| 1097 | PRI_TDO AF1 /*GPIO120*/ |
| 1098 | |
| 1099 | >; |
| 1100 | DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL; |
| 1101 | }; |
| 1102 | usb_id_pinmux: usb_id_pinmux { |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1103 | pinctrl-single,pins = < |
| 1104 | USB_ID AF1/* usbid-gpio99 */ |
| 1105 | >; |
| 1106 | DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE; |
| 1107 | }; |
| 1108 | usb_id_pinmux_slp: usb_id_pinmux_slp { |
| 1109 | pinctrl-single,pins = < |
| 1110 | USB_ID AF1 /* usbid-gpio99 */ |
| 1111 | >; |
| 1112 | DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE; |
| 1113 | }; |
| 1114 | usb_host_pinmux: usb_host_pinmux { |
| 1115 | pinctrl-single,pins = < |
| 1116 | VBUS_DRV AF1 /* gpio-122 */ |
| 1117 | >; |
| 1118 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE; |
| 1119 | }; |
| 1120 | i2s_func: i2s_func { |
| 1121 | pinctrl-single,pins = < |
| 1122 | GPIO25 AF2 |
| 1123 | GPIO26 AF2 |
| 1124 | GPIO27 AF2 |
| 1125 | GPIO28 AF2 |
| 1126 | >; |
| 1127 | MFP_DEFAULT; |
| 1128 | }; |
| 1129 | i2s_gpio: i2s_gpio { |
| 1130 | pinctrl-single,pins = < |
| 1131 | GPIO25 AF0 |
| 1132 | GPIO26 AF0 |
| 1133 | GPIO27 AF0 |
| 1134 | GPIO28 AF0 |
| 1135 | >; |
| 1136 | MFP_LPM_FLOAT; |
| 1137 | }; |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1138 | sensors_int:sensors_int { |
| 1139 | pinctrl-single,pins = < |
| 1140 | GPIO22 AF0 |
| 1141 | >; |
| 1142 | MFP_PULL_DOWN; |
| 1143 | }; |
| 1144 | sensors_csb:sensors_csb { |
| 1145 | pinctrl-single,pins = < |
| 1146 | VCXO_OUT AF1 |
| 1147 | >; |
| 1148 | DS_MEDIUM;PULL_UP;EDGE_NONE; |
| 1149 | }; |
yu.dong | 23a7d13 | 2025-06-24 10:47:01 -0700 | [diff] [blame] | 1150 | sensors_sleep:sensors_sleep { |
| 1151 | pinctrl-single,pins = < |
| 1152 | GPIO22 AF0 |
| 1153 | VCXO_OUT AF1 |
| 1154 | >; |
| 1155 | DS_OFF;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 1156 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1157 | }; |
| 1158 | |
| 1159 | ssp0: spi@d401b000 { |
| 1160 | status = "okay"; |
| 1161 | pinctrl-names = "default"; |
| 1162 | pinctrl-0 = <&ssp0_pmx_func>; |
| 1163 | asr,spi-inc-mode; |
| 1164 | #ifdef CONFIG_FB_SPI_LCD |
| 1165 | /* this enhancemnet feature is not suitable for |
| 1166 | 3 line 9bits spi lcd. */ |
| 1167 | /* asr,ssp-enhancement; */ |
| 1168 | |
| 1169 | lcd: spidev@0 { |
| 1170 | #address-cells = <1>; |
| 1171 | #size-cells = <1>; |
| 1172 | compatible = "spilcd"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1173 | // pinctrl-names = "default"; |
| 1174 | // pinctrl-0 = <&lcd_bl_func>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1175 | reg = <0>; |
| 1176 | /* ST7735: need to set spi-max-frequency to 26M |
| 1177 | * ST7789V: can set spi-max-frequency to 52M |
| 1178 | */ |
| 1179 | spi-max-frequency = <26000000>; |
| 1180 | xres = <128>; |
| 1181 | yres = <128>; |
| 1182 | bits = <8>; /* 8: 4line, 9: 3line */ |
| 1183 | rst_gpio = <&gpio 24 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1184 | // bl_gpio = <&gpio 126 0>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1185 | rs_gpio = <&gpio 22 0>; |
| 1186 | /* if comment the following statement, it means |
| 1187 | * the avdd is sit on the "always-on" ldo. |
| 1188 | */ |
| 1189 | /* avdd-supply = <&LDO1>; */ |
| 1190 | }; |
| 1191 | #else |
| 1192 | /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */ |
| 1193 | slic: spidev@0{ |
| 1194 | #address-cells = <1>; |
| 1195 | #size-cells = <1>; |
| 1196 | compatible = "asr,slic"; |
| 1197 | reg = <0>; |
| 1198 | spi-cpol; |
| 1199 | spi-cpha; |
| 1200 | spi-max-frequency = <6500000>; |
| 1201 | }; |
| 1202 | #endif |
| 1203 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1204 | ssp2: spi@d401c000{ |
lichengzhang | b746a89 | 2025-06-24 15:41:08 +0800 | [diff] [blame] | 1205 | status = "disabled"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1206 | pinctrl-names = "default"; |
| 1207 | pinctrl-0 = <&ssp2_pmx_func>; |
| 1208 | asr,spi-inc-mode; |
| 1209 | cs-gpios = <&gpio 39 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1210 | mbtk: spidev@0{ |
| 1211 | compatible = "asr,spidev"; |
| 1212 | reg = <0>; |
| 1213 | status = "okay"; |
| 1214 | spi-cpol; |
| 1215 | spi-cpha; |
| 1216 | spi-max-frequency = <6500000>; |
| 1217 | }; |
| 1218 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1219 | twsi0: i2c@d4011000 { |
| 1220 | status= "okay"; |
yu.dong | 23a7d13 | 2025-06-24 10:47:01 -0700 | [diff] [blame] | 1221 | pinctrl-names = "default","gpio","sleep"; |
| 1222 | pinctrl-2 = <&twsi0_pmx_sleep>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1223 | alc5616@1b { |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1224 | status= "disabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1225 | compatible = "asrmicro,alc5616"; |
| 1226 | reg = <0x1b>; |
| 1227 | pinctrl-names = "default", "sleep"; |
| 1228 | pinctrl-0 = <&alc5616_pmx_func1>; |
| 1229 | pinctrl-1 = <&alc5616_pmx_func2>; |
| 1230 | clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>; |
| 1231 | clock-names = "i2s_sys_clk"; |
| 1232 | #if 0 |
| 1233 | 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */ |
| 1234 | irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */ |
| 1235 | #else |
| 1236 | irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */ |
| 1237 | #endif |
| 1238 | }; |
| 1239 | |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1240 | nau8810@1a { |
| 1241 | compatible = "marvell,nau8810"; |
| 1242 | clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>; |
| 1243 | clock-names = "i2s_sys_clk"; |
| 1244 | |
| 1245 | |
| 1246 | pinctrl-names = "default"; |
| 1247 | pinctrl-0 = <&es8311_pa_func1>; |
| 1248 | pinctrl-1 = <&es8311_pa_func2>; |
| 1249 | reg = <0x1a>; |
| 1250 | status= "disabled"; |
| 1251 | }; |
| 1252 | |
| 1253 | es8311@18 { |
| 1254 | compatible = "ambarella,es8311"; |
| 1255 | reg = <0x18>; |
| 1256 | clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>; |
| 1257 | clock-names = "i2s_sys_clk"; |
| 1258 | |
| 1259 | pinctrl-names = "default"; |
| 1260 | pinctrl-0 = <&es8311_pa_func1>; |
| 1261 | pinctrl-1 = <&es8311_pa_func2>; |
yu.dong | b3e4937 | 2025-06-23 23:57:56 -0700 | [diff] [blame] | 1262 | gpios = <&gpio 54 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1263 | |
| 1264 | // gpios = <&gpio 21 0>, |
| 1265 | // <&gpio 23 0>, |
| 1266 | // <&gpio 24 0>, |
| 1267 | // <&gpio 22 0>; |
| 1268 | |
| 1269 | status= "okay"; |
| 1270 | }; |
| 1271 | |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1272 | asm330lhhx-imu@0x6a { |
| 1273 | compatible = "st,asm330lhhx"; |
| 1274 | reg = <0x6b>; |
yu.dong | 23a7d13 | 2025-06-24 10:47:01 -0700 | [diff] [blame] | 1275 | pinctrl-names = "default", "sleep"; |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1276 | pinctrl-0 = <&sensors_int &sensors_csb>; |
yu.dong | 23a7d13 | 2025-06-24 10:47:01 -0700 | [diff] [blame] | 1277 | pinctrl-1 = <&sensors_sleep>; |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1278 | interrupt-parent = <&gpio>; |
| 1279 | interrupts = <22 1>; |
| 1280 | //interrupts = <22>; |
| 1281 | vddio-supply = <&sensors_vddio>; |
| 1282 | //vdd-supply = <&sensors_vdd>; |
| 1283 | st,int-pin = <1>; |
| 1284 | //st,mlc-int-pin = <2>; |
| 1285 | mount-matrix = "1", "0", "0", |
| 1286 | "0", "1", "0", |
| 1287 | "0", "0", "1"; |
| 1288 | }; |
yu.dong | b39db3e | 2025-06-06 03:15:42 -0700 | [diff] [blame] | 1289 | /* AWINIC AW87XXX Smart K PA */ |
| 1290 | aw87xxx_pa@58 { |
| 1291 | compatible = "awinic,aw87xxx_pa"; |
| 1292 | reg = <0x58>; |
| 1293 | reset-gpio = <&gpio 24 0>; |
| 1294 | dev_index = < 0 >; |
| 1295 | status = "okay"; |
| 1296 | }; |
| 1297 | /* AWINIC AW87XXX Smart K PA End */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1298 | /* |
| 1299 | pmic4: 88pm805@38 { |
| 1300 | compatible = "marvell,88pm805"; |
| 1301 | reg = <0x38>; |
| 1302 | }; |
| 1303 | */ |
| 1304 | }; |
| 1305 | twsi1: i2c@d4010800 { |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1306 | #if 1 |
yu.dong | 23a7d13 | 2025-06-24 10:47:01 -0700 | [diff] [blame] | 1307 | pinctrl-names = "default","gpio","sleep"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1308 | pinctrl-0 = <&twsi1_pmx_func>; |
| 1309 | pinctrl-1 = <&twsi1_pmx_gpio>; |
yu.dong | 23a7d13 | 2025-06-24 10:47:01 -0700 | [diff] [blame] | 1310 | pinctrl-2 = <&twsi1_pmx_sleep>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1311 | i2c-gpio = <&gpio 10 0 &gpio 11 0>; |
| 1312 | #endif |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1313 | status= "okay"; |
| 1314 | //nau8810@1a { |
| 1315 | // compatible = "marvell,nau8810"; |
| 1316 | // reg = <0x1a>; |
| 1317 | //}; |
| 1318 | |
| 1319 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1320 | }; |
| 1321 | twsi2: i2c@d4037000 { |
| 1322 | status = "okay"; |
| 1323 | |
| 1324 | pmic4: 88pm805@38 { |
| 1325 | compatible = "marvell,88pm805"; |
| 1326 | reg = <0x38>; |
| 1327 | }; |
| 1328 | |
| 1329 | pmic5: pm802@0 { |
| 1330 | compatible = "asr,pm802"; |
| 1331 | reg = <0x00>; |
| 1332 | interrupts = <4>; |
| 1333 | interrupt-parent = <&intc>; |
| 1334 | interrupt-controller; |
| 1335 | #interrupt-cells = <1>; |
| 1336 | chg_irq_from_exton; |
| 1337 | scs-int-active-high; |
| 1338 | battery { |
| 1339 | compatible = "asr,pm802-bat"; |
| 1340 | status = "disabled"; |
| 1341 | |
| 1342 | online-gpadc = <1>; |
| 1343 | temperature-gpadc = <1>; |
| 1344 | |
| 1345 | hi-volt-online = <1150>; /* mV */ |
| 1346 | lo-volt-online = <20>; /* mV */ |
| 1347 | hi-volt-temp = <1150>; /* mV */ |
| 1348 | lo-volt-temp = <200>; /* mV */ |
| 1349 | |
| 1350 | sw-fg-use-ntc; |
| 1351 | full-capacity = <2050>; /* mAh */ |
| 1352 | r1-resistor = <40>; /* mohm */ |
| 1353 | r2-resistor = <30>; /* mohm */ |
| 1354 | rs-resistor = <120>; /* mohm */ |
| 1355 | roff-resistor = <0>; /* mohm */ |
| 1356 | roff-initial-resistor = <0>; /* mohm */ |
| 1357 | |
| 1358 | times-in-zero-degree = <1>; |
| 1359 | offset-in-zero-degree = <0>; |
| 1360 | |
| 1361 | times-in-ten-degree = <2>; |
| 1362 | offset-in-ten-degree = <100>; |
| 1363 | |
| 1364 | power-off-threshold = <3350>; /* mV */ |
| 1365 | safe-power-off-threshold = <3200>; /* mV */ |
| 1366 | |
| 1367 | online-gp-bias-curr = <11>; /* uA */ |
| 1368 | |
| 1369 | soc-ramp-up-interval = <150>; /* s */ |
| 1370 | /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */ |
| 1371 | tbat-threshold = <20 0 10 40 45 55>; /* ohm */ |
| 1372 | ntc-table-size = <88>; |
| 1373 | stop-chg-for-vbatmeas; |
| 1374 | /* -24C, -23C, ..., 62C, 63C */ |
| 1375 | ntc-table = < |
| 1376 | 89680 85130 80840 76790 72970 69360 65960 62740 |
| 1377 | 59700 56830 54130 51530 49100 46800 44610 42550 |
| 1378 | 40590 38730 36970 35300 33710 32210 30780 29420 |
| 1379 | 28130 26910 25750 24640 23590 22580 21630 20720 |
| 1380 | 19860 19030 18250 17500 16790 16110 15460 14840 |
| 1381 | 14250 13690 13150 12640 12150 11680 11230 10800 |
| 1382 | 10390 10000 9620 9270 8920 8590 8280 7980 |
| 1383 | 7690 7410 7150 6890 6650 6410 6190 5970 |
| 1384 | 5770 5570 5380 5190 5020 4850 4680 4530 |
| 1385 | 4380 4230 4100 3960 3830 3710 3590 3480 |
| 1386 | 3370 3260 3160 3060 2960 2870 2780 2700 |
| 1387 | >; |
| 1388 | }; |
| 1389 | usb { |
| 1390 | status = "disabled"; |
| 1391 | vbus_gpio = <0xff>; /* set_vbus */ |
| 1392 | id-gpadc = <0xff>; /* usb-id */ |
| 1393 | vchg-from-exton = <1>; |
| 1394 | vbus-detect = <1>; /* vbus-irq */ |
| 1395 | get-vbus = <1>; /* get-vbus */ |
| 1396 | }; |
| 1397 | }; |
| 1398 | pmic6: pm803@30 { |
| 1399 | compatible = "asr,pm803"; |
| 1400 | reg = <0x30>; |
| 1401 | interrupts = <4>; |
| 1402 | interrupt-parent = <&intc>; |
| 1403 | interrupt-controller; |
| 1404 | #interrupt-cells = <1>; |
| 1405 | chg_irq_from_exton; |
| 1406 | scs-int-active-high; |
| 1407 | battery { |
| 1408 | compatible = "asr,pm803-bat"; |
| 1409 | status = "disabled"; |
| 1410 | |
| 1411 | online-gpadc = <1>; |
| 1412 | temperature-gpadc = <1>; |
| 1413 | |
| 1414 | hi-volt-online = <1150>; /* mV */ |
| 1415 | lo-volt-online = <20>; /* mV */ |
| 1416 | hi-volt-temp = <1150>; /* mV */ |
| 1417 | lo-volt-temp = <200>; /* mV */ |
| 1418 | |
| 1419 | sw-fg-use-ntc; |
| 1420 | full-capacity = <2050>; /* mAh */ |
| 1421 | r1-resistor = <40>; /* mohm */ |
| 1422 | r2-resistor = <30>; /* mohm */ |
| 1423 | rs-resistor = <120>; /* mohm */ |
| 1424 | roff-resistor = <0>; /* mohm */ |
| 1425 | roff-initial-resistor = <0>; /* mohm */ |
| 1426 | |
| 1427 | times-in-zero-degree = <1>; |
| 1428 | offset-in-zero-degree = <0>; |
| 1429 | |
| 1430 | times-in-ten-degree = <2>; |
| 1431 | offset-in-ten-degree = <100>; |
| 1432 | |
| 1433 | power-off-threshold = <3350>; /* mV */ |
| 1434 | safe-power-off-threshold = <3200>; /* mV */ |
| 1435 | |
| 1436 | online-gp-bias-curr = <11>; /* uA */ |
| 1437 | |
| 1438 | soc-ramp-up-interval = <150>; /* s */ |
| 1439 | /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */ |
| 1440 | tbat-threshold = <20 0 10 40 45 55>; /* ohm */ |
| 1441 | ntc-table-size = <88>; |
| 1442 | stop-chg-for-vbatmeas; |
| 1443 | /* -24C, -23C, ..., 62C, 63C */ |
| 1444 | ntc-table = < |
| 1445 | 89680 85130 80840 76790 72970 69360 65960 62740 |
| 1446 | 59700 56830 54130 51530 49100 46800 44610 42550 |
| 1447 | 40590 38730 36970 35300 33710 32210 30780 29420 |
| 1448 | 28130 26910 25750 24640 23590 22580 21630 20720 |
| 1449 | 19860 19030 18250 17500 16790 16110 15460 14840 |
| 1450 | 14250 13690 13150 12640 12150 11680 11230 10800 |
| 1451 | 10390 10000 9620 9270 8920 8590 8280 7980 |
| 1452 | 7690 7410 7150 6890 6650 6410 6190 5970 |
| 1453 | 5770 5570 5380 5190 5020 4850 4680 4530 |
| 1454 | 4380 4230 4100 3960 3830 3710 3590 3480 |
| 1455 | 3370 3260 3160 3060 2960 2870 2780 2700 |
| 1456 | >; |
| 1457 | }; |
| 1458 | usb { |
| 1459 | status = "disabled"; |
| 1460 | vbus_gpio = <0xff>; /* set_vbus */ |
| 1461 | id-gpadc = <0xff>; /* usb-id */ |
| 1462 | vchg-from-exton = <1>; |
| 1463 | vbus-detect = <1>; /* vbus-irq */ |
| 1464 | get-vbus = <1>; /* get-vbus */ |
| 1465 | }; |
| 1466 | }; |
| 1467 | }; |
| 1468 | }; |
| 1469 | }; |
| 1470 | |
| 1471 | vcc_sdh1: sd-regulator { |
| 1472 | compatible = "regulator-fixed"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1473 | /*pinctrl-names = "default";*/ |
| 1474 | /*pinctrl-0 = <&sd_ldo_en>;*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1475 | regulator-name = "SDH1 VCC"; |
| 1476 | regulator-min-microvolt = <3300000>; |
| 1477 | regulator-max-microvolt = <3300000>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1478 | /* gpio = <&gpio 45 0>;*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1479 | enable-active-high; |
| 1480 | status = "okay"; |
| 1481 | }; |
| 1482 | |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1483 | sensors_vddio: imu-regulator { |
| 1484 | compatible = "regulator-fixed"; |
| 1485 | /*pinctrl-names = "default";*/ |
| 1486 | /*pinctrl-0 = <&sd_ldo_en>;*/ |
| 1487 | regulator-name = "IMU VDDIO"; |
| 1488 | gpio = <&gpio 21 0>; |
| 1489 | enable-active-high; |
| 1490 | status = "okay"; |
| 1491 | }; |
| 1492 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1493 | asr-rfkill { |
| 1494 | compatible = "asr,asr-rfkill"; |
| 1495 | pinctrl-names = "off", "on"; |
| 1496 | pinctrl-0 = <&sdh1_pmx_pd_rst_off>; |
| 1497 | pinctrl-1 = <&sdh1_pmx_pd_rst_on>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1498 | sd-host = <&sdh0>; |
| 1499 | //pd-gpio = <&gpio 90 0>; |
| 1500 | rst-gpio = <&gpio 90 0>; |
| 1501 | |
| 1502 | /*3v3-ldo-gpio = <&gpio 8 0>;*/ |
| 1503 | /*edge-wakeup-gpio = <&gpio 10 0>;*/ |
| 1504 | status = "okay"; |
| 1505 | }; |
| 1506 | |
| 1507 | mbtk-sdh{ |
| 1508 | compatible = "mbtk,mbtk-sdh"; |
| 1509 | pinctrl-names = "off", "on"; |
| 1510 | pinctrl-0 = <&mbtk_sdh_pmx_off>; |
| 1511 | pinctrl-1 = <&mbtk_sdh_pmx_on>; |
| 1512 | sd-host = <&sdh1>; |
| 1513 | 1v8-ldo-gpio = <&gpio 123 0>; |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1514 | //host-wakeup-wlan-gpio = <&gpio 127 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1515 | wlan_en_gpio = <&gpio 125 0>; |
| 1516 | status = "okay"; |
| 1517 | }; |
| 1518 | |
| 1519 | asr-gps { |
| 1520 | compatible = "asr,asr-gnss"; |
| 1521 | pinctrl-names = "default"; |
| 1522 | pinctrl-0 = <&gnss_clk_on>; |
| 1523 | enable_vctcxo_out1; |
| 1524 | host-wakeup-gnss-gpio = <&gpio 47 0>; |
| 1525 | /*gnss-wakeup-host-gpio = <&gpio 47 0>;*/ |
| 1526 | rst-gpio = <&gpio 45 0>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1527 | status = "okay"; |
| 1528 | }; |
| 1529 | |
| 1530 | pcie-rfkill { |
| 1531 | compatible = "mrvl,pcie-rfkill"; |
| 1532 | pinctrl-names = "off", "on"; |
| 1533 | pinctrl-0 = <&pcie_pmx_pd_rst_off>; |
| 1534 | pinctrl-1 = <&pcie_pmx_pd_rst_on>; |
| 1535 | rst-gpio = <&gpio 42 0>; |
| 1536 | 3v3-ldo-gpio = <&gpio 24 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1537 | status = "disabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1538 | }; |
| 1539 | |
| 1540 | sound { |
| 1541 | compatible = "ASRMICRO,asrmicro-snd-card"; |
| 1542 | ssp-controllers = <&ssp_dai1>; |
| 1543 | }; |
| 1544 | |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1545 | asr-adc { |
| 1546 | compatible = "asr,adc"; |
| 1547 | //pinctrl-names = "default"; |
| 1548 | //pinctrl-0 = <&pin_func_work>; |
| 1549 | status = "okay"; |
| 1550 | }; |
| 1551 | |
| 1552 | #if 0 |
| 1553 | |
| 1554 | mbtk_PlatIrq{ |
| 1555 | compatible = "mbtk,plat-irq"; |
| 1556 | pinctrl-names = "sc_irq0", "sc_irq1", "sc_irq2", "sc_irq3"; |
| 1557 | |
| 1558 | pinctrl-0 = <&sc_ext_int0>; |
| 1559 | pinctrl-1 = <&sc_ext_int1>; |
| 1560 | pinctrl-2 = <&sc_ext_int2>; |
| 1561 | pinctrl-3 = <&sc_ext_int3>; |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 1562 | status = "disabled"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1563 | }; |
| 1564 | |
| 1565 | #else |
| 1566 | |
| 1567 | mbtk_PlatIrq{ |
| 1568 | compatible = "mbtk,plat-irq"; |
| 1569 | pinctrl-names = "default", "sleep"; |
| 1570 | pinctrl-0 = <&mbtk_plat_irq_func>; |
| 1571 | pinctrl-1 = <&mbtk_plat_irq_func_sleep>; |
you.chen | 9824a89 | 2025-06-04 20:23:26 +0800 | [diff] [blame] | 1572 | //gpio_irq0 = <&gpio 21 0>; |
| 1573 | //gpio_irq1 = <&gpio 22 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1574 | gpio_irq2 = <&gpio 23 0>; |
| 1575 | gpio_irq3 = <&gpio 24 0>; |
yu.dong | ca721ca | 2025-06-04 07:21:21 -0700 | [diff] [blame] | 1576 | status = "disabled"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1577 | }; |
| 1578 | |
| 1579 | #endif |
| 1580 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1581 | ecall { |
| 1582 | compatible = "asr,ecall-event"; |
| 1583 | pinctrl-names = "default"; |
| 1584 | pinctrl-0 = <&ecall_pmx_func>; |
| 1585 | gpio-auto-ecall = <8>; |
| 1586 | gpio-manual-ecall = <9>; |
| 1587 | status = "disabled"; |
| 1588 | }; |
| 1589 | |
| 1590 | usim1: usim1 { |
| 1591 | compatible = "asr,usim1"; |
| 1592 | pinctrl-names = "default", "sleep"; |
| 1593 | pinctrl-0 = <&usim1_pmx_func>; |
| 1594 | pinctrl-1 = <&usim1_pmx_func_sleep>; |
yq.wang | 107f986 | 2025-05-12 15:44:50 +0800 | [diff] [blame] | 1595 | edge_detect_gpio = <119>; /* GPIO19: SIM detect pin */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1596 | status = "okay"; |
| 1597 | }; |
| 1598 | /* set okay for this node if usim2 is needed */ |
| 1599 | usim2: usim2 { |
| 1600 | compatible = "asr,usim2"; |
| 1601 | pinctrl-names = "default", "sleep"; |
| 1602 | pinctrl-0 = <&usim2_pmx_func>; |
| 1603 | pinctrl-1 = <&usim2_pmx_func_sleep>; |
| 1604 | edge_detect_gpio = <44>; /* GPIO44: SIM detect pin */ |
| 1605 | #ifdef CONFIG_ASR_DSDS |
| 1606 | status = "okay"; |
| 1607 | #else |
| 1608 | status = "disabled"; |
| 1609 | #endif |
| 1610 | }; |
| 1611 | gpio_keys { |
| 1612 | compatible = "gpio-keys"; |
| 1613 | #address-cells = <1>; |
| 1614 | #size-cells = <0>; |
| 1615 | /* autorepeat; */ |
| 1616 | pinctrl-names = "default"; |
lichengzhang | b746a89 | 2025-06-24 15:41:08 +0800 | [diff] [blame] | 1617 | pinctrl-0 = <&gpiokey_pmx_func &gpiokey_ssp2_func>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1618 | button@1 { |
| 1619 | label = "qrcode-key"; |
| 1620 | linux,code = <139>; /* KEY_MENU, refer to linux/input.h */ |
| 1621 | /* NOTE: |
| 1622 | * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB. |
| 1623 | * Customer SHOULD change it to any other gpios. |
| 1624 | * Because user may do the misoperation that |
| 1625 | * powerup with FDL key pressed, |
| 1626 | * then the borad will enter force download mode. |
| 1627 | */ |
| 1628 | gpios = <&gpio 9 1>; |
| 1629 | gpio-key,wakeup; |
| 1630 | }; |
| 1631 | }; |
| 1632 | |
| 1633 | audio_pa { |
| 1634 | compatible = "asrmicro,audio-pa"; |
| 1635 | pinctrl-names = "default"; |
| 1636 | pinctrl-0 = <&audio_pa_pmx_func>; |
| 1637 | pa-gpio = <&gpio 14 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1638 | status = "disabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1639 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1640 | mbtk_GpioWakeUp { |
| 1641 | compatible = "mbtk,GpioWakeUp"; |
| 1642 | pinctrl-names = "default", "sleep"; |
| 1643 | pinctrl-0 = <&wake_pmx_func &wake_pmx_func1>; |
| 1644 | pinctrl-1 = <&wake_pmx_func_sleep>; |
| 1645 | wakeup-in-gpio = <&gpio 118 0>; |
| 1646 | wakeup-out-gpio = <&gpio 117 0>; |
| 1647 | status = "okay"; |
| 1648 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1649 | |
hong.liu | f241688 | 2025-05-23 20:41:06 -0700 | [diff] [blame] | 1650 | |
| 1651 | dtsleds{ |
| 1652 | compatible = "gpio-leds"; |
| 1653 | pinctrl-names = "default"; |
| 1654 | pinctrl-0 = <&led_pmx_func1>; |
| 1655 | status = "okay"; |
| 1656 | led0{ |
| 1657 | label = "red"; |
| 1658 | gpios = <&gpio 8 0>; |
| 1659 | linux,default-trigger = "pattern"; |
| 1660 | led-pattern = "100:100:100"; |
hong.liu | f241688 | 2025-05-23 20:41:06 -0700 | [diff] [blame] | 1661 | |
yu.dong | 553c5fd | 2025-06-24 19:53:47 -0700 | [diff] [blame] | 1662 | default-state = "off"; |
hong.liu | f241688 | 2025-05-23 20:41:06 -0700 | [diff] [blame] | 1663 | }; |
| 1664 | |
| 1665 | // led1{ |
| 1666 | // label = "blue"; |
| 1667 | // gpios = <&gpio 99 0>; |
| 1668 | // linux,default-trigger = "timer"; |
| 1669 | // timer-delay-on = <100>; |
| 1670 | // timer-delay-off = <100>; |
| 1671 | // brightness-levels = <100>; |
| 1672 | // brightness-max = <100>; |
| 1673 | // default-state = "on"; |
| 1674 | // }; |
| 1675 | |
| 1676 | }; |
| 1677 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1678 | audio_regs { |
| 1679 | compatible = "ASRMICRO,audio-registers"; |
| 1680 | reg = <0xD4050044 0x4>; |
| 1681 | status = "okay"; |
| 1682 | }; |
| 1683 | |
| 1684 | nz3-slic { |
| 1685 | compatible = "asr,nz3-slic"; |
| 1686 | pinctrl-names = "default", "sleep"; |
| 1687 | pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>; |
| 1688 | pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>; |
| 1689 | rst-gpio = <&gpio 21 0>; |
| 1690 | edge-wakeup-gpio = <&gpio 20 0>; |
| 1691 | vdd-3v3-gpio = <&gpio 127 0>; |
| 1692 | status = "disabled"; |
| 1693 | }; |
| 1694 | microsemi-slic { |
| 1695 | compatible = "asr,microsemi-slic"; |
| 1696 | pinctrl-names = "default", "sleep"; |
| 1697 | pinctrl-0 = <&slic_pmx_func1>; |
| 1698 | pinctrl-1 = <&slic_pmx_func1_sleep>; |
| 1699 | edge-wakeup-gpio = <&gpio 20 0>; |
| 1700 | vdd-3v3-gpio = <&gpio 127 0>; |
| 1701 | status = "disabled"; |
| 1702 | }; |
| 1703 | maxlinear-slic { |
| 1704 | compatible = "asr,maxlinear-slic"; |
| 1705 | pinctrl-names = "default", "sleep"; |
| 1706 | pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>; |
| 1707 | pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>; |
| 1708 | rst-gpio = <&gpio 21 0>; |
| 1709 | edge-wakeup-gpio = <&gpio 20 0>; |
| 1710 | vdd-3v3-gpio = <&gpio 127 0>; |
| 1711 | status = "disabled"; |
| 1712 | }; |
| 1713 | /* deprecated, move to mfpr@d401e000 |
| 1714 | lpm-board-cfg { |
| 1715 | compatible = "asr,lpm-board-cfg"; |
| 1716 | wakeup-state-d1pp = <0x1>; |
| 1717 | udr-mfpr-config = <0x1B0 0xA040 0x0 |
| 1718 | 0x1B4 0xA040 0x0>; |
| 1719 | }; |
| 1720 | */ |
| 1721 | }; |
| 1722 | #ifdef CONFIG_ASR_DSDS |
| 1723 | #include "asr_pm802_2usim.dtsi" |
| 1724 | #include "88pm805.dtsi" |
| 1725 | #include "asr_pm803_2usim.dtsi" |
| 1726 | #else |
| 1727 | #include "asr_pm802.dtsi" |
| 1728 | #include "88pm805.dtsi" |
| 1729 | #include "asr_pm803.dtsi" |
| 1730 | #endif |
| 1731 | |
| 1732 | #ifdef CONFIG_AB_SYSTEM |
| 1733 | #include "asr1806_ab_flash_layout.dtsi" |
| 1734 | #else |
| 1735 | #include "asr1806_flash_layout.dtsi" |
| 1736 | #endif |